DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Other Refs: Shallal (US 10241727) – Dram Flash NVM devices for improved inter-memory data transmission.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-13, 14-21 are rejected under 35 U.S.C. 103 as being unpatentable over Nale (US 20170199830, hereinafter “Nale830”) and in view of Nale (US 20210216238, hereinafter “Nale238”) and further in view of Vergis (US 20180061478) and Runas (UC 5906003)
Claim 1. Nale830 discloses An apparatus (eg., 0049 Fig. 4A-B, DIMM 400) comprising:
a command/address (CA) bus (eg., 0049 - command bus 430-1);
multiple dynamic random access (DRAM) devices coupled to the CA bus (eg., 0034 - memory devices 122-1 to 122-n at DIMMs 120-1 to 120-n may include all or combinations of types of volatile or non-volatile memory.; 0120 - volatile memory may include DRAM.; 0028 - respective command buses 130-1 to 130-n ); and
Nale830 does not disclose, but Nale238 discloses
a registering clock driver (RCD) to time division multiplex separate first commands for a first group of the DRAM devices from second commands for a second group of the DRAM devices on the CA bus, (eg., 0021 Fig. 4 RCD 402 of FIG. 4 ; 0021 - multiplexers 410 before being decoded and re-driven; )
wherein the RCD is to issue two column address strobe (CAS) commands with a single read command to exchange a double amount of data per DRAM device per read command (eg., 0019 - doubling the number of CA and CS signals ; [0012] A memory transaction over the A sub-channel 101a can therefore target any one of the four different ranks associated with the pair of A pseudo channels, and, likewise, a memory transaction over the B sub-channel 101b can therefore target any one of the four different ranks associated with the pair of B pseudo channels.)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the Dimm with DRAMs as disclosed by Nale830 with Nale238, providing the benefit of an improved RCD chip design 402 that can be used for either the X8 DIMM 100 (see Nale238, 0021) use of pseudo channels extends the LRDIMM architecture to an extended LRDIMM (0027).
Nale830 in view of Nale238 does not disclose, but Vergis discloses
including a first group of the DRAM devices to respond together to first commands and a second group of the DRAM devices to respond together to second commands (eg., 0046 Fig. 2 - multiple memory devices or DRAM devices 222 and 224.; 0052 - C/A bus 244 carries the command signals of C/A bus 242 to DRAMs 222. Thus, from one perspective, C/A bus 242 and C/A bus 244 can be considered the same command bus, such as having two portions);
with time division multiplexing (eg., 0074 - interface logic includes multiplexers to multiplex the DDR command signals )
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the Dimm with DRAMs as disclosed by Nale830 with Nale238, with Vergis, providing the benefit memory subsystem includes a command address bus that has a bus width mismatch with the memory devices. The command bus from the host is narrower and operates at a higher data rate than the native command bus interface of the memory devices. The memory subsystem includes logic to receive the higher data rate command signals and forward them to the memory devices at the lower or standard data rate. The logic can thus be an interface for a command bus with a lower number of signal lines and a higher data rate to a command bus with a higher number of signal lines and a lower data rate (see Vergis, 0018).
Nale830 in view of Nale238 and Vergis does not disclose, but Runas discloses
in response to receipt of a first read command for the first group of the DRAM devices, the RCD is to issue two separate column address strobe (CAS) commands for the first read command to read two portions of data per DRAM device per read command (eg., col 7:3-10 Fig. 4 - Location 1 column address bits are sent to the DRAM device and two consecutive CAS active (low) periods are exercised which cause bits 0-15 and bits 16-31 of a 32-bit double word to be read out of the DRAM device; col 6:32-37 - Because the two data words were located in consecutive locations within the same row, only one row address was needed. However, two separate column addresses were required in order to select the two individual data words )
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the Dimm with DRAMs as disclosed by Nale830 with Nale238 and Vergis, with Runas, providing the benefit of improved memory circuits and processing systems using the improved memory circuits that can more easily access large data words in system memory. In particular, there is a need for processing systems and memory devices that can more easily access large data words in system memory by configuring the data I/O width of the memory devices "on the fly." (see Runas, col 2:21-27).
Claim 2. Nale830 does not disclose, but Nale238 discloses
wherein the RCD is to drive two CA buses per channel, to provide four pseudo channels per channel (eg., [0011] Each of the A and B sub-channels 101a, 101b can be further divided into two additional pseudo channels where each pseudo channel provides for two ranks of memory chips that implement a DDR5 data interface.; [0012] A memory transaction over the A sub-channel 101a can therefore target any one of the four different ranks associated with the pair of A pseudo channels, and, likewise, a memory transaction over the B sub-channel 101b can therefore target any one of the four different ranks associated with the pair of B pseudo channels).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the Dimm with DRAMs as disclosed by Nale830 with Nale238, providing the benefit of an improved RCD chip design 402 that can be used for either the X8 DIMM 100 (see Nale238, 0021) use of pseudo channels extends the LRDIMM architecture to an extended LRDIMM (0027).
Claim 3. Nale830 discloses further comprising:
a printed circuit board (PCB) having DRAM devices on a front side of the PCB and on a back side of the PCB (eg., 0034 – memory devices 122-1 at DIMM 120-1 may include volatile memory (e.g., DRAM) on a front; 0034, 0049 Fig. 4B - a back or second side. In other examples, a hybrid DIMM may include combinations of non-volatile and volatile types of memory for memory devices 122-1 on either side of DIMM 120-1. In other examples, all memory devices 122-1 may be either volatile types of memory or non-volatile types of memory),
with a pseudo channel having data bus interfaces of DRAM devices on the front side and on the back side multiplexed to a same data buffer (eg., 0049 - Multi-port register 420 may serve as buffer to at least temporarily store CACs to be routed via respective memory devices 410-1 and 410-2 to facilitate or enable access to these memory devices),
with extra chip select signal lines between the RCD and the multiple DRAM devices as compared to a number of chip select signal lines between a host memory controller and the RCD (eg., 0075 - Multi-port register 1010 may include logic and/or features to determine which memory device data bus based on information from the host computing device that indicates which rank is being access via chip selects or other means. For write operations or cycles, buffers 1030-1 to 1030-10 may either drive host data onto both sets of memory device data buses,).
Claim 4. Nale830 discloses wherein the RCD is to receive a single CAS command with the first read command, and issue the two CAS commands to the DRAM devices (eg., 0049 Fig. 4A-B - multiple command buses including a command bus 430-1 and a command bus 430-2 may be routed through multi-port register 420 and then to respective memory devices 410-1 and memory devices 410-2. Multi-port register 420 may serve as buffer to at least temporarily store CACs to be routed via respective memory devices 410-1 and 410-2 to facilitate or enable access to these memory devices.).
Claim 5. Nale830 discloses further comprising: a data bus to couple to a host memory controller (eg., 0031 Fig 1 - data channels 140-1 coupled with DIMM 120-1.); and
multiple data buffers coupled between the multiple DRAM devices and the host memory controller on the data bus (eg., 0072 - FIG. 10A, buffers 1030-1 to 1030-10 may be data buffers).
Claim 6. Nale830 does not disclose, but Nale238 discloses
a data mask signal per 8 signal lines of the data bus, wherein the multiple DRAM devices are to provide error correction coding (ECC) information to the host memory controller via the data mask signal (eg., 0010 Fig. 1 - X8 memory chips. As is known in the art, a single Joint Electron Device Engineering Council (JEDEC) dual data rate 5 (DDR5) channel is composed of two separate sub-channels (an “A” sub-channel 101a and a “B” sub-channel 101b). Each of the A and B sub-channels include a respective 40 bit (b) wide data bus and command/address and chip (“CA_&_CS”) signal lines (the 40b data bus includes 32b of data and 8b of error correction code (ECC)).)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the Dimm with DRAMs as disclosed by Nale830 with Nale238, providing the benefit of an improved RCD chip design 402 that can be used for either the X8 DIMM 100 (see Nale238, 0021) use of pseudo channels extends the LRDIMM architecture to an extended LRDIMM (0027).
Claim 8. Nale830 does not disclose, but Nale238 discloses
wherein each DRAM device has a x8 data bus interface to exchange 8 data bits per unit interval with the data bus (eg., 0010 Fig. 1 - X8 memory chips. As is known in the art, a single Joint Electron Device Engineering Council (JEDEC) dual data rate 5 (DDR5) channel is composed of two separate sub-channels (an “A” sub-channel 101a and a “B” sub-channel 101b). Each of the A and B sub-channels include a respective 40 bit (b) wide data bus and command/address and chip (“CA_&_CS”) signal lines (the 40b data bus includes 32b of data and 8b of error correction code (ECC)).)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the Dimm with DRAMs as disclosed by Nale830 with Nale238, providing the benefit of an improved RCD chip design 402 that can be used for either the X8 DIMM 100 (see Nale238, 0021) use of pseudo channels extends the LRDIMM architecture to an extended LRDIMM (0027).
Claim 9. Nale830 discloses
wherein each data buffer multiplexes data from DRAM devices of different pseudo channels (eg., 0072 - each memory device included in memory devices 1022-1 may be coupled with respective buffers 1030-1 to 1030-10 via a 4 b data bus. As shown in FIG. 10A, data channel 0 has ten memory devices separately coupled to data channel 0 via 4 b data buses and data channel 2 also has ten memory devices separately coupled to data channel. So each data channel may compose separate 40 b data channels. ).
Claim 10. Nale830 discloses
wherein each data buffer multiplexes data from DRAM devices of a single pseudo channel (eg., 0072 - each memory device included in memory devices 1022-1 may be coupled with respective buffers 1030-1 to 1030-10 via a 4 b data bus.)
Claim 11. Nale830 in view of Nale238 does not disclose, but Vergis discloses
wherein each DRAM device has a x16 data bus interface to exchange 16 data bits per unit interval with the data bus (eg., 0032 - the data bus can support memory devices that have either a ×32 interface, a ×16 interface, a ×8 interface, or other interface. The convention “xW,” where W is an integer that refers to an interface size or width of the interface of memory device 140, which represents a number of signal lines to exchange data with memory controller 120.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the Dimm with DRAMs as disclosed by Nale830 with Nale238, with Vergis, providing the benefit of the bus width from the host can be reduced without impacting the bandwidth of the command bus … parity computation logic can be simplified since there are fewer signal lines (see Vergis, 0020).
Claim 12. Nale830 discloses
wherein each data buffer multiplexes data from DRAM devices of different pseudo channels (eg., [0072] In some examples, for configuration 1001 shown in FIG. 10A, buffers 1030-1 to 1030-10 may be data buffers controlled by logic and/or features of multi-port register 1010 to route data associated with requests for access to memory devices 1022-1 for data channel 0 or data channel 1 via a BCOM 0 or a BCOM 1 bus ).
Claim 13. Nale830 discloses
wherein each data buffer multiplexes data from a single DRAM device of a single pseudo channel (eg., 0075 - Multi-port register 1010 may include logic and/or features to determine which memory device data bus based on information from the host computing device that indicates which rank is being access via chip selects or other means. For write operations or cycles, buffers 1030-1 to 1030-10 may either drive host data onto …only a set of memory devices identified as a target of a write command for the write operation.).
Claim 14. Nale830 discloses A system (eg., 0049 Fig. 1, system 100) comprising:
a memory controller (eg., 0028 controller 113)
a memory module coupled to the memory controller, the memory module including (eg.,0028 Fig. 1 - DIMMs 120-1 to 120-n; 0071 DIMM 1000 ) including:
a command/address (CA) bus (eg., 0049 - command bus 430-1);
multiple dynamic random access (DRAM) devices coupled to the CA bus (eg., 0034 - memory devices 122-1 to 122-n at DIMMs 120-1 to 120-n may include all or combinations of types of volatile or non-volatile memory.; 0120 - volatile memory may include DRAM.; 0028 - respective command buses 130-1 to 130-n ); and
Nale830 does not disclose, but Nale238 discloses
a registering clock driver (RCD) to time division multiplex separate first commands for a first group of the DRAM devices from second commands for a second group of the DRAM devices on the CA bus, (eg., 0021 Fig. 4 RCD 402 of FIG. 4 ; 0021 - multiplexers 410 before being decoded and re-driven; )
wherein the RCD is to issue two column address strobe (CAS) commands with a single read command to exchange a double amount of data per DRAM device per read command (eg., 0019 - doubling the number of CA and CS signals ; [0012] A memory transaction over the A sub-channel 101a can therefore target any one of the four different ranks associated with the pair of A pseudo channels, and, likewise, a memory transaction over the B sub-channel 101b can therefore target any one of the four different ranks associated with the pair of B pseudo channels.)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the Dimm with DRAMs as disclosed by Nale830 with Nale238, providing the benefit of an improved RCD chip design 402 that can be used for either the X8 DIMM 100 (see Nale238, 0021) use of pseudo channels extends the LRDIMM architecture to an extended LRDIMM (0027).
Nale830 in view of Nale238 does not disclose, but Vergis discloses
including a first group of the DRAM devices to respond together to first commands and a second group of the DRAM devices to respond together to second commands (eg., 0046 Fig. 2 - multiple memory devices or DRAM devices 222 and 224.; 0052 - C/A bus 244 carries the command signals of C/A bus 242 to DRAMs 222. Thus, from one perspective, C/A bus 242 and C/A bus 244 can be considered the same command bus, such as having two portions);
with time division multiplexing (eg., 0074 - interface logic includes multiplexers to multiplex the DDR command signals )
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the Dimm with DRAMs as disclosed by Nale830 with Nale238, with Vergis, providing the benefit memory subsystem includes a command address bus that has a bus width mismatch with the memory devices. The command bus from the host is narrower and operates at a higher data rate than the native command bus interface of the memory devices. The memory subsystem includes logic to receive the higher data rate command signals and forward them to the memory devices at the lower or standard data rate. The logic can thus be an interface for a command bus with a lower number of signal lines and a higher data rate to a command bus with a higher number of signal lines and a lower data rate (see Vergis, 0018).
Nale830 in view of Nale238 and Vergis does not disclose, but Runas discloses
in response to receipt of a first read command for the first group of the DRAM devices, the RCD is to issue two separate column address strobe (CAS) commands for the first read command to read two portions of data per DRAM device per read command (eg., col 7:3-10 Fig. 4 - Location 1 column address bits are sent to the DRAM device and two consecutive CAS active (low) periods are exercised which cause bits 0-15 and bits 16-31 of a 32-bit double word to be read out of the DRAM device; col 6:32-37 - Because the two data words were located in consecutive locations within the same row, only one row address was needed. However, two separate column addresses were required in order to select the two individual data words )
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the Dimm with DRAMs as disclosed by Nale830 with Nale238 and Vergis, with Runas, providing the benefit of improved memory circuits and processing systems using the improved memory circuits that can more easily access large data words in system memory. In particular, there is a need for processing systems and memory devices that can more easily access large data words in system memory by configuring the data I/O width of the memory devices "on the fly." (see Runas, col 2:21-27).
Claim 15 is rejected for reasons similar to Claim 4 above.
Claim 16 is rejected for reasons similar to Claim 3 above.
Claim 17 is rejected for reasons similar to Claim 5 above.
Claim 18 is rejected for reasons similar to Claim 6 above.
Claim 19 is rejected for reasons similar to Claim 9 above.
Claim 20 is rejected for reasons similar to Claim 10 above.
Claim 21. Nale830 discloses including one or more of:
a host processor coupled to the memory module (eg., 0028 Fig. 1 - Circuitry 112 may include one or more processing element(s) 111 );
a display communicatively coupled to a host processor (eg., 0105 - a desktop computer, a laptop computer, a notebook computer, a netbook computer, a tablet, a smart phone, );
a network interface communicatively coupled to a host processor (eg., 0028 Fig. 1 - DIMMs 120-1 to 120-n may be coupled to host computing device 110 through interface 115 via respective command buses 130-1 to 130-n and data channels 140-1 to 140-n.); or
a battery to power the system (eg., 0149 - a battery communicatively coupled).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Nale (US 20170199830, hereinafter “Nale830”) and in view of Nale (US 20210216238, hereinafter “Nale238”), Vergis (cited above) and Runas (cited above), and further in view of Kim (US 20190206477 A1)
Claim 7. Nale830 in view of Nale238, Vergis and Runas does not disclose, but Kim discloses
wherein the ECC information comprises internal ECC bits generated by on-die ECC on the multiple DRAM devices (eg., 0019 - The ECC memory device 102A is configured to provide error protection for the data memory devices 102A. The ECC memory device 102B is configured to provide error protection for the data memory devices 102B. ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the Dimm with DRAMs as disclosed by Nale830 with Nale238, Vergis and Runas, with Kim, providing the benefit of to using dual channel memory as single channel memory in a memory module (see Kim, 0001, 0003).
Response to Arguments
Applicant's arguments filed 4/7/2026 have been fully considered but they are not persuasive.
For claims 1, 8 and 14, Applicant argues that that the cited references do not disclose the amended limitations. The Office disagrees.
In the present OA, the updated combination of references render the amended limitations as obvious.
Specifically, Nale830 in view of Nale238 does not disclose, but Vergis discloses
including a first group of the DRAM devices to respond together to first commands and a second group of the DRAM devices to respond together to second commands (eg., 0046 Fig. 2 - multiple memory devices or DRAM devices 222 and 224.; 0052 - C/A bus 244 carries the command signals of C/A bus 242 to DRAMs 222. Thus, from one perspective, C/A bus 242 and C/A bus 244 can be considered the same command bus, such as having two portions);
with time division multiplexing (eg., 0074 - interface logic includes multiplexers to multiplex the DDR command signals )
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the Dimm with DRAMs as disclosed by Nale830 with Nale238, with Vergis, providing the benefit memory subsystem includes a command address bus that has a bus width mismatch with the memory devices. The command bus from the host is narrower and operates at a higher data rate than the native command bus interface of the memory devices. The memory subsystem includes logic to receive the higher data rate command signals and forward them to the memory devices at the lower or standard data rate. The logic can thus be an interface for a command bus with a lower number of signal lines and a higher data rate to a command bus with a higher number of signal lines and a lower data rate (see Vergis, 0018).
Nale830 in view of Nale238 and Vergis does not disclose, but Runas discloses
in response to receipt of a first read command for the first group of the DRAM devices, the RCD is to issue two separate column address strobe (CAS) commands for the first read command to read two portions of data per DRAM device per read command (eg., col 7:3-10 Fig. 4 - Location 1 column address bits are sent to the DRAM device and two consecutive CAS active (low) periods are exercised which cause bits 0-15 and bits 16-31 of a 32-bit double word to be read out of the DRAM device; col 6:32-37 - Because the two data words were located in consecutive locations within the same row, only one row address was needed. However, two separate column addresses were required in order to select the two individual data words )
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the Dimm with DRAMs as disclosed by Nale830 with Nale238 and Vergis, with Runas, providing the benefit of improved memory circuits and processing systems using the improved memory circuits that can more easily access large data words in system memory. In particular, there is a need for processing systems and memory devices that can more easily access large data words in system memory by configuring the data I/O width of the memory devices "on the fly." (see Runas, col 2:21-27).
Applicant’s arguments for dependent claims are based on their respective base independent claims 1 and 14, which are addressed above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GAUTAM SAIN whose telephone number is (571)270-3555. The examiner can normally be reached M-F 9-5.
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/GAUTAM SAIN/Primary Examiner, Art Unit 2135
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