DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12 June 2026 has been entered.
Election/Restrictions
Claims 5-11, 13-26 and 28-33 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 06 February 2024.
Applicant’s election without traverse of Species I, corresponding to originally filed Claims 1-4, 27, and 34-35 in the reply filed on 06 February 2024 is acknowledged.
Response to Amendments
It should be noted that the applicant has directed attention to Figure 28 of the originally filed disclosure as providing support and definition for the structural features of the presently claimed invention (see Remarks received 11 December 2024 at Page 20 and Remarks received 03 September 2025 at Page 21).
The applicant has directed attention to Figures 5, 6, 7, and/or 29 of the originally filed disclosure as providing support and definition for the functional features of the presently claimed invention (see Remarks received 23 June 2024 at Page 20; see Remarks received 16 April 2025 at Page 19; and see Remarks received 03 September 2025 at Page 21).
It should further be noted that the embodiment of Figure 28 is directed to a pixel circuit embodiment in which “a data writing module can be reused as the first bias module” (see the originally filed Specification at Paragraph [00153]). Thus, as recited in the claimed invention, the claimed “first bias module” or “first bias circuit” is interpreted to be the same structural element as the claimed “data writing module” or “data writing circuit.”
Claim Objections
Claims 1, 27, 34, and 35 are objected to because of the following informalities: the claims all recite “the third bias phase” instead of “the third bias stage” at the end of the respective claims in the block that begins “the first reset circuit is turned on….” Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
A “driving circuit configured to drive a light-emitting element” in Claims 1, 27, 34, and 35.
A “first light-emitting control circuit” in Claims 1, 27, 34, and 35.
A “threshold compensation circuit” in Claims 1, 27, 34, and 35.
A “first reset circuit” in Claims 1, 27, 34, and 35.
A “second reset circuit” in Claims 1, 27, 34, and 35.
A “data writing circuit” in Claims 1, 27, 34, and 35.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
Specifically, as disclosed with respect to originally filed Figure 28 of the application (see Paragraphs [00153]-[00162] of the originally filed Specification):
The claimed “driving circuit” is interpreted as being a transistor “M1” (101) as shown in Figure 28.
The claimed “first light-emitting control circuit” is interpreted as being a transistor “M5” (107) in Figure 28.
The claimed “threshold compensation circuit” is interpreted as being a transistor “M3” (104) as shown in Figure 28.
The claimed “first reset circuit” is interpreted as being a transistor “M4” (108) as shown in Figure 28.
The claimed “second reset circuit” is interpreted as being a transistor “M7” (108) as shown in Figure 28.
The claimed “data writing circuit” is interpreted as being the “reused” transistor “M2” (103) as shown in Figure 28.
Further, the claimed “first bias circuit,” corresponding to transistor “M2” (103) in Figure 28 is interpreted, as disclosed with relevance to Figure 28, as being both a “data writing circuit” and a “first bias circuit,” as Figure 28 is specifically directed to an embodiment in which “The data writing module can be reused as the first bias module” (see Paragraph [00153] of the originally filed Specification).
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 27, and 34-35 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (hereinafter “Kim” US 2023 / 0079102) in view of Kim et al. (hereinafter “Kim2” US 2023 / 0215360).
As pertaining to Claim 1, Kim discloses (see Fig. 3, Fig. 7B, and Fig. 8B) a pixel circuit (see Fig. 3), comprising (see Page 5, Para. [0085]; and Page 6, Para. [0095], [0097]-[0103] and [0105]-[0110]):
a driving circuit (DRT) configured to drive a light-emitting element (ED) to emit light;
a first bias circuit (T2) electrically connected to a first terminal or a second terminal (i.e., an upper terminal) of the driving circuit (DRT), wherein the first bias circuit (T2) is configured to provide a first bias signal (VOBS) to the first terminal or the second terminal (i.e., the upper terminal) of the driving circuit (DRT), and the first bias signal (VOBS) is configured to adjust a bias state (i.e., a voltage state) of the driving circuit (DRT), and wherein the first bias circuit (T2) comprises an eighth transistor (see (T2)), a gate of the eighth transistor (T2) being electrically connected to a first scan signal terminal (SCAN2), a first electrode (i.e., a right electrode) of the eighth transistor (T2) being electrically connected to a first bias signal terminal (VOBS), and a second electrode (i.e., a left electrode) of the eighth transistor (T2) being electrically connected to the first terminal or the second terminal (i.e., the upper terminal),
wherein a light-emitting cycle of the light-emitting element (ED) comprises a refresh frame (see Fig. 7B) or a hold frame (see Fig. 8B), wherein a control terminal (i.e., a gate terminal) of the driving circuit (DRT) is refreshed in the refresh frame (see Fig. 7B), and the control terminal (i.e., the gate terminal) of the driving circuit (DRT) is not refreshed in the hold frame (see Fig. 8B); each of the refresh frame (see Fig. 7B) and the hold frame (see Fig. 8B) comprises a first stage (i.e., (EM) is high) and a second stage (i.e., (EM) is low), the first stage (i.e., when (EM) is high) is located before the second stage (i.e., when (EM) is low), the first stage (i.e., when (EM) is high) comprises one or more bias stages (i.e., (SCAN2) is low), and the second stage (i.e., when (EM) is low) comprises a light-emitting stage of the light-emitting element (ED), and wherein in the bias stages (i.e., when (SCAN2) is low), the first bias circuit (T2) is turned on (i.e., via (SCAN2)), and the first bias signal (VOBS) is transmitted to the first terminal or the second terminal (i.e., the upper terminal) of the driving circuit (DRT);
a time interval between a start moment (i.e., when (EM) is high) of the hold frame (see Fig. 8B) and a turn-on start moment (i.e., when (SCAN2) is low) of the first bias circuit (T2) in the hold frame (see Fig. 8B) is different than a time interval between a start moment (i.e., when (EM) is high) of the refresh frame (see Fig. 7B) and a turn-on start moment (i.e., when (SCAN2) is low) of the first bias circuit (T2) in the refresh frame (see Fig. 7B);
a gate of the driving circuit (DRT) is electrically connected to a first node (i.e., a gate node), a first electrode (i.e., an upper electrode) of the driving circuit (DRT) is electrically connected to a second node (i.e., an upper node), and a second electrode (i.e., a lower electrode) of the driving circuit (DRT) is electrically connected to a third node (i.e., a lower node);
a first terminal (i.e., a left terminal) of the first bias circuit (T2) is electrically connected to the second node (i.e., the upper node) or the third node (i.e., the lower node); and
the pixel circuit further comprises:
a first light-emitting control circuit (T4), a first terminal (i.e., an upper terminal) of the first light-emitting control circuit (T4) is electrically connected to the third node (i.e., the lower node), and a second terminal (i.e., a lower terminal) of the first light-emitting control circuit (T4) is electrically connected to a first electrode (i.e., an upper electrode) of the light-emitting element (ED);
a threshold compensation circuit (T1), a first terminal (i.e., a left terminal) of the threshold compensation circuit (T1) being electrically connected to the first node (i.e., the gate node), a second terminal (i.e., a right terminal) of the threshold compensation circuit (T1) being electrically connected to the third node (i.e., the lower node), and a control terminal (i.e., a gate terminal) of the threshold compensation circuit (T1) is electrically connected to a third scan signal terminal (SCAN1);
a first reset circuit (T5), a control terminal (i.e., a gate terminal) of the first reset circuit (T5) being electrically connected to a fourth scan signal terminal (SCAN3), a first terminal (i.e., a lower terminal) of the first reset circuit (T5) being electrically connected to a first initialization signal terminal (Vini), and a second terminal (i.e., an upper terminal) of the first reset circuit (T5) being electrically connected to the first node (i.e., the gate node of (DRT));
a second reset circuit (T6), a control terminal (i.e., a gate terminal) of the second reset circuit (T6) being electrically connected to a sixth scan signal terminal (SCAN4), a first terminal (i.e., a left terminal) of the second reset circuit (T6) being electrically connected to a second initialization signal terminal (VAR), and a second terminal (i.e., a right terminal) of the second reset circuit (T6) being electrically connected to the first electrode (i.e., the upper electrode) of the light-emitting element (ED); and
a data writing circuit (T2), a control terminal (i.e., a gate terminal) of the data writing circuit (T2) being electrically connected to a second scan signal terminal (SCAN2), a first terminal (i.e., a right terminal) of the data writing circuit (T2) being electrically connected to a data signal terminal (Vdata), and a second terminal (i.e., a left terminal) of the data writing circuit (T2) being electrically connected to the first terminal (i.e., the upper terminal) or the second terminal (i.e., the lower terminal) of the driving circuit (DRT),
wherein a turn-on duration of the sixth scan signal terminal (SCAN4) overlaps (i.e., is equal to) a turn-on duration of the second scan signal terminal (SCAN2; see Fig. 8B);
the refresh frame (see Fig. 7B) includes an initialization stage (i.e., an arbitrary time period during which (SCAN3) is a high voltage), a third bias stage (i.e., an arbitrary time period during which (SCAN1) is a high voltage), a data writing stage (i.e., an arbitrary time period during which (SCAN2) is a low voltage), a second bias stage (i.e., another arbitrary time period during which (SCAN2) is a low voltage), and a light-emitting stage (i.e., an arbitrary time period during which (EM) is a low voltage) arranged in time sequence (see Fig. 7B), and the data writing stage (i.e., the arbitrary time period during which (SCAN2) is a low voltage) of the refresh frame (see Fig. 7B) is the same stage as a first bias stage (i.e., when (SCAN2) is low) of the refresh frame (see Fig. 7B), and the threshold compensation circuit (T1) is turned on in the third bias stage (i.e., the arbitrary time period during which (SCAN1) is a high voltage) of the refresh frame (see Fig. 7B);
the first bias circuit (T2) is turned on under a control of a scan signal provided by the first scan signal terminal (SCAN2) in the third bias stage (i.e., the arbitrary time period during which (SCAN1) is a high voltage; see Fig. 7B);
the first reset circuit (T5) is turned on (i.e., via (SCAN3)) before the first bias circuit (T2) and the threshold compensation circuit (T1) are turned on in the refresh frame (again, see Fig. 7B), and in the third bias phase (i.e., the arbitrary time period during which (SCAN1) is a high voltage), the first reset circuit (T5) and the threshold compensation circuit (T1) are turned on (i.e., via (SCAN3) and (SCAN1), respectively; see Fig. 7B); and
the data writing circuit (T2) is turned on under a control of a scan signal provided by the second scan signal terminal (SCAN2) in the data writing stage (i.e., the arbitrary time period during which (SCAN2) is a low voltage) and the second bias stage (i.e., another arbitrary time period during which (SCAN2) is a low voltage; see Fig. 7B and note that (T2) is turned on two times via (SCAN2) in the refresh frame, once during the data writing stage, which is the same as the first bias stage, and once during the second bias stage following the data writing stage; see Page 6 through Page 7, Para. [0120]; and Page 9, Para. [0174], [0176]-[0178], and [0181]-[0182]; and again, see Page 6, Para. [0107]-[0110]).
Kim discloses that a level of a bias signal can be different in the refresh frame and the hold frame (see Page 10, Para. [0191] and [0195]-[0197]). However, Kim does not explicitly disclose that the first bias circuit is further configured to have a turn-on duration in the hold frame and a turn-on duration in the refresh frame that is different from the turn-on duration in the hold frame.
However, in the same field of endeavor, Kim2 discloses (see Fig. 2) a pixel circuit (PX; see Page 4, Para. [0063]) comprising a first bias circuit (T7) configured to provide a first bias signal (VAINT) to a driving circuit, and the first bias signal (VAINT) is configured to adjust a bias state of the driving circuit (see (T1, T6) in Fig. 20, for example; and see Page 11, Para. [0114]), wherein a light-emitting cycle of a light-emitting element (EL) comprises a refresh frame (SP) and a hold frame (HP), and wherein (see Fig. 8 and Fig. 10) the first bias circuit (T7) is further configured to have a turn-on duration (see (GB)) in the hold frame (HP) and a turn-on duration (see (GB)) in the refresh frame (SP) that is different from the turn-on duration (again, see (GB)) in the hold frame (HP; see Page 6 through Page 7, Para. [0079]-[0080] and Page 7 through Page 8, Para. [0084]-[0086]). In addition, Kim2 further discloses (see Fig. 22 and Fig. 23) that a time interval between a start moment of the hold frame (HP; see Fig. 22) and a turn-on start moment (see (GB)) of the first bias circuit (T7) in the hold frame (HP) can be different from a time interval between a start moment of the refresh frame (SP; see Fig. 23) and a turn-on start moment (see (GB)) of the first bias circuit (T7) in the refresh frame (SP; see Page 12, Para. [0124]-[0127]). Further still, Kim2 discloses (see Fig. 11) that a level of the first bias signal (VAINT) can be different in the refresh frame (SP) and the hold frame (HP; see Page 8, Para. [0088]-[0091]). Kim2 discloses a number of ways in which the first bias signal can be utilized to adjust a bias state of the driving circuit in order to provide a uniform luminance level across a display device when a pixel circuit is driven at different driving frequencies (see Page 1, Para. [0006]-[0007]). Specifically, Kim2 suggests various driving implementations of a first bias circuit for preventing a luminance difference during a refresh frame and a hold frame when a pixel circuit is driven at different driving frequencies (see Page 3, Para. [0029]). This is a goal that is shared by Kim (see at least Page 1, Para. [0009] of Kim).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kim with the teachings of Kim2, such that a time interval between a start moment of the hold frame and a tum-on start moment of the first bias circuit in the hold frame is different from a time interval between a start moment of the refresh frame and a tum-on start moment of the first bias circuit in the refresh frame, as suggested by both Kim and Kim2, and such that the first bias circuit is further configured to have a turn-on duration in the hold frame and a turn-on duration in the refresh frame that is different from the tum-on duration in the hold frame, as suggested by Kim2, in order to provide a driving implementation of the first bias circuit that prevents a luminance difference during a refresh frame and a hold frame when a pixel circuit is driven at different driving frequencies, thereby providing a uniform luminance level across a display device.
As pertaining to Claim 2, Kim discloses (see Fig. 3, Fig. 7B, and Fig. 8B) that in the hold frame (see Fig. 8B), the bias stages (i.e., when (SCAN2) is low) comprise the first bias stage (i.e., again, when (SCAN2) is low), wherein in the first bias stage (i.e., when (SCAN2) is low), the first bias circuit (T2) is turned on, and the first bias signal (VOBS) is transmitted to the first terminal or the second terminal (i.e., the upper terminal) of the driving circuit (see (DRT); and again, see Page 9, Para. [0174], [0176]-[0178], and [0181]-[0182]).
As pertaining to Claim 3, Kim discloses (see Fig. 3, Fig. 7B, and Fig. 8B) in the refresh frame (see Fig. 7B) and the hold frame (see Fig. 8B), the first scan signal (SCAN2) comprises one or more pulses for controlling the first bias circuit (T2) to be turned on, and the pulses comprise 1st to Mth pulses (SCAN2) arranged at intervals in time sequence, where M is a positive integer (i.e., M is one or greater);
a time interval between a turn-on moment of the 1st pulse (SCAN2) of the first scan signal (see (SCAN2)) in the hold frame (see Fig. 8B) and the light-emitting stage (i.e., when (EM) is low) in the hold frame (see Fig. 8B) is a first time interval (again, see Fig. 8B), and a time interval between a turn-on moment of the 1st pulse (SCAN2) of the first scan signal (see (SCAN2)) in the refresh frame (see Fig. 7B) and the light-emitting stage (i.e., when (EM) is low) in the refresh frame (see Fig. 7B) is a second time interval (again, see Fig. 7B), and wherein the first time interval (see a first (SCAN2) in Fig. 8B) is greater than the second time interval (see a first (SCAN2) in Fig. 7B; and again, see Page 9, Para. [0174], [0176]-[0178], and [0181]-[0182]).
As pertaining to Claim 4, Kim discloses (see Fig. 3, Fig. 7B, and Fig. 8B) a width of the pulse (SCAN2) in the hold frame (see Fig. 8B) is equal to a width of the pulse (SCAN2) in the refresh frame (see Fig. 7B; and again, see Page 9, Para. [0174], [0176]-[0178], and [0181]-[0182]).
As pertaining to Claim 27, Kim discloses (see Fig. 3, Fig. 7B, and Fig. 8B) a driving method of a pixel circuit (see Fig. 3; and see Page 5, Para. [0085]; and Page 6, Para. [0095], [0097]-[0103] and [0105]-[0110]), wherein the pixel circuit comprises: a driving circuit (DRT) configured to drive a light-emitting element (ED) to emit light; and
a first bias circuit (T2) electrically connected to a first terminal or a second terminal (i.e., an upper terminal) of the driving circuit (DRT), wherein the first bias circuit (T2) is configured to provide a first bias signal (VOBS) to the first terminal or the second terminal (i.e., the upper terminal) of the driving circuit (DRT), and the first bias signal (VOBS) is configured to adjust a bias state (i.e., a voltage state) of the driving circuit (DRT), and wherein the first bias circuit (T2) comprises an eighth transistor (see (T2)), a gate of the eighth transistor (T2) being electrically connected to a first scan signal terminal (SCAN2), a first electrode (i.e., a right electrode) of the eighth transistor (T2) being electrically connected to a first bias signal terminal (VOBS), and a second electrode (i.e., a left electrode) of the eighth transistor (T2) being electrically connected to the first terminal or the second terminal (i.e., the upper terminal),
wherein a light-emitting cycle of the light-emitting element (ED) comprises a refresh frame (see Fig. 7B) or a hold frame (see Fig. 8B), wherein a control terminal (i.e., a gate terminal) of the driving circuit (DRT) is refreshed in the refresh frame (see Fig. 7B), and the control terminal (i.e., the gate terminal) of the driving circuit (DRT) is not refreshed in the hold frame (see Fig. 8B); each of the refresh frame (see Fig. 7B) and the hold frame (see Fig. 8B) comprises a first stage (i.e., (EM) is high) and a second stage (i.e., (EM) is low), the first stage (i.e., when (EM) is high) is located before the second stage (i.e., when (EM) is low), the first stage (i.e., when (EM) is high) comprises one or more bias stages (i.e., (SCAN2) is low), and the second stage (i.e., when (EM) is low) comprises a light-emitting stage of the light-emitting element (ED);
the driving method comprises:
in the bias stages (i.e., when (SCAN2) is low), controlling the first bias circuit (T2) to be turned on (i.e., via (SCAN2)), and transmitting the first bias signal (VOBS) to the first terminal or the second terminal (i.e., the upper terminal) of the driving circuit (DRT);
a time interval between a start moment (i.e., when (EM) is high) of the hold frame (see Fig. 8B) and a turn-on start moment (i.e., when (SCAN2) is low) of the first bias circuit (T2) in the hold frame (see Fig. 8B) is different from a time interval between a start moment (i.e., when (EM) is high) of the refresh frame (see Fig. 7B) and a turn-on start moment (i.e., when (SCAN2) is low) of the first bias circuit (T2) in the refresh frame (see Fig. 7B);
a gate of the driving circuit (DRT) is electrically connected to a first node (i.e., a gate node), a first electrode (i.e., an upper electrode) of the driving circuit (DRT) is electrically connected to a second node (i.e., an upper node), and a second electrode (i.e., a lower electrode) of the driving circuit (DRT) is electrically connected to a third node (i.e., a lower node);
a first terminal (i.e., a left terminal) of the first bias circuit (T2) is electrically connected to the second node (i.e., the upper node) or the third node (i.e., the lower node);
the pixel circuit further comprises:
a first light-emitting control circuit (T4), a first terminal (i.e., an upper terminal) of the first light-emitting control circuit (T4) is electrically connected to the third node (i.e., the lower node), and a second terminal (i.e., a lower terminal) of the first light-emitting control circuit (T4) is electrically connected to a first electrode (i.e., an upper electrode) of the light-emitting element (ED);
a threshold compensation circuit (T1), a first terminal (i.e., a left terminal) of the threshold compensation circuit (T1) being electrically connected to the first node (i.e., the gate node), a second terminal (i.e., a right terminal) of the threshold compensation circuit (T1) being electrically connected to the third node (i.e., the lower node), and a control terminal (i.e., a gate terminal) of the threshold compensation circuit (T1) is electrically connected to a third scan signal terminal (SCAN1);
a first reset circuit (T5), a control terminal (i.e., a gate terminal) of the first reset circuit (T5) being electrically connected to a fourth scan signal terminal (SCAN3), a first terminal (i.e., a lower terminal) of the first reset circuit (T5) being electrically connected to a first initialization signal terminal (Vini), and a second terminal (i.e., an upper terminal) of the first reset circuit (T5) being electrically connected to the first node (i.e., the gate node of (DRT));
a second reset circuit (T6), a control terminal (i.e., a gate terminal) of the second reset circuit (T6) being electrically connected to a sixth scan signal terminal (SCAN4), a first terminal (i.e., a left terminal) of the second reset circuit (T6) being electrically connected to a second initialization signal terminal (VAR), and a second terminal (i.e., a right terminal) of the second reset circuit (T6) being electrically connected to the first electrode (i.e., the upper electrode) of the light-emitting element (ED); and
a data writing circuit (T2), a control terminal (i.e., a gate terminal) of the data writing circuit (T2) being electrically connected to a second scan signal terminal (SCAN2), a first terminal (i.e., a right terminal) of the data writing circuit (T2) being electrically connected to a data signal terminal (Vdata), and a second terminal (i.e., a left terminal) of the data writing circuit (T2) being electrically connected to the first terminal (i.e., the upper terminal) or the second terminal (i.e., the lower terminal) of the driving circuit (DRT),
wherein a turn-on duration of the sixth scan signal terminal (SCAN4) overlaps (i.e., is equal to) a turn-on duration of the second scan signal terminal (SCAN2; see Fig. 8B); and
the refresh frame (see Fig. 7B) includes an initialization stage (i.e., an arbitrary time period during which (SCAN3) is a high voltage), a third bias stage (i.e., an arbitrary time period during which (SCAN1) is a high voltage), a data writing stage (i.e., an arbitrary time period during which (SCAN2) is a low voltage), a second bias stage (i.e., another arbitrary time period during which (SCAN2) is a low voltage), and a light-emitting stage (i.e., an arbitrary time period during which (EM) is a low voltage) arranged in time sequence (see Fig. 7B), the data writing stage (i.e., the arbitrary time period during which (SCAN2) is a low voltage) of the refresh frame (see Fig. 7B) is the same stage as a first bias stage (i.e., when (SCAN2) is low) of the refresh frame (see Fig. 7B), and the threshold compensation circuit (T1) is turned on in the third bias stage (i.e., the arbitrary time period during which (SCAN1) is a high voltage) of the refresh frame (see Fig. 7B);
the first bias circuit (T2) is turned on under a control of a scan signal provided by the first scan signal terminal (SCAN2) in the third bias stage (i.e., the arbitrary time period during which (SCAN1) is a high voltage; see Fig. 7B);
the first reset circuit (T5) is turned on (i.e., via (SCAN3)) before the first bias circuit (T2) and the threshold compensation circuit (T1) are turned on in the refresh frame (again, see Fig. 7B), and in the third bias phase (i.e., the arbitrary time period during which (SCAN1) is a high voltage), the first reset circuit (T5) and the threshold compensation circuit (T1) are turned on (i.e., via (SCAN3) and (SCAN1), respectively; see Fig. 7B); and
the data writing circuit (T2) is turned on under a control of a scan signal provided by the second scan signal terminal (SCAN2) in the data writing stage (i.e., the arbitrary time period during which (SCAN2) is a low voltage) and the second bias stage (i.e., another arbitrary time period during which (SCAN2) is a low voltage; see Fig. 7B and note that (T2) is turned on two times via (SCAN2) in the refresh frame, once during the data writing stage, which is the same as the first bias stage, and once during the second bias stage following the data writing stage; see Page 6 through Page 7, Para. [0120]; and Page 9, Para. [0174], [0176]-[0178], and [0181]-[0182]; and again, see Page 6, Para. [0107]-[0110]).
Kim discloses that a level of a bias signal can be different in the refresh frame and the hold frame (see Page 10, Para. [0191] and [0195]-[0197]). However, Kim does not explicitly disclose that the first bias circuit is further configured to have a turn-on duration in the hold frame and a turn-on duration in the refresh frame that is different from the turn-on duration in the hold frame.
However, in the same field of endeavor, Kim2 discloses (see Fig. 2) a pixel circuit (PX; see Page 4, Para. [0063]) comprising a first bias circuit (T7) configured to provide a first bias signal (VAINT) to a driving circuit, and the first bias signal (VAINT) is configured to adjust a bias state of the driving circuit (see (T1, T6) in Fig. 20, for example; and see Page 11, Para. [0114]), wherein a light-emitting cycle of a light-emitting element (EL) comprises a refresh frame (SP) and a hold frame (HP), and wherein (see Fig. 8 and Fig. 10) the first bias circuit (T7) is further configured to have a turn-on duration (see (GB)) in the hold frame (HP) and a turn-on duration (see (GB)) in the refresh frame (SP) that is different from the turn-on duration (again, see (GB)) in the hold frame (HP; see Page 6 through Page 7, Para. [0079]-[0080] and Page 7 through Page 8, Para. [0084]-[0086]). In addition, Kim2 further discloses (see Fig. 22 and Fig. 23) that a time interval between a start moment of the hold frame (HP; see Fig. 22) and a turn-on start moment (see (GB)) of the first bias circuit (T7) in the hold frame (HP) can be different from a time interval between a start moment of the refresh frame (SP; see Fig. 23) and a turn-on start moment (see (GB)) of the first bias circuit (T7) in the refresh frame (SP; see Page 12, Para. [0124]-[0127]). Further still, Kim2 discloses (see Fig. 11) that a level of the first bias signal (VAINT) can be different in the refresh frame (SP) and the hold frame (HP; see Page 8, Para. [0088]-[0091]). Kim2 discloses a number of ways in which the first bias signal can be utilized to adjust a bias state of the driving circuit in order to provide a uniform luminance level across a display device when a pixel circuit is driven at different driving frequencies (see Page 1, Para. [0006]-[0007]). Specifically, Kim2 suggests various driving implementations of a first bias circuit for preventing a luminance difference during a refresh frame and a hold frame when a pixel circuit is driven at different driving frequencies (see Page 3, Para. [0029]). This is a goal that is shared by Kim (see at least Page 1, Para. [0009] of Kim).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kim with the teachings of Kim2, such that a time interval between a start moment of the hold frame and a tum-on start moment of the first bias circuit in the hold frame is different from a time interval between a start moment of the refresh frame and a tum-on start moment of the first bias circuit in the refresh frame, as suggested by both Kim and Kim2, and such that the first bias circuit is further configured to have a turn-on duration in the hold frame and a turn-on duration in the refresh frame that is different from the tum-on duration in the hold frame, as suggested by Kim2, in order to provide a driving implementation of the first bias circuit that prevents a luminance difference during a refresh frame and a hold frame when a pixel circuit is driven at different driving frequencies, thereby providing a uniform luminance level across a display device.
As pertaining to Claim 34, Kim discloses (see Fig. 3, Fig. 7B, and Fig. 8B) a display panel comprising a pixel circuit (see Fig. 3), wherein the pixel circuit comprises (see Page 5, Para. [0085]; and Page 6, Para. [0095], [0097]-[0103] and [0105]-[0110]):
a driving circuit (DRT) configured to drive a light-emitting element (ED) to emit light; and
a first bias circuit (T2) electrically connected to a first terminal or a second terminal (i.e., an upper terminal) of the driving circuit (DRT), wherein the first bias circuit (T2) is configured to provide a first bias signal (VOBS) to the first terminal or the second terminal (i.e., the upper terminal) of the driving circuit (DRT), and the first bias signal (VOBS) is configured to adjust a bias state (i.e., a voltage state) of the driving circuit (DRT), and wherein the first bias circuit (T2) comprises an eighth transistor (see (T2)), a gate of the eighth transistor (T2) being electrically connected to a first scan signal terminal (SCAN2), a first electrode (i.e., a right electrode) of the eighth transistor (T2) being electrically connected to a first bias signal terminal (VOBS), and a second electrode (i.e., a left electrode) of the eighth transistor (T2) being electrically connected to the first terminal or the second terminal (i.e., the upper terminal),
wherein a light-emitting cycle of the light-emitting element (ED) comprises a refresh frame (see Fig. 7B) or a hold frame (see Fig. 8B), wherein a control terminal (i.e., a gate terminal) of the driving circuit (DRT) is refreshed in the refresh frame (see Fig. 7B), and the control terminal (i.e., the gate terminal) of the driving circuit (DRT) is not refreshed in the hold frame (see Fig. 8B); each of the refresh frame (see Fig. 7B) and the hold frame (see Fig. 8B) comprises a first stage (i.e., (EM) is high) and a second stage (i.e., (EM) is low), the first stage (i.e., when (EM) is high) is located before the second stage (i.e., when (EM) is low), the first stage (i.e., when (EM) is high) comprises one or more bias stages (i.e., (SCAN2) is low), and the second stage (i.e., when (EM) is low) comprises a light-emitting stage of the light-emitting element (ED), and wherein in the bias stages (i.e., when (SCAN2) is low), the first bias circuit (T2) is turned on (i.e., via (SCAN2)), and the first bias signal (VOBS) is transmitted to the first terminal or the second terminal (i.e., the upper terminal) of the driving circuit (DRT);
a time interval between a start moment (i.e., when (EM) is high) of the hold frame (see Fig. 8B) and a turn-on start moment (i.e., when (SCAN2) is low) of the first bias circuit (T2) in the hold frame (see Fig. 8B) is different from a time interval between a start moment (i.e., when (EM) is high) of the refresh frame (see Fig. 7B) and a turn-on start moment (i.e., when (SCAN2) is low) of the first bias circuit (T2) in the refresh frame (see Fig. 7B);
a gate of the driving circuit (DRT) is electrically connected to a first node (i.e., a gate node), a first electrode (i.e., an upper electrode) of the driving circuit (DRT) is electrically connected to a second node (i.e., an upper node), and a second electrode (i.e., a lower electrode) of the driving circuit (DRT) is electrically connected to a third node (i.e., a lower node);
a first terminal (i.e., a left terminal) of the first bias circuit (T2) is electrically connected to the second node (i.e., the upper node) or the third node (i.e., the lower node);
wherein the pixel circuit further comprises:
a first light-emitting control circuit (T4), a first terminal (i.e., an upper terminal) of the first light-emitting control circuit (T4) is electrically connected to the third node (i.e., the lower node), and a second terminal (i.e., a lower terminal) of the first light-emitting control circuit (T4) is electrically connected to a first electrode (i.e., an upper electrode) of the light-emitting element (ED);
a threshold compensation circuit (T1), a first terminal (i.e., a left terminal) of the threshold compensation circuit (T1) being electrically connected to the first node (i.e., the gate node), a second terminal (i.e., a right terminal) of the threshold compensation circuit (T1) being electrically connected to the third node (i.e., the lower node), and a control terminal (i.e., a gate terminal) of the threshold compensation circuit (T1) is electrically connected to a third scan signal terminal (SCAN1);
a first reset circuit (T5), a control terminal (i.e., a gate terminal) of the first reset circuit (T5) being electrically connected to a fourth scan signal terminal (SCAN3), a first terminal (i.e., a lower terminal) of the first reset circuit (T5) being electrically connected to a first initialization signal terminal (Vini), and a second terminal (i.e., an upper terminal) of the first reset circuit (T5) being electrically connected to the first node (i.e., the gate node of (DRT));
a second reset circuit (T6), a control terminal (i.e., a gate terminal) of the second reset circuit (T6) being electrically connected to a sixth scan signal terminal (SCAN4), a first terminal (i.e., a left terminal) of the second reset circuit (T6) being electrically connected to a second initialization signal terminal (VAR), and a second terminal (i.e., a right terminal) of the second reset circuit (T6) being electrically connected to the first electrode (i.e., the upper electrode) of the light-emitting element (ED); and
a data writing circuit (T2), a control terminal (i.e., a gate terminal) of the data writing circuit (T2) being electrically connected to a second scan signal terminal (SCAN2), a first terminal (i.e., a right terminal) of the data writing circuit (T2) being electrically connected to a data signal terminal (Vdata), and a second terminal (i.e., a left terminal) of the data writing circuit (T2) being electrically connected to the first terminal (i.e., the upper terminal) or the second terminal (i.e., the lower terminal) of the driving circuit (DRT),
wherein a turn-on duration of the sixth scan signal terminal (SCAN4) overlaps (i.e., is equal to) a turn-on duration of the second scan signal terminal (SCAN2; see Fig. 8B);
the refresh frame (see Fig. 7B) includes an initialization stage (i.e., an arbitrary time period during which (SCAN3) is a high voltage), a third bias stage (i.e., an arbitrary time period during which (SCAN1) is a high voltage), a data writing stage (i.e., an arbitrary time period during which (SCAN2) is a low voltage), a second bias stage (i.e., another arbitrary time period during which (SCAN2) is a low voltage), and a light-emitting stage (i.e., an arbitrary time period during which (EM) is a low voltage) arranged in time sequence (see Fig. 7B), the data writing stage (i.e., the arbitrary time period during which (SCAN2) is a low voltage) of the refresh frame (see Fig. 7B) is the same stage as a first bias stage (i.e., when (SCAN2) is low) of the refresh frame (see Fig. 7B), and the threshold compensation circuit (T1) is turned on in the third bias stage (i.e., the arbitrary time period during which (SCAN1) is a high voltage) of the refresh frame (see Fig. 7B);
the first bias circuit (T2) is turned on under a control of a scan signal provided by the first scan signal terminal (SCAN2) in the third bias stage (i.e., the arbitrary time period during which (SCAN1) is a high voltage; see Fig. 7B);
the first reset circuit (T5) is turned on (i.e., via (SCAN3)) before the first bias circuit (T2) and the threshold compensation circuit (T1) are turned on in the refresh frame (again, see Fig. 7B), and in the third bias phase (i.e., the arbitrary time period during which (SCAN1) is a high voltage), the first reset circuit (T5) and the threshold compensation circuit (T1) are turned on (i.e., via (SCAN3) and (SCAN1), respectively; see Fig. 7B); and
the data writing circuit (T2) is turned on under a control of a scan signal provided by the second scan signal terminal (SCAN2) in the data writing stage (i.e., the arbitrary time period during which (SCAN2) is a low voltage) and the second bias stage (i.e., another arbitrary time period during which (SCAN2) is a low voltage; see Fig. 7B and note that (T2) is turned on two times via (SCAN2) in the refresh frame, once during the data writing stage, which is the same as the first bias stage, and once during the second bias stage following the data writing stage; see Page 6 through Page 7, Para. [0120]; and Page 9, Para. [0174], [0176]-[0178], and [0181]-[0182]; and again, see Page 6, Para. [0107]-[0110]).
Kim discloses that a level of a bias signal can be different in the refresh frame and the hold frame (see Page 10, Para. [0191] and [0195]-[0197]). However, Kim does not explicitly disclose that the first bias circuit is further configured to have a turn-on duration in the hold frame and a turn-on duration in the refresh frame that is different from the turn-on duration in the hold frame.
However, in the same field of endeavor, Kim2 discloses (see Fig. 2) a pixel circuit (PX; see Page 4, Para. [0063]) comprising a first bias circuit (T7) configured to provide a first bias signal (VAINT) to a driving circuit, and the first bias signal (VAINT) is configured to adjust a bias state of the driving circuit (see (T1, T6) in Fig. 20, for example; and see Page 11, Para. [0114]), wherein a light-emitting cycle of a light-emitting element (EL) comprises a refresh frame (SP) and a hold frame (HP), and wherein (see Fig. 8 and Fig. 10) the first bias circuit (T7) is further configured to have a turn-on duration (see (GB)) in the hold frame (HP) and a turn-on duration (see (GB)) in the refresh frame (SP) that is different from the turn-on duration (again, see (GB)) in the hold frame (HP; see Page 6 through Page 7, Para. [0079]-[0080] and Page 7 through Page 8, Para. [0084]-[0086]). In addition, Kim2 further discloses (see Fig. 22 and Fig. 23) that a time interval between a start moment of the hold frame (HP; see Fig. 22) and a turn-on start moment (see (GB)) of the first bias circuit (T7) in the hold frame (HP) can be different from a time interval between a start moment of the refresh frame (SP; see Fig. 23) and a turn-on start moment (see (GB)) of the first bias circuit (T7) in the refresh frame (SP; see Page 12, Para. [0124]-[0127]). Further still, Kim2 discloses (see Fig. 11) that a level of the first bias signal (VAINT) can be different in the refresh frame (SP) and the hold frame (HP; see Page 8, Para. [0088]-[0091]). Kim2 discloses a number of ways in which the first bias signal can be utilized to adjust a bias state of the driving circuit in order to provide a uniform luminance level across a display device when a pixel circuit is driven at different driving frequencies (see Page 1, Para. [0006]-[0007]). Specifically, Kim2 suggests various driving implementations of a first bias circuit for preventing a luminance difference during a refresh frame and a hold frame when a pixel circuit is driven at different driving frequencies (see Page 3, Para. [0029]). This is a goal that is shared by Kim (see at least Page 1, Para. [0009] of Kim).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kim with the teachings of Kim2, such that a time interval between a start moment of the hold frame and a tum-on start moment of the first bias circuit in the hold frame is different from a time interval between a start moment of the refresh frame and a tum-on start moment of the first bias circuit in the refresh frame, as suggested by both Kim and Kim2, and such that the first bias circuit is further configured to have a turn-on duration in the hold frame and a turn-on duration in the refresh frame that is different from the tum-on duration in the hold frame, as suggested by Kim2, in order to provide a driving implementation of the first bias circuit that prevents a luminance difference during a refresh frame and a hold frame when a pixel circuit is driven at different driving frequencies, thereby providing a uniform luminance level across a display device.
As pertaining to Claim 35, Kim discloses (see Fig. 3, Fig. 7B, and Fig. 8B) a display device comprising a display panel, wherein the display panel comprises a pixel circuit (see Fig. 3), and the pixel circuit comprises (see Page 5, Para. [0085]; and Page 6, Para. [0095], [0097]-[0103] and [0105]-[0110]):
a driving circuit (DRT) configured to drive a light-emitting element (ED) to emit light; and
a first bias circuit (T2) electrically connected to a first terminal or a second terminal (i.e., an upper terminal) of the driving circuit (DRT), wherein the first bias circuit (T2) is configured to provide a first bias signal (VOBS) to the first terminal or the second terminal (i.e., the upper terminal) of the driving circuit (DRT), and the first bias signal (VOBS) is configured to adjust a bias state (i.e., a voltage state) of the driving circuit (DRT), and wherein the first bias circuit (T2) comprises an eighth transistor (see (T2)), a gate of the eighth transistor (T2) being electrically connected to a first scan signal terminal (SCAN2), a first electrode (i.e., a right electrode) of the eighth transistor (T2) being electrically connected to a first bias signal terminal (VOBS), and a second electrode (i.e., a left electrode) of the eighth transistor (T2) being electrically connected to the first terminal or the second terminal (i.e., the upper terminal),
wherein a light-emitting cycle of the light-emitting element (ED) comprises a refresh frame (see Fig. 7B) or a hold frame (see Fig. 8B), wherein a control terminal (i.e., a gate terminal) of the driving circuit (DRT) is refreshed in the refresh frame (see Fig. 7B), and the control terminal (i.e., the gate terminal) of the driving circuit (DRT) is not refreshed in the hold frame (see Fig. 8B); each of the refresh frame (see Fig. 7B) and the hold frame (see Fig. 8B) comprises a first stage (i.e., (EM) is high) and a second stage (i.e., (EM) is low), the first stage (i.e., when (EM) is high) is located before the second stage (i.e., when (EM) is low), the first stage (i.e., when (EM) is high) comprises one or more bias stages (i.e., (SCAN2) is low), and the second stage (i.e., when (EM) is low) comprises a light-emitting stage of the light-emitting element (ED), and wherein in the bias stages (i.e., when (SCAN2) is low), the first bias circuit (T2) is turned on (i.e., via (SCAN2)), and the first bias signal (VOBS) is transmitted to the first terminal or the second terminal (i.e., the upper terminal) of the driving circuit (DRT);
a time interval between a start moment (i.e., when (EM) is high) of the hold frame (see Fig. 8B) and a turn-on start moment (i.e., when (SCAN2) is low) of the first bias circuit (T2) in the hold frame (see Fig. 8B) is different from a time interval between a start moment (i.e., when (EM) is high) of the refresh frame (see Fig. 7B) and a turn-on start moment (i.e., when (SCAN2) is low) of the first bias circuit (T2) in the refresh frame (see Fig. 7B);
a gate of the driving circuit (DRT) is electrically connected to a first node (i.e., a gate node), a first electrode (i.e., an upper electrode) of the driving circuit (DRT) is electrically connected to a second node (i.e., an upper node), and a second electrode (i.e., a lower electrode) of the driving circuit (DRT) is electrically connected to a third node (i.e., a lower node);
a first terminal (i.e., a left terminal) of the first bias circuit (T2) is electrically connected to the second node (i.e., the upper node) or the third node (i.e., the lower node);
the pixel circuit further comprises:
a first light-emitting control circuit (T4), a first terminal (i.e., an upper terminal) of the first light-emitting control circuit (T4) is electrically connected to the third node (i.e., the lower node), and a second terminal (i.e., a lower terminal) of the first light-emitting control circuit (T4) is electrically connected to a first electrode (i.e., an upper electrode) of the light-emitting element (ED);
a threshold compensation circuit (T1), a first terminal (i.e., a left terminal) of the threshold compensation circuit (T1) being electrically connected to the first node (i.e., the gate node), a second terminal (i.e., a right terminal) of the threshold compensation circuit (T1) being electrically connected to the third node (i.e., the lower node), and a control terminal (i.e., a gate terminal) of the threshold compensation circuit (T1) is electrically connected to a third scan signal terminal (SCAN1);
a first reset circuit (T5), a control terminal (i.e., a gate terminal) of the first reset circuit (T5) being electrically connected to a fourth scan signal terminal (SCAN3), a first terminal (i.e., a lower terminal) of the first reset circuit (T5) being electrically connected to a first initialization signal terminal (Vini), and a second terminal (i.e., an upper terminal) of the first reset circuit (T5) being electrically connected to the first node (i.e., the gate node of (DRT));
a second reset circuit (T6), a control terminal (i.e., a gate terminal) of the second reset circuit (T6) being electrically connected to a sixth scan signal terminal (SCAN4), a first terminal (i.e., a left terminal) of the second reset circuit (T6) being electrically connected to a second initialization signal terminal (VAR), and a second terminal (i.e., a right terminal) of the second reset circuit (T6) being electrically connected to the first electrode (i.e., the upper electrode) of the light-emitting element (ED); and
a data writing circuit (T2), a control terminal (i.e., a gate terminal) of the data writing circuit (T2) being electrically connected to a second scan signal terminal (SCAN2), a first terminal (i.e., a right terminal) of the data writing circuit (T2) being electrically connected to a data signal terminal (Vdata), and a second terminal (i.e., a left terminal) of the data writing circuit (T2) being electrically connected to the first terminal (i.e., the upper terminal) or the second terminal (i.e., the lower terminal) of the driving circuit (DRT),
wherein a turn-on duration of the sixth scan signal terminal (SCAN4) overlaps (i.e., is equal to) a turn-on duration of the second scan signal terminal (SCAN2; see Fig. 8B);
the refresh frame (see Fig. 7B) includes an initialization stage (i.e., an arbitrary time period during which (SCAN3) is a high voltage), a third bias stage (i.e., an arbitrary time period during which (SCAN1) is a high voltage), a data writing stage (i.e., an arbitrary time period during which (SCAN2) is a low voltage), a second bias stage (i.e., another arbitrary time period during which (SCAN2) is a low voltage), and a light-emitting stage (i.e., an arbitrary time period during which (EM) is a low voltage) arranged in time sequence (see Fig. 7B), the data writing stage (i.e., the arbitrary time period during which (SCAN2) is a low voltage) of the refresh frame (see Fig. 7B) is the same stage as a first bias stage (i.e., when (SCAN2) is low) of the refresh frame (see Fig. 7B), and the threshold compensation circuit (T1) is turned on in the third bias stage (i.e., the arbitrary time period during which (SCAN1) is a high voltage) of the refresh frame (see Fig. 7B);
the first bias circuit (T2) is turned on under a control of a scan signal provided by the first scan signal terminal (SCAN2) in the third bias stage (i.e., the arbitrary time period during which (SCAN1) is a high voltage; see Fig. 7B);
the first reset circuit (T5) is turned on (i.e., via (SCAN3)) before the first bias circuit (T2) and the threshold compensation circuit (T1) are turned on in the refresh frame (again, see Fig. 7B), and in the third bias phase (i.e., the arbitrary time period during which (SCAN1) is a high voltage), the first reset circuit (T5) and the threshold compensation circuit (T1) are turned on (i.e., via (SCAN3) and (SCAN1), respectively; see Fig. 7B); and
the data writing circuit (T2) is turned on under a control of a scan signal provided by the second scan signal terminal (SCAN2) in the data writing stage (i.e., the arbitrary time period during which (SCAN2) is a low voltage) and the second bias stage (i.e., another arbitrary time period during which (SCAN2) is a low voltage; see Fig. 7B and note that (T2) is turned on two times via (SCAN2) in the refresh frame, once during the data writing stage, which is the same as the first bias stage, and once during the second bias stage following the data writing stage; see Page 6 through Page 7, Para. [0120]; and Page 9, Para. [0174], [0176]-[0178], and [0181]-[0182]; and again, see Page 6, Para. [0107]-[0110]).
Kim discloses that a level of a bias signal can be different in the refresh frame and the hold frame (see Page 10, Para. [0191] and [0195]-[0197]). However, Kim does not explicitly disclose that the first bias circuit is further configured to have a turn-on duration in the hold frame and a turn-on duration in the refresh frame that is different from the turn-on duration in the hold frame.
However, in the same field of endeavor, Kim2 discloses (see Fig. 2) a pixel circuit (PX; see Page 4, Para. [0063]) comprising a first bias circuit (T7) configured to provide a first bias signal (VAINT) to a driving circuit, and the first bias signal (VAINT) is configured to adjust a bias state of the driving circuit (see (T1, T6) in Fig. 20, for example; and see Page 11, Para. [0114]), wherein a light-emitting cycle of a light-emitting element (EL) comprises a refresh frame (SP) and a hold frame (HP), and wherein (see Fig. 8 and Fig. 10) the first bias circuit (T7) is further configured to have a turn-on duration (see (GB)) in the hold frame (HP) and a turn-on duration (see (GB)) in the refresh frame (SP) that is different from the turn-on duration (again, see (GB)) in the hold frame (HP; see Page 6 through Page 7, Para. [0079]-[0080] and Page 7 through Page 8, Para. [0084]-[0086]). In addition, Kim2 further discloses (see Fig. 22 and Fig. 23) that a time interval between a start moment of the hold frame (HP; see Fig. 22) and a turn-on start moment (see (GB)) of the first bias circuit (T7) in the hold frame (HP) can be different from a time interval between a start moment of the refresh frame (SP; see Fig. 23) and a turn-on start moment (see (GB)) of the first bias circuit (T7) in the refresh frame (SP; see Page 12, Para. [0124]-[0127]). Further still, Kim2 discloses (see Fig. 11) that a level of the first bias signal (VAINT) can be different in the refresh frame (SP) and the hold frame (HP; see Page 8, Para. [0088]-[0091]). Kim2 discloses a number of ways in which the first bias signal can be utilized to adjust a bias state of the driving circuit in order to provide a uniform luminance level across a display device when a pixel circuit is driven at different driving frequencies (see Page 1, Para. [0006]-[0007]). Specifically, Kim2 suggests various driving implementations of a first bias circuit for preventing a luminance difference during a refresh frame and a hold frame when a pixel circuit is driven at different driving frequencies (see Page 3, Para. [0029]). This is a goal that is shared by Kim (see at least Page 1, Para. [0009] of Kim).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kim with the teachings of Kim2, such that a time interval between a start moment of the hold frame and a tum-on start moment of the first bias circuit in the hold frame is different from a time interval between a start moment of the refresh frame and a tum-on start moment of the first bias circuit in the refresh frame, as suggested by both Kim and Kim2, and such that the first bias circuit is further configured to have a turn-on duration in the hold frame and a turn-on duration in the refresh frame that is different from the tum-on duration in the hold frame, as suggested by Kim2, in order to provide a driving implementation of the first bias circuit that prevents a luminance difference during a refresh frame and a hold frame when a pixel circuit is driven at different driving frequencies, thereby providing a uniform luminance level across a display device.
Response to Arguments
Applicant's arguments filed 12 June 2026 have been fully considered but they are not persuasive. The applicant has argued that none of the references relied upon by the examiner in the prior Office Action, particularly Kim and Kim2, teach or fairly suggest the combination of structural and functional features recited in independent Claims 1, 27, 34, and 35. Specifically, the applicant has argued that the combined teachings of Kim and Kim2 do not provide for the features wherein “the refresh frame includes an initialization stage, a third bias stage, a data writing stage, a second bias stage, and a light-emitting stage arranged in time sequence and the data writing stage in the refresh frame is the same stage as a first bias stage in the refresh frame” and “in the third bias stage of the refresh frame, the threshold compensation circuit is turned on” (see Remarks at Pages 23 through 25); “the first bias circuit is turned on under a control of a scan signal provided by the first scan signal terminal in the third bias stage;” “the first reset circuit is turned on before the first bias circuit and the threshold compensation circuit are turned on in the refresh frame, and in the third bias phase, the first reset circuit and the threshold compensation circuit are turned on;” and “the data writing circuit is turned on under a control of a scan signal provided by the second scan signal terminal in the data writing stage and the second bias stage” (see Remarks at Pages 25 through 28). The examiner respectfully disagrees.
Again, the applicant is respectfully reminded that the claims must be given their broadest reasonable interpretation in view of the Specification without reading features from the Specification into the claims. With respect to the claimed “refresh frame,” the applicant has specifically argued that the examiner “has selected isolated signal states and assigned them labels from the claims without any textual basis in Kim” and that the teachings of Kim do not “characterize these signal states as ‘stages’” (see Remarks at Page 24). Respectfully, there is nothing inherent in the terms “initialization stage,” “bias stage,” “data writing stage,” and “light-emitting stage” that would limit these terms to specific “signal states” beyond the “signal states” disclosed by Kim. That is, the claimed “stages” are open to broad interpretation and merely represent some portion or portions of a “refresh frame” that are defined by the limitations established by the claimed invention. It is improper to read unclaimed features from the Specification into the claims. In this respect, the teachings of Kim plainly provide for a refresh frame as shown in Figure 7B that includes an initialization stage, defined by an arbitrary time period during which (SCAN3) is a high voltage, a third bias stage, defined by an arbitrary time period during which (SCAN1) is a high voltage, a data writing stage, defined by an arbitrary time period during which (SCAN2) is a low voltage, a second bias stage, defined by another arbitrary time period during which (SCAN2) is a low voltage, and a light-emitting stage, defined by an arbitrary time period during which (EM) is a low voltage, arranged in time sequence. There is nothing recited in the claimed invention that distinguished the claimed “stages” from these “stages” disclosed by Kim.
The applicant has further argued with respect to the claimed “refresh frame” that “Kim’s data writing stage (when SCAN2 is low) is the same stage as the first bias stage (also when SCAN 2 is low)” and, as such, the teachings of Kim fail both structurally and operationally to provide the claimed “data writing stage” and the claimed “first bias stage” (see Remarks at Page 25). In this regard, the applicant has asserted that the pixel circuit structure of Kim “precludes the Examiner’s interpretation as a matter of circuit physics” and that the “data writing stage” and the “first bias stage” cannot be a same stage. Respectfully, the applicant appears to be importing structural and/or operational features into the claims that are beyond the scope of the claims. The claimed data writing stage is interpreted in Kim to be the arbitrary time period during which (SCAN2) is a low voltage, which is the same as the claimed first bias stage interpreted in Kim to also be the arbitrary time period when (SCAN2) is low. During a data writing stage in Kim (see Fig. 7A and Fig. 7B), when (SCAN2) is low, a data voltage (Vdata) is asserted at transistor (T2), and during a first bias stage in Kim, when (SCAN2) is low), a bias voltage (VOBS) is asserted at transistor (T2). Again, there is nothing recited in or required by the claimed invention that would distinguish these “stages” from the teachings of Kim.
With respect to the claimed timing of the claimed “first bias circuit,” “first reset circuit,” “threshold compensation circuit,” and “data writing circuit,” the applicant has asserted that the teachings of Kim do not suggest the “specific temporal relationship” required by claims and has directed attention to Figure 13 of Kim as supporting this position (see Remarks at Page 26 and Page 28). The examiner respectfully points out that Figure 13 of Kim has not previously been relied upon in the rejection of any of the claims and, therefore, any argument directed to the Figure 13 of Kim is moot. As shown in Figure 3 of Kim, Kim suggests a first bias circuit (T2), a first reset circuit (T5), a second reset circuit (T6), a threshold compensation circuit (T1), a first light-emitting control circuit (T4), and a data writing circuit (T2). Kim further discloses the “specific temporal relationship” required by the claims (see the above rejections). The applicant appears to assert that originally filed Figure 31 provides for distinguishing features of the claimed invention (see Remarks at Page 28). However, as noted in the Response to Amendments section above, the claimed invention is directed to the embodiment of Figure 28 and Figure 29 of the originally filed disclosure, not Figure 31 which appears to be directed to the embodiment of Figure 30. Therefore, any argument directed to Figure 30 and Figure 31 is likewise moot.
Therefore, the rejection of Claims 1-4, 27, and 34-35 is maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
The teachings of Chung et al. (US 11,545,083), initially cited by the examiner in the Office Action mailed 14 March 2024, discloses a number of embodiments of a bias circuit, data writing circuit, and reset circuit pertinent to the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON M MANDEVILLE whose telephone number is (571)270-3136. The examiner can normally be reached Mon - Fri 7:30AM-4:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached at 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON M MANDEVILLE/Primary Examiner, Art Unit 2623
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