DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
This Office Action is in response to Applicant’s application 17/988,267 filed June 23 2026 in which claims 1 to 39 are pending.
Drawings
The drawings submitted on 16 November 2022 have been reviewed and accepted by the Examiner.
Priority
Receipt is acknowledged of paper submitted under 35 U.S.C. 119(a)-(d) or under 35 U.S.C. 120, 121, 365(c), or 386(c) which has been placed of record in the file.
Notation
References to patents will be in the form of (C:L) where C is the column number and L is the line number. References to pre-grant patent publications will be to the paragraph number in the form of (¶ XXXX).
Election/Restrictions
Applicant’s election without traverse of claims 1-6 in the reply filed on January 20 2026 is acknowledged. Claims 7-39 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4 and 6 are rejected under AIA 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2021/0057436 A1).
Regarding claim 1, Kim teaches a resistive memory device (Figs.1-20) comprising:
a stack structure (10; Fig.15; ¶ 0074) in which a plurality of interlayer insulating layers (60; Fig.20; ¶0027) and a plurality of conductive layers (24; Fig.20; ¶ 0056) are alternately stacked (60 and 24; Fig.20);
a hole passing through the stack structure in a vertical direction (through via in the vertical direction; Fig.20);
a gate insulating layer (28; Fig.15; ¶ 0053), a channel layer (44, Fig.15; ¶ 0045), and a variable resistance layer (38, Fig.15; ¶ 0042) sequentially formed along a sidewall of the hole (along the sidewall of the hole formed through 24 and 60; Fig.15); and
a high dielectric layer (70; Fig.15; ¶ 0033; formed from “high-k”) formed between the channel layer (44) and the gate insulating layer (28), the high dielectric layer (70; Fig.15) being adjacent to the plurality of interlayer insulating layers (60; Fig.15);
wherein the gate insulating layer (28; Fig.15) is disposed along sidewalls of the plurality of inter insulating layers (60; Fig.15, every layer has 4 sidewalls (right, left, bottom and top)) and sidewalls of the plurality of conductive layers (24, fig.15).
Regarding claim 4, Kim teaches wherein the high dielectric layer (28; Fig.15; ¶ 0055) is disposed only in the space between vertically adjacent conductive layers (16), among the plurality of conductive layers (24), and wherein the high dielectric layer (28) that is disposed in the space between the plurality of protruding conductive layers has a concave sidewall (the top surface combined with the side surface and bottom surface; Fig.21) that is in contact with the channel layer (all layers are in electrical /thermal contact).
Regarding claim 6, Kim teaches wherein the channel layer includes a concave area (44; has a concave area) that is adjacent to the plurality of interlayer insulating layers (60) and a substantially straight area that is adjacent to the plurality of conductive layers (44 has a straight area close to 24).
Claims 1, 3 and 5 are rejected under AIA 35 U.S.C. 102(a)(1) as being anticipated by Shim et al. (US 2021/0151461 A1; hereinafter “Shim”).
Regarding claim 1, Shim teaches a resistive memory device (Figs.1-19F) comprising:
a stack structure (100; Fig.1-3A; ¶ 00028) in which a plurality of interlayer insulating layers (120; Fig.2; ¶0028) and a plurality of conductive layers (130; ¶ 0028) are alternately stacked (120 and 130);
a hole passing through the stack structure in a vertical direction (through via in the vertical direction; Figs.2-3A);
a gate insulating layer (132; Fig.3A; ¶ 0034), a channel layer (140, Fig.3A; ¶ 0034), and a variable resistance layer (144, Fig.3A; ¶ 0046) sequentially formed along a sidewall of the hole (along the sidewall of the hole formed through 130 and 120; Fig.3A); and
a high dielectric layer (142; Fig.3A; ¶ 0044; “a high-k material”) formed between the channel layer (144) and the gate insulating layer (132), the high dielectric layer 142; Fig.3A) being adjacent to the plurality of interlayer insulating layers (142 is adjacent to the plurality of 120; Fig.3A).
Regarding claim 3, Shim teaches the high dielectric layer (142; Fig.3A; ¶0044) is disposed only in a space between the plurality of protruding conductive layers (135; Fig.3A; ¶0032 and 0042).
Regarding claim 5, Shim teaches the channel layer has a wave-like pattern extending in the vertical direction (140; Fig. 4C; ¶ 0036).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2021/0057436 A1).
Regarding claim 2, Kim does not explicitly teach the high dielectric layer has a higher dielectric constant that is higher than the gate insulating layer.
However, Kim teaches in ¶ 0054 “materials 70[the high dielectric layer] and 28 [gate insulation layer] may comprise a same composition as one another, or may comprise different compositions relative to one another.” (Since the two layers can have different compositions relative to one another, than the dielectric constant can be higher or smaller than the gate insulation layer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention, to have the high dielectric layer has a higher dielectric constant that is higher than the gate insulating layer in the device of Kim since such a modification merely involves choosing from a finite number of known dielectric material to improve the relative dielectric constants of the gate dielectric layer and the high k dielectric which would have been within the routine skill of the art and yields no more than predictable results.
Claims 3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2021/0057436 A1) as applied to claim 1 above and further in view of Shim et al. (US 2021/0151461 A1; hereinafter “Shim”).
Regarding claim 3, Kim teaches wherein the plurality of conductive layers (24; Fig.15) protrude farther into the hole compared to the plurality of interlayer insulating layers (60; Fig.15).
Kim does not teach wherein the high dielectric layer is disposed only in a space between the plurality of protruding conductive layers.
However, Shim teaches in the same field of endeavor wherein the high dielectric layer (142; Fig.3A; ¶0044) is disposed only in a space between the plurality of protruding conductive layers (135; Fig.3A; ¶0032 and 0042).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention, to have the high dielectric layer is disposed only in a space between the plurality of protruding conductive layers in the device of Kim as taught by Shim for the purpose of improving the reliability of the memory device (¶0154).
Regarding claim 5, Kim does not teach wherein the channel layer has a wave-like pattern extending in the vertical direction.
However, Shim teaches the channel layer has a wave-like pattern extending in the vertical direction (140; Fig. 4C; ¶ 0036).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention; to have, the channel layer has a wave-like pattern extending in the vertical direction in the device of Kim as taught by Shim since such modification would have involved a mere change in size/shape of a component. A change in shape is generally recognized as being with the level of ordinary skill in the art MPEP § 2144.04 IV B.
Response to Arguments
Applicant's arguments filed on June 23 2026 have been fully considered but they are not persuasive.
Applicant Alleges:
Kim fails to teach or suggest "wherein the gate insulating layer is disposed along sidewalls of the plurality of interlayer insulating layers and sidewalls of the plurality of conductive layers" as set forth in claim 1 as amended. FIG. 20 of Kim shows a high-k dielectric material 28 formed to surround surfaces of a pair of conductive materials 24 and 26, and therefore is not formed along a sidewall of the first material 60. Thus, Kim fails to teach or suggest "wherein the gate insulating layer is disposed along sidewalls of the plurality of interlayer insulating layers and sidewalls of the plurality of conductive layers" as set forth in claim 1 as amended.
Examiner’s Response:
Examiner respectfully disagree with the applicant for the following reasons:
The prior art reference Kim et al. (US 2021/0057436 A1) teaches the new amended limitations: wherein the gate insulating layer (28; Fig.15) is disposed along sidewalls of the plurality of inter insulating layers (60; Fig.15, every layer has 4 sidewalls (right, left, bottom and top)) and sidewalls of the plurality of conductive layers (24, fig.15).
The office interprets that each layer comprises four sidewalls. The direction of the sidewall can be defined in the claim, however, if the claim does not define the direction of the layer, then any side the layer can be a sidewall. Regardless if the sidewall is formed on the right side, left side, top side or bottom side.
Here, the claim does not define the direction of the layers. The sidewalls can be formed on top of each other instead of being formed on the right and left side of each other. Annotate figure 15 below shows the sidewalls of the conductive layer (24, dotted line) and sidewalls of inter insulating layer (60; solid line). The high dielectric layer (28, annotated figure below) shows that the high dielectric layer is formed along the sidewall of each of the layers of 24 and 60.
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If applicant further define the sidewalls are formed with respect to the top surface and bottom surface of each layer and high dielectric layer is formed on the sidewalls than the limitation seems to further align with the interpretation of the applicant and might overcome the prior art.
However, as the amendment presented the prior art reference teaches the above limitation and rejection of claim 1 under AIA 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2021/0057436 A1) is deemed proper and maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mounir S Amer whose telephone number is (571)270-3683. The examiner can normally be reached Monday-Friday 9:00-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Mounir S Amer/Primary Examiner, Art Unit 2818
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