DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 11-15 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication 2012/0044024 to Wagner (Wagner) in view of US Patent Application Publication 2024/0233854 to Akiyoshi (Akiyoshi).
Claim 1
With regard to or each of a plurality of predetermined delay times: providing a first signal to a data input of a first latch of a ring oscillator circuit via a delay block, the delay block configured to delay the providing of the first signal to the data input of the first latch by the predetermined delay time; Wagner teaches a latched ring oscillator with a plurality of latch-based delay stages (Fig. 2, latched ring oscillator circuit; pars. 22, 23) and providing a input to Vin via a NOR element, that corresponds to a delay to a latch input (Fig. 3, Vin, NOR 32, latch 34; par. 26).
With regard to providing the first signal to a first logic clock buffer (LCB); Wagner teaches providing the input signal to a clock via an XOR circuit element (Fig. 3, XOR 40; par. 26).
With regard to generating a clock signal by the first LCB responsive to receiving the first signal; Wagner teaches that the output of the XOR is input to the clock input of latch (Fig. 3, XOR 40, latch 34, E (clock) input; par. 26).
With regard to providing the clock signal to a clock input of the first latch; Wagner teaches the output of the XOR element is input to the clock input of the latch 34 (par. 26).
Wagner does not teach determining from an output of the ring oscillator circuit that the ring oscillator circuit is in either an oscillating state or a non-oscillating state; and determining at least one timing window parameter for the first latch based on one or more of the plurality of delay times that are associated with an oscillating state of the ring oscillator circuit.
Akiyoshi teaches measuring the delay characteristic of a transistor using a plurality of ring oscillators using multiple characteristic measurement circuits based on the frequency of the ring oscillator (par. 19). The frequency of the ring oscillator will indicate whether the ring oscillator is oscillating. It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the delay measurement, as taught by Wagner, to include using the frequency of the ring oscillator to determine delay characteristics, as taught by Akiyoshi, because then the precision of the delay characteristic measurement would have been improved (Akiyoshi, par. 7).
Claim 2
Wagner does not teach that the determining that the ring oscillator circuit is in either an oscillating condition or non-oscillating condition is determined using a plurality of ring oscillator circuits each having a delay block configured for the predetermined delay time. Akiyoshi teaches that each characteristic measurement circuit includes a ring oscillator (par. 19). It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the delay measurement, as taught by Wagner, to include using the frequency of the ring oscillator to determine delay characteristics using multiple characteristic measurement circuits, as taught by Akiyoshi, because then the precision of the delay characteristic measurement would have been improved (Akiyoshi, par. 7).
Claim 11
Wagner teaches that the first signal comprises a start-up pulse signal (Fig. 2, Vin 42, par. 26).
Claim 12
Wagner teaches that the at least one timing window parameter includes one or more of a setup time or a hold time of the first latch (par. 27).
Claim 13
With regard to a ring oscillator circuit comprising: a first latch including a data input, a clock input, and a latch output; Wagner teaches a latched ring oscillator with a plurality of latch-based delay stages (Fig. 2, latched ring oscillator circuit; pars. 22, 23; Fig. 3, latch 34, data input A, clock input E, latch output Vout).
With regard to a delay block coupled to the data input of the first latch, the delay block configured to receive a first signal and delay providing of the first signal to the data input of the first latch by a predetermined delay time; Wagner teaches providing a input to Vin via a NOR element, that corresponds to a delay to a latch input (Fig. 3, Vin, NOR 32, latch 34; par. 26).
With regard to a first logic clock buffer (LCB) coupled to the clock input of the first latch, the first LCB configured to receive the first signal, generate a clock signal responsive to receiving the first signal, and provide the clock signal to the clock input of the first latch; Wagner teaches that the output of the XOR is input to the clock input of latch (Fig. 3, XOR 40, latch 34, E (clock) input; par. 26).
Wagner does not teach a measurement circuit configured to determine from an output of the ring oscillator circuit that the ring oscillator circuit is in either an oscillating state or a non-oscillating state.
Akiyoshi teaches measuring the delay characteristic of a transistor using a plurality of ring oscillators using multiple characteristic measurement circuits based on the frequency of the ring oscillator (par. 19). The frequency of the ring oscillator will indicate whether the ring oscillator is oscillating. It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the delay measurement, as taught by Wagner, to include using the frequency of the ring oscillator to determine delay characteristics, as taught by Akiyoshi, because then the precision of the delay characteristic measurement would have been improved (Akiyoshi, par. 7).
Claim 14
Wagner does not teach that the measurement circuit is further configured to operate the ring oscillator circuit for each of a plurality of predetermine delay times to determine that the ring oscillator is in either the oscillating state or the non-oscillating state for the predetermined delay time, and determine at least one timing window parameter for the first latch based on one or more of the plurality of predetermined delay times that are associated with an oscillating state of the ring oscillator circuit.
Akiyoshi teaches that each characteristic measurement circuit includes a ring oscillator (par. 19). It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the delay measurement, as taught by Wagner, to include using the frequency of the ring oscillator to determine delay characteristics using multiple characteristic measurement circuits, as taught by Akiyoshi, because then the precision of the delay characteristic measurement would have been improved (Akiyoshi, par. 7).
Claim 15
Wagner teaches that the at least one timing window parameter includes one or more of a setup time or a hold time of the first latch (par. 27).
Claim 20
Wagner teaches that the first signal comprises a start-up pulse signal (Fig. 2, Vin 42, par. 26).
Claim(s) 4-7 and 16-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wagner in view of Akiyoshi as applied to claims 1 and 13 above, and further in view of US Patent Application Publication 2023/0275572 to Raja et al. (Raja).
Claims 4 and 16
Wagner and Akiyoshi teaches all the limitations of claim 1 upon which claim 4 depends and claim 13 upon which claim 16 depends. Wagner and Akiyoshi do not teach that the delay block comprises a plurality of inverter delay stages having a total delay equal to the predetermined delay time. Raja teaches configuring delay using multiple delay elements which may include inverters (Figs. 3A-3E, inverters; Fig. 4, multiplexers 406, 408, par. 36). It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the delay measurement combination, as taught by Wagner and Akiyoshi, to include configuring multiple inverters for different delays, as taught by Raja, because then the measurement of delay would have been more precise (Raja, par. 18).
Claims 5 and 17
Wagner and Akiyoshi teaches all the limitations of claim 1 upon which claim 5 depends and claim 13 upon which claim 17 depends. Wagner and Akiyoshi do not teach that the delay block comprises a variable digital delay stage having a delay configured to be set to the predetermined delay time. Raja teaches configuring delay using elements that can be implemented using analog or digital elements (Figs. 3A-3E, inverters; Fig. 4, multiplexers 406, 408; par. 36). It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the delay measurement combination, as taught by Wagner and Akiyoshi, to include configuring multiple inverters for different delays, as taught by Raja, because then the measurement of delay would have been more precise (Raja, par. 18).
Claims 6 and 18
Wagner and Akiyoshi teaches all the limitations of claim 1 upon which claim 6 depends and claim 13 upon which claim 18 depends. Wagner and Akiyoshi do not teach that the delay block comprises a variable analog delay circuit having a delay configured to be set to the predetermined delay time. Raja teaches configuring delay using elements that can be implemented using analog or digital elements (Figs. 3A-3E, inverters; Fig. 4, multiplexers 406, 408; par. 36). It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the delay measurement combination, as taught by Wagner and Akiyoshi, to include configuring multiple inverters for different delays, as taught by Raja, because then the measurement of delay would have been more precise (Raja, par. 18).
Claims 7 and 19
Wagner and Akiyoshi teaches all the limitations of claim 1 upon which claim 7 depends and claim 13 upon which claim 19 depends. Wagner and Akiyoshi do not teach that the delay block comprises a digital tap circuit including digital multiplexing circuitry to tap into a chain of a plurality of delay stages to configure a delay of the delay block to the predetermined delay time. Raja teaches configuring delay using elements that can be implemented using analog or digital elements (Figs. 3A-3E, inverters; Fig. 4, multiplexers 406, 408; par. 36). It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the delay measurement combination, as taught by Wagner and Akiyoshi, to include configuring multiple inverters for different delays, as taught by Raja, because then the measurement of delay would have been more precise (Raja, par. 18).
Allowable Subject Matter
Claims 3 and 8-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The primary reason for indicating allowable subject matter in claim 3 is because the cited prior art does not teach a method for direct measurement of a latch timing window that includes combining the outputs of each of the plurality of ring oscillator circuits into a multiplexed output signal, wherein the oscillating state of each of the ring oscillator circuits is determined based on the multiplexed signal.
The primary reason for indicating allowable subject matter in claim 8-10 is because the cited prior art does not teach a method for direct measurement of a latch timing window that includes mapping the oscillating state or non-oscillating state and associated predetermined delay time for each of the predetermined time delays to latch tuning bit values; and tuning a latch timing of a second latch using the latch tuning bit values.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MANUEL L BARBEE whose telephone number is (571)272-2212. The examiner can normally be reached M-F: 9-5:30..
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/MANUEL L BARBEE/Primary Examiner, Art Unit 2857