Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status
This instant application No. 17/988748 has
Claims 9 and 10 are cancelled.
Claims 1-8, 11-22 are pending. The effective filing date of this application is 09/12/2022.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 11, 19, 21 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Heller et al (2018/0322051) hereafter Heller in view of SEO et al (2015/0149789) hereafter SEO.
Regarding claim 1, Heller discloses A storage device (Heller: Fig. 2A:’ ‘non-volatile storage system 100’”), comprising:
a volatile storage (Heller: Fig. 2B: ‘data cache 156’);
a non-volatile storage (Heller: Fig. 2B: ‘non-volatile memory 142’);
a backup power source configured to provide backup power to the volatile storage (Heller: [0061]: “the storage system 100 comprises a capacitor that is configured to hold enough charge to power the storage system 100 for more than the pre-defined time delay);
a connector to connect the storage device to a processor (Heller: Fig. 2A: [0045]: “Front end module 108 includes a host interface 120 (here, with a command queue 123) and a physical layer interface (PHY) 122 that provide the electrical interface with the host or next level storage controller”, <examiner note: Figure 2A shows the non-volatile system connects to the host through host interface that facilitates transfer for data, control signals, and timing signals>); and
a controller (Heller: Fig. 2A: ‘controller 102’) configured to use the volatile storage as a cache for the non-volatile storage (Heller: [0049]: “some storage systems operate in a “cache mode,” in which data sent to the storage system for writing in the storage system's non-volatile memory is first stored in a volatile write cache”), wherein the controller is configured to copy a data from the volatile storage to the non- volatile storage based at least in part on receiving a signal indicating that data has been copied into the volatile storage (Heller: [0049]: “the host can send a “flush command” to the storage system, which triggers the storage system to write the data that is stored in the volatile write cache into the non-volatile memory”; examiner note: when data from the host first is stored in a volatile cache, then host send a flush command (interpreted as flush signal) to write data to non-volatile memory. Thus, the flush signal, being received by the storage system, implicitly indicates data sent by the host and stored in the write cache).
Heller does not explicitly disclose data has been copied from a cache of the processor, wherein the processor is external to the storage device.
However, SEO discloses data has been copied from a cache of the processor, wherein the processor is external to the storage device (SEO: Fig. 2: host system 2000 includes CPU 210 and RAM 220; [0058]: “Host data is stored in RAM 220. For example, RAM 200 may be a volatile memory, such as DRAM, SRAM, or the like. CPU 210 controls host system 2000 and executes arithmetic logic operations or data processing. Also, CPU 210 generates a host command for performing a write operation or a read operation in memory system 1000”; [0059]: “ CPU 210 generates the first type of host command based on the type of host data to be stored in memory system 1000, and transmits the first type of host command to memory system 1000”; [0060]: “The first type of host command is a command for performing an operation of writing host data to a storage area of RAM 130 allocated to support a compression function or an encryption function in memory system 1000. The second host command is a command for performing an operation of reading data stored in RAM 130 of memory system 1000 and writing the read data to NVM 200 of memory system 1000”).
Thus, Heller discloses data sent by the host for writing in the storage system's non-volatile memory is first stored in a volatile write cache. Host then send a flush command (interpreted as flush signal) to write data to non-volatile memory. The flush signal, being received by the storage system, implicitly indicates data sent by the host and stored in the write cache. Heller does not explicitly disclose data sent from a cache of the processor external to the storage device. However, in addition to Heller, SEO discloses a host includes a processor and RAM (interpreted as cache of processor) in which processor generates and sends a RAM flush command for performing a write operation to write host data from its RAM to Non-Volatile memory device of the memory system. Therefore, the combination of Heller and SEO disclose all limitations of claim 1.
Disclosures by Heller and SEO are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate writing data from volatile to non-volatile storage basing on receiving flush command taught by Heller to include flushing data transferred by host processor to a NVM device disclosed by SEO. The motivation for flushing data transferred by host processor to a NVM device by paragraph [0007] of SEO is for preventing performance degradation that may otherwise occur in a system due to a data compression process or an encryption process, and they may also reduce power consumption of the system.
Regarding claim 11, Heller discloses A method, comprising:
receiving a signal at a connector of a storage device indicating that data has been copied into a volatile storage of the storage device (Heller: Fig. 2A: ‘controller 102’ ; [0045]: “Front end module 108 includes a host interface 120”; [0049]: “the host can send a “flush command” to the storage system, which triggers the storage system to write the data that is stored in the volatile write cache into the non-volatile memory”; examiner note: when data from the host first stored in a volatile cache, then host send a flush command (interpreted as flush signal) to write data to non-volatile memory); and
copying the data from the volatile storage of the storage device to a non-volatile storage of the storage device based at least in part on receiving the signal (Heller: [0049]: “the host can send a “flush command” to the storage system, which triggers the storage system to write the data that is stored in the volatile write cache into the non-volatile memory”);
Heller does not explicitly disclose data has been copied from a cache of the processor, wherein the processor is external to the storage device.
However, SEO discloses data has been copied from a cache of the processor, wherein the processor is external to the storage device (SEO: Fig. 2: host system 2000 includes CPU 210 and RAM 220; [0058]: “Host data is stored in RAM 220. For example, RAM 200 may be a volatile memory, such as DRAM, SRAM, or the like. CPU 210 controls host system 2000 and executes arithmetic logic operations or data processing. Also, CPU 210 generates a host command for performing a write operation or a read operation in memory system 1000”; [0059]: “ CPU 210 generates the first type of host command based on the type of host data to be stored in memory system 1000, and transmits the first type of host command to memory system 1000”; [0060]: “The first type of host command is a command for performing an operation of writing host data to a storage area of RAM 130 allocated to support a compression function or an encryption function in memory system 1000. The second host command is a command for performing an operation of reading data stored in RAM 130 of memory system 1000 and writing the read data to NVM 200 of memory system 1000”).
Thus, SEO discloses a host includes a processor and RAM (interpreted as cache of processor). The processor generates and sends a RAM flush command for performing a write operation to write host data from its RAM to Non-Volatile memory device of the memory system.
Disclosures by Heller and SEO are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate writing data from volatile to non-volatile storage basing on receiving flush command taught by Heller to include flushing data transferred by host processor to a NVM device disclosed by SEO. The motivation for flushing data transferred by host processor to a NVM device by paragraph [0007] of SEO is for preventing performance degradation that may otherwise occur in a system due to a data compression process or an encryption process, and they may also reduce power consumption of the system.
Regarding claim 19, these claims limitations are significantly similar to those of claim 11, and, therefore, are rejected on the same grounds.
Regarding claim 21, Heller combined further discloses The storage device according to claim 1, wherein the controller is configured to copy a data from the volatile storage to the non-volatile storage based at least in part on receiving a signal indicating that the data has been completely copied from the cache of the processor into the volatile storage (Heller: [0049]: “the host can send a “flush command” to the storage system, which triggers the storage system to write the data that is stored in the volatile write cache into the non-volatile memory”; examiner note: when data received from the host first is stored in a volatile cache, then host send a flush command (interpreted as flush signal) to write data to non-volatile memory).
Regarding claim 22, these claims limitations are significantly similar to those of claim 21, and, therefore, are rejected on the same grounds.
Claims 2 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Heller and SEO as applied to claims 1 and 11 respectively above, and further in view of Han et al (2019/0206494) hereafter Han.
Regarding claim 2, Heller and Seo does not disclose exactly current limitation of claim 2.
However, Han discloses The storage device according to claim 1, wherein:
the connector includes a pin (Han: Fig. 11: Flushing pin 135); and
the controller is further configured to copy the data from the volatile storage to the non- volatile storage based at least in part on receiving the signal over the pin (Han: [0099]: “the flushing request may be made by a pin control, that is, in such a way that the input/output pad unit 130 is provided with a dedicated flushing pin 135 for requesting flushing, and the controller 300 may operate the flushing pin 135 to request flushing. Then, the flushing pin 135 may force all programming data temporarily stored in the data buffer 210 to be programmed in the non-volatile memory cell array”).
Disclosures by Heller, SEO and Han are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate writing data from volatile to non-volatile storage basing on receiving flush command taught by Heller/Seo to include a flushing pin disclosed by Han. The motivation for include the flushing pin by paragraph [0010] of Han is for minimizing the idle time and thus improving performance of the memory system.
Regarding claim 13, these claims limitations are significantly similar to those of claim 2, and, therefore, are rejected on the same grounds.
Claims 3, 4, 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Heller and SEO as applied to claims 1, 11 and 19 respectively above, and further in view of Natu (2020/0192798).
Regarding claim 3, Heller and SEO does not disclose exactly current limitation of claim 3.
However, Natu discloses The storage device according to claim 1, wherein the signal includes a Global Persistent Flush (GPF) message (Natu: [0065]: “CPU 605 may likewise transmit GPF cache flush request messages (e.g., 915g, 915h) (and any other flush request messages (e.g., 910b)) to devices (e.g., 660, 845, 860) directly connected to the CPU 605”).
Disclosures by Heller, SEO and Natu are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate writing data from volatile to non-volatile storage basing on receiving flush command taught by Heller/SEO to include a global persistent flush disclosed by Natu. The motivation for include a global persistent flush by paragraph [0061] of Natu is for improved implementation to trigger the GPF in response to an indication of an imminent power loss.
Regarding claim 14, these claims limitations are significantly similar to those of claim 3, and, therefore, are rejected on the same grounds.
Regarding claim 4, Heller and SEO does not disclose exactly current limitation of claim 4.
However, Natu further discloses The storage device according to claim 3, wherein the storage device is remote from a component that sends the GPF message (Natu: Fig. 8: CPU 605 that sends a GPF message is remote from the persistent memory 830).
Disclosures by Heller, SEO and Natu are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate writing data from volatile to non-volatile storage basing on receiving flush command taught by Heller/SEO to include a global persistent flush disclosed sent by external component by Natu. The motivation for include a global persistent flush by paragraph [0061] of Natu is for improved implementation to trigger the GPF in response to an indication of an imminent power loss.
Regarding claim 15, these claims limitations are significantly similar to those of claim 4, and, therefore, are rejected on the same grounds.
Claims 5, 12 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Heller and SEO as applied to claims 1, 11 and 19 respectively above, and further in view of Jenne (2019/0012101) hereafter Jenne.
Regarding claim 5, Heller and SEO do not disclose exactly current limitation of claim 5.
However, Jenne discloses The storage device according to claim 1, wherein the controller is configured to copy the data from the volatile storage to the non-volatile storage based at least in part on receiving the signal from a platform controller hub (Jenne: [0035]: “the processing complex 120 can include a Platform Control Hub (PCH), as used with Intel-based processors, to which the CPLD sends a signal to trigger Asynchronous DRAM Refresh (ADR). In response, the PCH will notify the processing complex 110 to flush its caches, and other volatile information, to NVDIMM 130 in anticipation of losing power After processing complex 110 has finished flushing desired information to the NVDIMM”).
Disclosures by Heller, SEO and Jenne are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate writing data from volatile to non-volatile storage basing on receiving flush command taught by Heller/SEO to include a Platform Control Hub disclosed by Jenne. The motivation for include a Platform Control Hub by paragraph [0035] of Jenne is for flushing its caches, and other volatile information, to NVDIMM in anticipation of losing power After processing complex has finished flushing desired information to the NVDIMM.
Regarding claims 12 and 20, these claims limitations are significantly similar to those of claim 5, and, therefore, are rejected on the same grounds.
Claims 6, 7, 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Heller and SEO as applied to claims 1 and 11 above, and further in view of Ishikawa et al (2008/0086659).
Regarding claim 6, Heller and SEO does not disclose exactly current limitation of claim 6.
However, Ishikawa discloses The storage device according to claim 1, wherein the controller is further configured to copy a second data from the volatile storage to the non-volatile storage based at least in part on a change of a primary power for the storage device (Ishikawa: Fig. 3: a second data (P2) to be continuously saved, using the DC power source, to the nonvolatile memory when the main supply power AC failures; [0014]: “a control section adapted to start saving of the data in the volatile memory into the nonvolatile memory when the detecting circuit has output the momentary interruption detecting signal, continue save of the data”).
Disclosures by Heller, SEO and Ishikawa are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate writing data from volatile to non-volatile storage basing on receiving flush command taught by Heller/SEO to include a capacitor to store the electric charge disclosed by Ishikawa. The motivation for include the capacitor to store the electric charge by paragraph [0004] of Ishikawa is for supplying a DC voltage to the circuit component to save data for some time after suspension of the AC input.
Regarding claim 16, these claims limitations are significantly similar to those of claim 6, and, therefore, are rejected on the same grounds.
Regarding claim 7, Heller and SEO does not disclose exactly current limitation of claim 7.
However, Ishikawa further discloses The storage device according to claim 6, wherein the storage device further comprises a power monitor configured to send a second signal to the controller that the primary power for the storage device is changed (Ishikawa: [0014]: “a detecting circuit for outputting a momentary interruption detecting signal when a power source voltage is below a first threshold voltage, and a power failure detecting signal when the power source voltage is below a second threshold voltage that is lower than the first threshold voltage”).
Disclosures by Heller, SEO and Ishikawa are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate writing data from volatile to non-volatile storage basing on receiving flush command taught by Heller/SEO to include a monitoring circuit disclosed by Ishikawa. The motivation for include the monitoring circuit by paragraph [0014] of Ishikawa is for detecting a power failure from the power source voltage to keep saving data in the volatile memory into the nonvolatile using the capacitor.
Regarding claim 17, these claims limitations are significantly similar to those of claim 7, and, therefore, are rejected on the same grounds.
Claims 8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Heller, SEO and Ishikawa as applied to claims 6 and 16 above, and further in view of Freerksen et al (6314491) hereafter Freerksen.
Regarding claim 8, Heller, SEO and Ishikawa do not disclose exactly current limitation of claim 8.
However, Freerksen discloses The storage device according to claim 6, wherein the controller is configured to copy the data from the volatile storage to the non-volatile storage based at least in part on receiving the signal and a dirty block indicator for the data (Freerksen: column 17, lines 46-55: “the L2 cache determines that there is a set presence bit, then the modified data is in an L1 cache, and must be flushed. In this situation, in step 404 the request for ownership is refused to permit time for the L1 cache to flush the data to the main memory. Then in step 406, the L2 cache sends a flush writeback command to the L1 cache having the set presence bit, to cause that L1 cache to flush the data back to main memory”).
Disclosures by Heller, SEO, Ishikawa and Freerksen are analogous because they are in the same field of endeavor of memory access and control.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate writing data from volatile to non-volatile storage basing on receiving flush command taught by Heller/SEO/Ishikawa to include writing back modified data indicated by a set bit disclosed by Freerksen. The motivation for writing back modified data indicated by a set bit by column 2, lines 61-63 of Freerksen is for improving cache performance in a multiprocessor environment.
Regarding claim 18, these claims limitations are significantly similar to those of claim 8, and, therefore, are rejected on the same grounds.
Response to Arguments
In response to Applicant’s remarks filed on 12/03/2025:
Applicant’s arguments respect to claims 1, 11 and 19 have been considered but are not persuasive.
Applicant argues (page 10 of arguments) the prior arts of record do not teach or suggest that the flush command is sent based on the data being copied from the processor cache. Also the RAM of the prior arts would not be a processor cache. Examiner respectfully disagrees.
Heller discloses a storage system includes a cache, non-volatile memory and a controller (see Fig. 2A, paragraph [0049]). In response to receive data for writing to the storage from a host, the controller first store the data in the cache and the storage system may sent the host a completion signal after storing data in the cache. The host can send a “flush command” ( disclosed as signal) to the storage system to make sure that the data from the cache being committed to the non-volatile memory. The flush command triggers the storage system to write the data stored in the cache into the non-volatile memory. Here, Heller send the flush command basing on the data being stored in the cache.
Seo, in addition to Heller, discloses a data processing system includes a memory system and a host system (see Fig. 2, paragraph [0060]). The host system includes a CPU and a RAM ( disclosed as a cache). The CPU of the host system generates a first host command to process data in the RAM for perform an operation of writing data from the RAM to a RAM of memory system (discloses as a cache of the memory system). The CPU also generates a second host command to perform an operation of reading data stored in RAM of memory system and writing the read data to NVM of memory system. The claim language recited “a cache of the processor” which does not mean that the cache is internal cache of the processor. Therefore, Seo discloses data in the RAM is processed by the CPU to write to the memory system meeting the claim language as cited in claims 1, 11 and 19.
As such the combination of Heller and Seo meet all limitations of claims 1, 11 and 19.
Regarding claims 21 and 22, Applicant argues (see page 12 of arguments) the prior arts of record do not teach the signal indicates that the data has been completely copied from the cache of processor into the volatile storage. Examiner respectfully disagrees.
As described in claim 1 above, the combination of Heller and Seo disclose the CPU processes data from RAM to send to volatile cache. After data is stored in the volatile cache (here, data is completely copied to the volatile cache of the storage system), the flush command is sent to trigger to write data from the volatile cache to the non-volatile storage. Thus, the combination of Heller and Seo disclose the limitations of claims 21 and 22.
Applicant’s arguments respect to claims 3 and 14 (page 13 of arguments) have been considered but are not persuasive.
Regarding claims 3 and 14, Applicant argues the accelerator of Natu is not storage device and flushing the data to persistent memory which is not a non-volatile storage of storage device. Thus Natu does not teach the features of the claim. Examiner respectfully disagrees.
Natu discloses a global persistent flush (GPF) cache flush request messages transmitted by a CPU to accelerators (see Fig. 9A, paragraph [0065). These accelerator devices includes its own local storage (e.g. cache, here considered a storage). In response to receiving the GPF cache flush request message, these accelerators cause data stored in its local storage to be flushed to one or more persistent memory (here the non-volatile memory, by the definition persistent memory is a high speed, non-volatile memory that retains data even after power loss). Further, the combination of Heller and Seo also disclose flush command to write data from the local cache to the non-volatile memory. Therefore, Natu alone and/or combined with Heller and SEO discloses the features of claims 3 and 14.
Applicant’s arguments respect to claims 4 and 15 (pages 13-14 of arguments) have been considered but are not persuasive.
Regarding claims 4 and 15, Applicant argues Natu does not teach the feature the storage device is remote from the component that sends the GPF message. Examiner respectfully disagrees.
It is noted that the features upon which applicant relies on the specification are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Based on the claimed language, the “remote” component is reasonable interpreted as any component is not resided in another component. Therefore, the CPU, cited by Natu, in which the GPF message transmitted to cause data being flushed from the cache to the persistent memory, discloses the feature of claims 4 and 15.
Regarding claims 5, 12 and 20, Applicant argues (see pages 14-15 of arguments) the prior arts of record do not teach the flush command originate from a flatform controller hub. Examiner respectfully disagrees.
Jenne discloses (please see paragraph [0035]) the processing complex includes a Platform Control Hub (PCH) used with Intel-based processors. Jenne shows the feature PCH notifies the processing complex to flush its caches, and other volatile information, to NVDIMM 130 in anticipation of losing power. As such, Jenne discloses the flush signal that originated from the PCH.
Regarding claims 8 and 18, Applicant argues (see page 15-16 of the arguments) the prior arts of record do not teach copying the data from the volatile storge to the non-volatile storage based at least in part on receiving the signal and a dirty block indicator for the data. Examiner respectfully disagrees.
Freerksen discloses method to perform data consistency of a system including one or more processors and cache systems (please see column 17, lines 46-55). In response to a request to process a cached data in a system, a set presence bit is determined to check for whether or not the cached data is modified data. If the requested cached data is modified then a flush writeback command is issued to cause the modified data is flush to the main memory. Thus, Freerksen discloses this feature of the claims 8 and 18.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAN V DOAN whose telephone number is (571)270-7250. The examiner can normally be reached Monday, Wednesday and Thursday from 10:45 AM to 4:45PM EST.
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/HAN V DOAN/Examiner, Art Unit 2137
/PRASITH THAMMAVONG/Primary Examiner, Art Unit 2137