CTNF 17/988,884 CTNF 77036 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Objection Claim 8 is objected because there is no antecedent basic for “the sampled voltage”. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1 - is/are rejected under 35 U.S.C. 103 as being unpatentable over Surendranath et al. (US 20220021789) in view of Mouri et al. (US 20100194618) . As to claim 1, Surendranath et al.’s figure 1 discloses an apparatus, comprising: a circuit (not shown that provides S1) to generate a clock (S1) having a period with a duty cycle less than or equal to 90% (see figure 3. Furthermore, selecting the duty cycle for S1 as claimed is seen as an obvious design preference to ensure optimal performance, see MPEP 2144.05); and logic (140 and 154) to determine a difference (by 152) in an input voltage (generated by 120) between a first time ( based on S1) and a second time (based on S2), at least in part based on the duty cycle of the clock, and to produce a first signal (generated by 154). Figure 1 fails to show the detail of ADC 154. However, Mouri et al.’s figure 1 shows a precise ADC. It would have been obvious to one having ordinary skill in the art to use Mouri et al.’s ADC for Surendranath et al.’s ADC for the purpose of providing more precise digital signals. Thus, the modified Surendranath et al.’s figure 1 shows that the first signal is at least in part based on the difference in the input voltage and a first predetermined threshold (Mouri et al.’s V1-V7). As to claim 2, the modified Surendranath et al.’s figure 1 shows that the logic further is to determine a first value of the input voltage at a first time, at least in part based on the duty cycle of the clock. As to claim 3, the modified Surendranath et al.’s figure 1 shows that the logic further is to determine a second value of the input voltage at a second time, at least in part based on a remainder of the period of the clock (selecting the duty cycle or timing diagram to function as claimed is seen as an obvious design preference to ensure optimal performance, see MPEP 214.05). As to claim 4, the modified Surendranath et al.’s figure 1 shows that the difference is determined, at least in part based on a difference between the second value and the first value. As to claim 5, the modified Surendranath et al.’s figure 1 shows that the logic further is to produce the first signal, at least in part based on a determination that the magnitude of the difference in the input voltage exceeds the magnitude of the first predetermined threshold for a predetermined number of periods of the clock, and the predetermined number of periods is greater than 1 (the ADC generates signals based on clock signal). As to claim 6, the modified Surendranath et al.’s figure 1 shows that the first signal throttles a processor (160). As to claim 7, the modified Surendranath et al.’s figure 1 shows the processor (160), wherein the processor receives the input voltage and the first signal. As to claim 8. The modified Surendranath et al.’s figure 2 further shows a level comparator (260) to produce a second signal indicating whether the sampled voltage is less than a reference voltage. As to claim 9, the modified Surendranath et al.’s figure 2 shows that the logic produces the first signal, at least in part based on the second signal. As to claim 10, the modified Surendranath et al.’s figure 1 or 2 shows a sample-and-hold circuit (S1, R1 and C1) that samples the input voltage. As to claim 11, voltage divider to reduce a voltage level is well known in the art. It would have been obvious to one having ordinary skill in the art add voltage divider between 220 and 140 for the purpose of setting the detection threshold as desired. The apparatus of claim 1, further comprising: a voltage divider that receives a supply voltage and produces the input voltage, wherein the input voltage is at least in part based on the divided voltage. Claims 12-20 recite similar limitations of claims above. Therefore, they are rejected for the same reasons. As further regarding claims 17-20, computer readable medium to execute circuit operation is well known in the art. It would have been obvious to one having ordinary skill in the art to use a computer readable medium to execute the modified Surendranath et al.’s circuit for the purpose of providing more precise signals and save cost. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH-QUAN TRA whose telephone number is (571)272-1755. The examiner can normally be reached Mon-Fri from 8:00 A.M.-5:00 P.M. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /QUAN TRA/ Primary Examiner Art Unit 2842 Application/Control Number: 17/988,884 Page 2 Art Unit: 2842 Application/Control Number: 17/988,884 Page 3 Art Unit: 2842 Application/Control Number: 17/988,884 Page 4 Art Unit: 2842 Application/Control Number: 17/988,884 Page 5 Art Unit: 2842