DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 21-23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Khoury (US 5874944).
As to claim 21, Khoury’s figure 3 shows an apparatus, comprising: an input supply voltage node (Reference Voltage) ;a processor circuit (300 and 315) coupled to the input supply voltage node (via 137a) to receive an input supply voltage; a slope detection circuit (210, 230 and 320), coupled to the input supply voltage node to generate an input supply voltage slope value (at 325) based on a measured difference in the input supply voltage over a period of time; and a logic circuit (330 and 340) coupled to the slope detection circuit to generate a throttle signal (at 345) in response to the supply voltage slope value exceeding a predetermined threshold (max predetermined count x).
As to claim 22, figure 3 shows that the slope detection circuit includes first and second sample and hold circuits [(217 and 220) and (237 and 240)] coupled to first and second comparators (215 and 235) that each include inputs coupled to the input supply voltage node
As to claim 23, figure 3 shows that the first and second comparator inputs coupled to the input supply voltage node are coupled to the input supply voltage node through a resistor divider circuit (135a, 145a).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-16 and 21-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Khoury (US 5874944)
As to claim 1, Khoury’s figure 3 discloses an apparatus, comprising: a circuit (not shown that provides CLK1 or system clock, col 4, lines 29-30) to generate a clock (CLK_1) having a period with a duty cycle less than or equal to 90% (see figure 4. Furthermore, selecting the duty cycle for CLK_1 as claimed is seen as an obvious design preference to ensure optimal performance, see MPEP 2144.05); and logic (210 and 320 or further includes 330 and 340) to determine a difference in an input voltage (VIN of 210) between a first time (by 217 C1 based on CLK_1) and a second time (by 219 and C2 based on CLK_2) using the clock (col. 4, lines 29-30, teaches that “Clocks 1 and 2 may be derived from or the same as the system clock or timer clock 335) to produce a first signal (325 or 345), at least in part based on the difference in the input voltage (the comparator is for comparing the voltage difference between its inputs), a difference between the first and second times (the phases and pulse widths of the first and second clock signals determines voltages at the inputs of comparator 215), and a first predetermined threshold (generated by 230, 250 and/or 270 or the max predetermined count x).
As to claim 2, Khoury’s figure 3 shows that the logic further is to determine a first value of the input voltage at a first time, at least in part based on the duty cycle of the clock.
As to claim 3, Khoury’s figure 3 shows that the logic further is to determine a second value of the input voltage at a second time, at least in part based on a remainder of the period of the clock (selecting the duty cycle or timing diagram to function as claimed is seen as an obvious design preference to ensure optimal performance, see MPEP 214.05).
As to claim 5, Khoury’s figure 3 shows that the logic further is to produce the first signal (345), at least in part based on a determination that the magnitude of the difference in the input voltage exceeds the magnitude of the first predetermined threshold (the max predetermined count X) for a predetermined number of periods of the clock (timer clock, col. 5, lines 10-11, teaches that “the timer clock 335 may be derived from the system clock”), and the predetermined number of periods is greater than 1.
As to claim 6, Khoury’s figure 3 shows that the first signal throttles a processor (315, 300 and/or not shown circuit that receives the outputs of 305).
As to claim 7, Khoury’s figure 3 shows the processor (305), wherein the processor receives (via 137a) the input voltage and the first signal.
As to claim 8, Khoury’s figure 3 shows a level comparator (270) to produce a second signal (284) indicating whether a sampled voltage (generated by 277 and 280) is less than a reference voltage (generated by 279 and 282).
As to claim 9, Khoury’s figure 3 shows that the logic produces the first signal, at least in part based on the second signal.
As to claim 10, Khoury’s figure 3 shows a sample-and-hold circuit (217, 220 and 219,222) that samples the input voltage.
As to claim 11, Khoury’s figure 3 shows a voltage divider (135a) that receives a supply voltage (Reference voltage) and produces the input voltage, wherein the input voltage is at least in part based on the divided voltage.
Claims 12-16 and 21-23 recite similar limitations of claims above. Therefore, they are rejected for the same reasons.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH-QUAN TRA whose telephone number is (571)272-1755. The examiner can normally be reached Mon-Fri from 8:00 A.M.-5:00 P.M.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on 571-272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/QUAN TRA/
Primary Examiner
Art Unit 2843
Prosecution Insights