DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Son (US 2021/0183862) in view of Choi (US 2013/0292847) and further in view of Kwon (US 2016/0181143).
[claim 1] Son discloses a semiconductor device (fig. 2, 7, 8a), comprising: a plurality of conductive lines (BL, fig. 2, [0047]) vertically oriented over a substrate (SUB, fig. 2); and a plurality of vertical isolation layers (V1P1 and EP of VIP as well as SPC, fig. 7, 8a [0063]) disposed between the conductive lines, the vertical isolation layers each including an first insulation gap (EP, fig. 7) extending vertically, an active layer (SP,SPC, fig. 2) oriented laterally from the conductive lines, a lateral conductive line (GE, fig. 2, 8a) which is oriented laterally in a direction crossing the active layer, wherein each of the vertical isolation layers further includes: a second insulation gap (spacer SPC, fig. 8a, [0078]) formed in the active layer between the conductive lines and the lateral conductive line. Son, however, does not expressly disclose that that the EP first insulation gap between the bit conductive lines and spacer SPC second insulation gap are air gaps.
Choi discloses a semiconductor device (fig. 1B) where the insulation layers (170, fig. 1B, [0087][0093]) between the bit conductive lines (135, fig. 1B, [0106]) comprises an air gap for the insulation gap (AG, fig. 1B, [0106]).
It would have been obvious to one of ordinary skill in the art before the time of filing to have made the EP first insulation gap an air gap since using air as insulator has less parasitic capacitance since air has very low dielectric constant and using air as an insulator is well known to allow for better scaling since forming air gaps with high aspect ratios is easier.
Kwon discloses a semiconductor device (fig. 2a) where the gate spacer insulation layers (231, fig. 2a, [0033]) on the sidewall of the gate comprises an air gap for the insulation gap [0033] with a capping layer (232, fig. 2a, [0033]) thereon for protection
It would have been obvious to one of ordinary skill in the art before the time of filing to have made the spacer SPC first insulation gap an air gap with a capping layer for protection thereon since using air as insulator has less parasitic capacitance since air has very low dielectric constant and using air as an insulator is well known to allow for better scaling since forming air gaps with high aspect ratios is easier.
With this modification Son discloses:
[claim 2] The semiconductor device of claim 1, wherein each of the vertical isolation layers further includes: a gap-fill layer (VIP1, fig. 7), and wherein the first air gap (ES upon modification, fig. 7) is disposed between the gap-fill layer and the conductive lines (BL, fig. 7).
[claim 3] The semiconductor device of claim 2, wherein the gap-fill layer includes silicon oxide [0063].
[claim 4] The semiconductor device of claim 1, wherein the conductive lines extend vertically in a direction parallel to the first air gap (D3, fig. 2, 7).
[claim 5] The semiconductor device of claim 1, further comprising: a data storage element including a storage node (DS, fig. 2, [0040]) which is coupled to a semiconductor layer (SD1, fig. 2).
[claim 14] The semiconductor device of claim 1, further comprising: a bit line-side capping layer (SPC, fig. 2) disposed between the conductive line and the lateral conductive line, wherein the second air gap is formed in the bit line-side capping layer (note that in Kwon air spacer 231comprises a capping layer 232, fig. 2a thereon).
Claim(s) 7-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Son (US 2021/0183862) in view of Choi (US 2013/0292847) and further in view of Kwon (US 2016/0181143).
[claim 7] Son discloses a semiconductor device (fig. 2,3, 7, 8a), comprising: active layers (SP, fig. 2, [0038]) vertically stacked over a substrate (SUB, fig. 2); word lines (GE(WL), fig. 2,3 [0041]) extending in a direction crossing the active layers over the active layers; a bit line (BL, fig. 2,3) commonly coupled to first sides of the active layers and extending in a direction perpendicular to the substrate (fig. 2,3); storage nodes of a data storage element (DS, fig. 2,3, [0040]) that are vertically stacked over the substrate while being coupled to second sides of the active layers, respectively; and vertical isolation layers (V1P1 and EP of VIP, fig. 7 and SPC of fig 8a, [0063]) including first insulation gaps (EP, fig. 7) disposed between the bit lines and second insulation gaps (spacer SPC, fig. 8a, [0078]) formed in the active layer between the bit line and the word lines. Son, however, does not expressly disclose that that the EP first insulation gap between the bit lines and spacer SPC second insulation gap are air gaps.
Choi discloses a semiconductor device (fig. 1B) where the insulation layers (170, fig. 1B, [0087][0093]) between the bit conductive lines (135, fig. 1B, [0106]) comprises an air gap for the insulation gap (AG, fig. 1B, [0106]).
It would have been obvious to one of ordinary skill in the art before the time of filing to have made the EP insulation gap an air gap since using air as insulator has less parasitic capacitance since air has very low dielectric constant and using air as an insulator is well known to allow for better scaling since forming air gaps with high aspect ratios is easier.
Kwon discloses a semiconductor device (fig. 2a) where the gate spacer insulation layers (231, fig. 2a, [0033]) on the sidewall of the gate comprises an air gap for the insulation gap [0033]
It would have been obvious to one of ordinary skill in the art before the time of filing to have made the spacer SPC first insulation gap an air gap since using air as insulator has less parasitic capacitance since air has very low dielectric constant and using air as an insulator is well known to allow for better scaling since forming air gaps with high aspect ratios is easier.
With this modification Son discloses:
[claim 8] The semiconductor device of claim 7, wherein each of the vertical isolation layers further includes: a gap-fill layer (VIP1, fig. 7), and the first air gaps (ES upon modification, fig. 7) which are disposed between the gap-fill layer and the bit lines.
[claim 9] The semiconductor device of claim 8, wherein the gap-fill layer includes silicon oxide [0063].
[claim 10] The semiconductor device of claim 7, wherein the bit lines extend vertically in a direction parallel to the air gaps (fig. 2,3, 7).
[claim 11] The semiconductor device of claim 7, wherein the word line includes double word lines that are facing each other with the active layer interposed therebetween (e.g. the memory structure of fig. 3 has gate electrodes/word lines above and below the channel).
[claim 12] The semiconductor device of claim 7, wherein the storage nodes of the data storage element include a cylindrical storage node [0073].
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Son (US 2021/0183862) in view of Choi (US 2013/0292847) and further in view of Kwon (US 2016/0181143).
Son/Choi disclose the semiconductor device of claim 7 above but do not expressly disclose each of the active layers has a rhombus shape including a channel protrusion.
Nevertheless it would have been obvious to have made each of the active layers have a rhombus shape including a channel protrusion, since it has been held that a particular shape configuration (rhombus shape with a channel protrusion) was a matter of choice which a person of ordinary skill in the art before the time of filing would have found obvious absent evidence that the particular configuration was critical. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Response to Arguments
Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any interpretation applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/AMAR MOVVA/Primary Examiner, Art Unit 2898