Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier.
Claim
Means Plus Function Limitation
Corresponding Structure
30
means for transferring a first set of resultant values from a first set of accumulators to a memory, wherein the first set of resultant values were generated from a first set of multiply-accumulate (MAC) operations
[A] controller configured to concurrently: cause a first set of resultant values in the first set of accumulators to be transferred to the memory pursuant to a first set of store instructions, wherein the first set of resultant values was generated pursuant to a first set of multiply-accumulate (MAC) operations performed by the set of multipliers and the first set of accumulators; and cause the set of multipliers and the second set of accumulators to perform a second set of MAC operations. (claim 1)
30
means for performing a second set of MAC operations using a second set of accumulators concurrently with the transferring of the first set of resultant values from the first set of accumulators to the memory.
[A] controller configured to concurrently: cause a first set of resultant values in the first set of accumulators to be transferred to the memory pursuant to a first set of store instructions, wherein the first set of resultant values was generated pursuant to a first set of multiply-accumulate (MAC) operations performed by the set of multipliers and the first set of accumulators; and cause the set of multipliers and the second set of accumulators to perform a second set of MAC operations. (claim 1)
Because this claim limitation(s) is being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it is being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 2, 9, 19, and 28 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Regarding claim 2, it is an improper dependent form because it fails to further limit the subject matter of the claim 1. Claim 2 states "The apparatus of claim 1, wherein the first set of MAC operations precede the second set of MAC operations." This is already a limitation in claim 1 because in claim 1 it states a controller " configured to concurrently: cause a first set of resultant values in the first set of accumulators to be transferred to the memory pursuant to a first set of store instructions, wherein the first set of resultant values was generated pursuant to a first set of multiply-accumulate (MAC) operations performed by the set of multipliers and the first set of accumulators; and cause the set of multipliers and the second set of accumulators to perform a second set of MAC operations." Therefore, claim 2 doesn't constitute a further limitation on claim 1.
Regarding claim 9, it is of improper dependent form because it fails to further limit the subject matter of claim 1. By the plain meaning of MAC operations, MAC operations would generate a resultant value. Therefore, the second set of MAC operations in claim 1 already has the limitation of generating a second set of resultant values and claim 9 doesn’t specify a further limitation on claim 1.
Regarding claim 19, it is of improper dependent form because it fails to further limit the subject matter of claim 18. Claim 18 is a dependent claim of claim 9, which states the second set of resultant values are generated from the second set of MAC operations. It can be determined that since the second set of MAC operations precedes the second set of resultant values being transferred to memory, and the second set of resultant value being transferred to memory happens concurrently with the third set of MAC operations, that the second set of MAC operations precedes the third set of MAC operations. Therefore claim 19 doesn’t specify a further limitation on claim 18
Regarding claim 28, it is of improper dependent form for failing to further limit the subject matter of claim 26. By the ordinary definition of a MAC operation, MAC operations generate a resultant value. Therefore, claim 26 already has the limitation of the second set of MAC operations generating a second set of resultant values from a second set of accumulators, and claim 28 doesn't specify a further limitation on claim 26.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2, 9, 10, 18, 19, 26, 28, and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Hanzawa et al. (US 20230333816 A1), in view of Dally et al. (US 20210089864 A1) and Baptista et al. (NPL – “Raising the Abstraction Level of a Deep Learning Design on FPGAs”).
Regarding claim 1, Hanzawa teaches an apparatus, comprising:
a memory (Figure 3; element 19); a matrix multiplier engine (Figure 3; element 17) coupled to the memory, comprising: an array of multiplier-accumulate units (MAUs) (Figure 3; element 20) comprising: a set of multipliers (Figure 3; MAC 20); a first set of accumulators (Figure 3; MAC 20); and a controller (Figure 3; element 18) coupled to the matrix multiplier engine and the memory,
Hanzawa also teaches a first set of resultant values in the first set of accumulators in MAC 20 to be transferred to memory 19 pursuant to a first set of store instructions (Figure 3; MAC 20 and memory 19; ¶ [00131]).
However, since Hanzawa doesn’t teach each MAU having a double-buffered accumulator unit, Hanzawa doesn’t teach:
the controller configured to concurrently: cause a first set of resultant values in the first set of accumulators to be transferred to the memory pursuant to a first set of store instructions, wherein the first set of resultant values was generated pursuant to a first set of multiply-accumulate (MAC) operations performed by the set of multipliers and the first set of accumulators; and cause the set of multipliers and the second set of accumulators to perform a second set of MAC operations.
However, since Dally teaches each MAU containing a double-buffered accumulator unit (Figure 3A; element 340; paragraph [0083]),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the single accumulator system of Hanzawa’s to use double-buffered accumulator units as taught by Dally. This modification would have been obvious because it would help increase overall throughput and help prevent bottlenecks (see Baptista Fig. 4; Raising the Abstraction Level of a Deep Learning Design on FPGAs). Hanzawa in view of Dally therefore teaches a system including [a] controller configured to concurrently: cause a first set of resultant values in the first set of accumulators to be transferred to the memory pursuant to a first set of store instructions, wherein the first set of resultant values was generated pursuant to a first set of multiply-accumulate (MAC) operations performed by the set of multipliers and the first set of accumulators; and cause the set of multipliers and the second set of accumulators to perform a second set of MAC operations.
Regarding claim 2, it depends on and does not further limit claim 1. See rejection under 35 U.S.C. 112(d) above. Therefore, it is rejected for the same reasons as claim 1. Alternatively, Dally teaches the first set of MAC operations [preceding] the second set of MAC operations (Figure 3A; element 340; ¶ [0083]).
Regarding claim 9, it depends on and does not further limit claim 1. See rejection under 35 U.S.C. 112(d) above. Therefore, it is rejected for the same reasons as claim 1. Alternatively, Dally teaches a second set of MAC operations [generating] a second set of resultant values held in [a] second set of accumulators (Figure 3A; element 340; paragraph [0083]).
Regarding claim 10, Dally teaches the second set of resultant values [being] generated prior to the first set of resultant values being completely transferred to the memory (Figure 3A; element 340; paragraph [0083])
Regarding claim 18, since the double-buffered accumulator units taught by Dally (Figure 3A; element 340; paragraph [0083]) would allow for a third set of MAC operations to be performed in the first set of accumulators, the combination of Hanzawa in view of Dally and Baptista teaches the apparatus of claim 9:
wherein the controller (Hanzawa; figure 3; element 18) configured to concurrently: cause the second set of resultant values to be transferred to the memory pursuant to a second set of store instructions; and cause the set of multipliers and the first set of accumulators to perform a third set of MAC operations.
Regarding claim 19, it depends on and does not further limit claim 18. See rejection under 35 U.S.C. 112(d) above. Therefore, it is rejected for the same reasons as claim 18. Alternatively, Dally teaches the second set of MAC operations [preceding] the third set of MAC operations (Figure 3A; element 340; ¶ [0083]).
Regarding claims 26, it is a method claim corresponding to apparatus claim 1. It is rejected for the same reasons.
Regarding claim 28, it is a method claim corresponding to apparatus claim 9. It is rejected for the same reasons. Alternatively, it depends on and does not further limit claim 26. See rejection under 35 U.S.C. 112(d) above. Therefore, it is also rejected for the same reasons as claim 26.
Regarding claim 30, it is a means plus function claim corresponding to apparatus claim 1. See claim interpretation under 35 U.S.C. 112(f) above. It is rejected for the same reasons.
Claims 3, 4, 6-8, 20-24, and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Hanzawa in view of Dally and Baptista as applied to claim 1 above, and further in view of Nobile et al. (WO 2018228703 A1).
Regarding claim 3, the combination of Hanzawa in view of Dally and Baptista teaches the invention substantially as claimed. See the rejection of claim 1 above. Dally teaches that the double-buffered accumulator units are cleared before new values are written into them (Figure 3A; element 340; ¶ [0095]) but does not teach a mechanism for accomplishing this result. The combination of Hanzawa in view of Dally and Baptista therefore does not teach a system wherein the controller selects a second set of accumulators for the second set of MAC operations in response to a demarcation instruction.
However, Nobile teaches a demarcation instruction (pg. 11; lines 25-26).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Hanzawa in view of Dally and Baptista to use demarcation instruction to zero the first set of accumulators as taught by Nobile and configure the controller in the combination of Hanzawa in view of Dally and Baptista to respond to the demarcation instruction by [selecting] the second set of accumulators for the second set of MAC operations. It would’ve been obvious because the demarcation instruction provides a speedup (pg. 11; lines 27-28).
Regarding claim 4, Nobile teaches the demarcation instruction [comprising] an instruction to zero the first set of accumulators (Nobile; pg. 11; lines 25-26).
Regarding claim 6, Dally in view of Nobile teaches the demarcation instruction [indicating] that the second set of MAC operations is independent of the first set of MAC operations (Dally; figure 3A; element 340; ¶ [0095]) (Nobile; pg. 11; lines 25-26).
Regarding claim 7, Hanzawa in view of Dally and Baptista teaches the apparatus of claim 3:
wherein [a] controller (Hanzawa, figure 3; element 18) [being] configured to: cause the set of multipliers and the first set of accumulators to perform the first set of MAC operations; and cause the set of multipliers and the second set of accumulators to perform the second set of MAC operations (Dally; figure 3A; element 340; ¶ [0083]).
However, since it doesn’t teach MAC instructions or the demarcation instruction [being] sequentially situated between the first set of store instructions and the second set of MAC instructions, it doesn’t teach:
the controller [being] configured to: cause the set of multipliers and the first set of accumulators to perform the first set of MAC operations in response to a first set of MAC instructions; and cause the set of multipliers and the second set of accumulators to perform the second set of MAC operations in response to a second set of MAC instructions, wherein the demarcation instruction is sequentially situated between the first set of store instructions and the second set of MAC instructions
However, Nobile teaches a store instruction, a demarcation instruction, and a MAC instruction, with the demarcation instruction situated between the store and MAC instruction (page 12, lines 5 and 20; page 13, lines 1,2, and 8). Therefore, Hanzawa in view of Dally, Baptista, and Nobile teaches the apparatus of claim 3:
wherein the controller is configured to: cause the set of multipliers and the first set of accumulators to perform the first set of MAC operations in response to a first set of MAC instructions; and cause the set of multipliers and the second set of accumulators to perform the second set of MAC operations in response to a second set of MAC instructions, wherein the demarcation instruction is sequentially situated between the first set of store instructions and the second set of MAC instructions
Regarding claim 8, the combination of Hanzawa in view of Dally, and Baptista teaches the apparatus of claim 7:
wherein the controller (Hanzawa; figure 3; element 18) is configured to look ahead to cause the concurrent transfer of the first set of resultant values to the memory and the second set of MAC operations (Dally; figure 3A; element 340; ¶ [0083])
Nobile teaches the demarcation instruction (pg. 11; lines 25-26)
Therefore the combination of Hanzawa in view of Dally, Baptista, and Nobile teaches the apparatus of claim 7:
wherein the controller is configured to look ahead for the demarcation instruction to cause the concurrent transfer of the first set of resultant values to the memory and the second set of MAC operations.
Regarding claim 20, the combination of Hanzawa in view of Dally, Baptista, and Nobile teaches the apparatus of claim 18:
wherein the controller (Hanzawa; figure 3; element 18) is configured to select the first set of accumulators for the third set of MAC operations (Dally; figure 3A; element 340; ¶ [0095]) in response to a demarcation instruction (Nobile; pg. 11; lines 25-26);
Regarding claim 21, the combination of Hanzawa in view of Dally, Baptista, and Nobile teaches the apparatus of claim 20:
wherein the demarcation instruction comprises an instruction to zero the second set of accumulators (Nobile; pg. 11; lines 25-26).
Regarding claim 22, the combination of Hanzawa in view of Dally, Baptista, and Nobile teaches the demarcation instruction [indicating] that the third set of MAC operations is independent of the second set of MAC (Dally; figure 3A; element 340; ¶ [0095]).
Regarding claim 23, Hanzawa in view of Dally and Baptista teaches the apparatus of claim 20:
Wherein [a] controller (Hanzawa; figure 3; element 18) is configured to: cause the set of multipliers and the first set of accumulators to perform the third set of MAC operations; and cause the set of multipliers and the second set of accumulators to perform the second set of MAC operations (Dally; figure 3A; element 340; ¶ [0083]).
However, since it doesn’t teach MAC instructions or the demarcation instruction [being] sequentially situated between the first set of store instructions and the second set of MAC instructions, it doesn’t teach:
the controller [being] configured to: cause the set of multipliers and the first set of accumulators to perform the first set of MAC operations in response to a first set of MAC instructions; and cause the set of multipliers and the second set of accumulators to perform the second set of MAC operations in response to a third set of MAC instructions, wherein the demarcation instruction is sequentially situated between the first set of store instructions and the second set of MAC instructions.
However, Nobile teaches a store instruction, a demarcation instruction, and a MAC instruction, with the demarcation instruction situated between the store and MAC instruction (page 12, lines 5 and 20; page 13, lines 1,2, and 8). Therefore, the combination of Hanzawa in view of Dally, Baptista, and Nobile teaches the apparatus of claim 20:
wherein the controller (Hanzawa; figure 3; element 18) is configured to: cause the set of multipliers and the first set of accumulators to perform the first set of MAC operations in response to a first set of MAC instructions; and cause the set of multipliers and the second set of accumulators to perform the second set of MAC operations in response to a second set of MAC instructions, wherein the demarcation instruction is sequentially situated between the first set of store instructions and the second set of MAC instructions.
Regarding claim 24, the combination of Hanzawa in view of Dally and Baptista teaches the apparatus of claim 23:
wherein the controller (Hanzawa; figure 3; element 18) is configured to look ahead to cause the concurrent transfer of the second set of resultant values to the memory and the third set of MAC operations (Dally; figure 3A; element 340; ¶ [0083])
However, the combination of Hanzawa in view of Dally and Baptista doesn’t teach the controller looking ahead for a demarcation instruction. Nobile teaches the demarcation instruction (pg. 11; lines 25-26).
Therefore the combination of Hanzawa in view of Dally, Baptista, and Nobile teaches the apparatus of claim 23:
wherein the controller (Hanzawa; figure 3; element 18) is configured to look ahead for the demarcation instruction to cause the concurrent transfer of the second set of resultant values to the memory and the third set of MAC operations.
Regarding claim 27, it is a method claim corresponding to apparatus claim 6. It is rejected for the same reasons.
Claims 5 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Hanzawa in view of Dally, Baptista, and Nobile as applied to claim 3 above, and further in view of Srinivasa et al. (US 20220101091 A1) and Adsantec (NPL – “A Quick Refresher on Demultiplexers for Design Engineers”).
Regarding claim 5, the combination of Hanzawa in view of Dally, Baptista, and Nobile teaches the invention substantially as claimed. See the rejection of claim 3 above. The combination of Hanzawa in view of Dally, Baptista, and Nobile teaches the apparatus of claim 3:
wherein the array of MAUs [comprising a] set of multipliers, a first set of outputs coupled to the first set of accumulators, and a second set of outputs coupled to the second set of accumulators (Dally; figure 3A; element 340; ¶ [0083]).
However, the combination of Hanzawa in view of Dally, Baptista, and Nobile doesn’t teach the use of a demultiplexer or the controller sending control signals to the demultiplexer. Therefore, it doesn’t teach the apparatus of claim 3:
wherein the array of MAUs comprise a set of demultiplexers including a first set of inputs coupled to the set of multipliers, a first set of outputs coupled to the first set of accumulators, and a second set of outputs coupled to the second set of accumulators, wherein the controller is configured to select the second set of accumulators by sending a control signal to a set of select inputs of the set of demultiplexers, respectively
Srinivasa teaches a demultiplexer between three multipliers and three accumulators (figure 3; element 320). Therefore, Srinivasa teaches the apparatus of claim 3:
wherein the array of MAUs comprise a set of demultiplexers including a first set of inputs coupled to the set of multipliers, a first set of outputs coupled to the first set of accumulators, and a second set of outputs coupled to the second set of accumulators.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Hanzawa in view of Dally, Baptista, and Nobile to use a set of demultiplexer that is capable of being coupled to the output lines of multipliers and the input lines of accumulators as taught by Srinivasa. Although Srinivasa illustrates a demultiplexer coupled to three accumulators, it would also be capable of being coupled to two accumulators. It would’ve been obvious because demultiplexers are commonplace in digital electronics and are used in almost all applications that concern data distribution (Adsantec; lines 1 and 2).
Since Srinivasa doesn’t teach sending a control signal to a set of select inputs of [a] set of demultiplexers, Srinivasa doesn’t teach the apparatus of claim 3:
wherein the array of MAUs comprise a set of demultiplexers including a first set of inputs coupled to the set of multipliers, a first set of outputs coupled to the first set of accumulators, and a second set of outputs coupled to the second set of accumulators, wherein the controller is configured to select the second set of accumulators by sending a control signal to a set of select inputs of the set of demultiplexers, respectively.
However, Adsantec teaches that every demultiplexer has selector lines that are fed with different combination of inputs (i.e. control signals) to yield different routing responses at the output (§ Overview of Demultiplexers; lines 10-11). Therefore, the combination of Hanzawa, Dally, Baptista, Nobile, Srinivasa, and Adsantec teaches the apparatus of claim 3:
wherein the array of MAUs comprise a set of demultiplexers including a first set of inputs coupled to the set of multipliers, a first set of outputs coupled to the first set of accumulators, and a second set of outputs coupled to the second set of accumulators, wherein the controller is configured to select the second set of accumulators by sending a control signal to a set of select inputs of the set of demultiplexers, respectively.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Hanzawa in view of Dally, Baptista, Nobile, and Srinivasa to use control signals to a set of select inputs to the set of demultiplexers as taught by Adsantec. It would’ve been obvious because control signals ensures the demultiplexer sends data to the desired destination (§ Overview of Demultiplexers; lines 12-13).
Regarding claim 25, the demultiplexer taught by Srinivasa in view of Adsantec is capable of being coupled to one multiplier and two accumulators for each MAU (Srinivasa; figure 3; element 320) and have control signals send to the set of select inputs of the set of demultiplexers (Adsantec; § Overview of Demultiplexers, lines 10-11). Therefore, the combination of Hanzawa in view of Dally, Baptista, Nobile, Srinivasa, and Adsantec teaches the apparatus of claim 18:
wherein the array of MAUs (Hanzawa; figure 3; element 17) comprise a set of demultiplexers including a first set of inputs coupled to the set of multipliers, a first set of outputs coupled to the first set of accumulators, and a second set of outputs coupled to the second set of accumulators (Dally; figure 3A; element 340; ¶ [0083]), wherein the controller (Hanzawa; figure 3; element 18) is configured to select the first set of accumulators by sending a control signal to a set of select inputs of the set of demultiplexers, respectively.
Claims 11, 17, and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Hanzawa in view of Dally, and Baptista as applied to claim 9 above, and further in view of Mei et al. (US 20230153176 A1).
Regarding claim 11, since the combination of Hanzawa in view of Dally, and Baptista doesn’t teach triple-buffered multiply-accumulate units, it doesn’t teach the apparatus of claim 10:
wherein the array of MAUs further comprise a third set of accumulators, wherein the controller is configured to concurrently: continue the first set of resultant values to be transferred to the memory; and cause the set of multipliers and the third set of accumulators to perform a third set of MAC operations
However, Mei teaches triple-buffering with regards to producer and consumer threads (¶ 407), which can be applied to MAUs. Therefore, the combination of Hanzawa in view of Dally, Baptista, Nobile, and Mei teaches the apparatus of claim 10:
wherein the array of MAUs further comprise a third set of accumulators, wherein the controller is configured to concurrently: continue the first set of resultant values to be transferred to the memory; and cause the set of multipliers and the third set of accumulators to perform a third set of MAC operations
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Hanzawa in view of Dally, Baptista, and Nobile to use the triple-buffering of producer and consumer threads to allow the combination of Hanzawa in view of Dally, Baptista, and Nobile to have a third set of accumulators perform a third set of MAC operations. It would’ve been obvious because you could continue multiply-accumulate operations without conflicts (¶ 407).
Regarding claim 17, the use of a triple-buffered system as taught by Mei (¶ 407) allows for the continuation of the process in claim 11 (see 35 U.S.C. 103 rejection for claim 11 above). Therefore, the combination of Hanzawa in view of Dally, Baptista, Nobile, and Mei teaches the apparatus of claim 11:
wherein the controller (Hanzawa; figure 3; element 18) is configured to concurrently: continue to cause the set of multipliers and the third set of accumulators to perform the third set of MAC operations; and cause the second set of resultant values to be transferred to the memory.
Regarding claim 29, it is a method claim corresponding to apparatus claim 11. It is rejected for the same reasons.
Claims 12, 13, 15, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Hanzawa in view of Dally, Baptista, and Mei as applied to claim 11 above, and further in view of Nobile.
Regarding claim 12, Mei teaches triple buffering, allowing for the use of a third set of accumulators. Nobile teaches the demarcation instruction (pg. 11; lines 25-26), which can be responded to be the controller, similar to how Nobile teaches the demarcation instruction claim 3 (see 35 U.S.C. 103 rejection of claim 3 above). Therefore, the combination of Hanzawa in view of Dally, Baptista, Mei, and Nobile teaches the apparatus of claim 11:
wherein the controller (Hanzawa; figure 3; element 18) is configured to select the third set of accumulators for the third set of MAC operations in response to a demarcation instruction.
Regarding claim 13, the demarcation instruction taught by Nobile (pg. 11; lines 25-26) can be used to zero the second set of accumulators, similar to the one used to zero the first set of accumulators in claim 4 (see 35 U.S.C. 103 rejection of claim 4 above).
Regarding claim 15, the demarcation instruction taught by Nobile can functionally be used to indicate that the third set of MAC operations is independent of the second set of MAC operations, similar to how it is functionally used to indicate that the second set of MAC operations is independent of the first set of MAC operations in claim 6 (see 35 U.S.C. 103 rejection of claim 6 above).
Regarding claim 16, Mei teaches triple buffering (¶ 407), allowing for the use of three accumulators. In addition, the combination of Dally in view Nobile and Mei further teaches the demarcation instruction [being] sequentially situated between a second set of store instructions and the third set of MAC instructions (Dally; figure 3A; element 340; ¶ [0095]) (Nobile; pg. 11; lines 25-26) (Mei; ¶ 407).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Hanzawa in view of Dally, Baptista, Mei, and Nobile as applied to claim 12 above, and further in view of Shrinivasa and Adsantec.
Regarding claim 14, the demultiplexer taught by Srinivasa is capable of being coupled to one multiplier and three accumulators for each MAU (figure 3; element 320). In addition, Mei teaches triple buffering (Mei; ¶ 407), which would allow three accumulators in a MAU to be in use concurrently. Therefore the combination of Hanzawa in view of Dally, Baptista, Mei, and Nobile, Shrinivasa, and Adsantec teaches the apparatus of claim 12:
wherein the array of MAUs (Hanzawa; figure 3; element 17) comprise a set of demultiplexers including a first set of inputs coupled to the set of multipliers, a first set of outputs coupled to the first set of accumulators, a second set of outputs coupled to the second set of accumulators, and a third set of outputs coupled to the third set of accumulators, wherein the controller is configured to select the third set of accumulators by sending a control signal (Adsantec; § Overview of Demultiplexers, lines 10-11) to a set of select inputs of the set of demultiplexers, respectively.
Conclusion
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/DAVID J LIU/Examiner, Art Unit 2182
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
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