FINAL REJECTION
This Office action is responsive to the amendment filed December 8, 2025 (“Amendment”).
The instant 17/989,587 application is a reissue application of U.S. Pat. 10,841,243 B2 to Levi et al. (“the ‘243 Patent”), which issued November 17, 2020 from U.S. Pat. App. Ser. No. 16/012,826, filed June 20, 2018, with a domestic priority claim to U.S. Provisional Pat. App. Ser. No. 62,582,997 filed November 8, 2017.
The Examiner has deemed the ‘243 Patent to have an earliest possible effective filing date of November 8, 2017.
Claims 1-22 were originally pending in this application. By way of a preliminary amendment filed with the application, claims 23-46 are added. Thus claims 1-46 are pending.
This action is Final.
Reissue
The Examiner has determined that there are no other continuations, reissues, reexaminations, inter partes reviews, or other AIA trials or appeals currently pending with respect to the ‘243 Patent. A litigation search has determined there to be no pending litigation as to the ‘288 Patent.
Applicant is reminded of the continuing obligation under 37 CFR 1.178(b) to timely apprise the Office of any prior or concurrent proceeding in which Patent No. 10,841,243 is or was involved. These proceedings would include interferences, reissues, reexaminations, and litigation. Applicant is further reminded of the continuing obligation under 37 CFR 1.56, to timely apprise the Office of any information which is material to patentability of the claims under consideration in this reissue application. These obligations rest with each individual associated with the filing and prosecution of this application for reissue. See also MPEP §§ 1404, 1442.01 and 1442.04.
Because the instant ‘243 Patent is deemed not to contain claims having an effective date prior to March 16, 2013, the America Invents Act First Inventor to File (“AIA -FITF”) provisions apply, rather than the pre-AIA provisions. See 35 U.S.C. § 100 (note) and 35 U.S.C. § 100 (pre-AIA ). In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of any statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Reissue Amendment
The Amendment filed December 8, 2025 is objected to because of the following:
New claims 23-46 are added but are not underlined in their entirety, which does not meet 37 CFR 1.173(b)(2) and (d)(2).
Claims 10, 13, and 21 are amended using strikethrough and double bracketing to remove matter, rather than single bracketing. 37 CFR 1.173(d)(1).
Further, the amendment to the specification does not amend the first sentence of the specification to state that more than one reissue application has been filed and identify each of the reissue applications by relationship, application number and filing date as per 37 CFR 1.177. The amendment includes this information but not in the first sentence of the disclosure.
A supplemental paper correctly amending the reissue application is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when § 112(f) is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under § 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with § 112(f). The presumption that the claim limitation is interpreted under § 112(f), is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with § 112(f). The presumption that the claim limitation is not interpreted under § 112(f), is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under § 112(f), except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under § 112(f), except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under § 112(f), because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
In claims 10, 21, 35, and 44 “[a] network interface controller … configured for/to: receiving a packet”;
In claims 10 and 21, “[a] network interface controller … configured for: determining that at least a portion of the stages of the pipeline are acceleration-defined stages”;
In claims 10 and 21, “[a] network interface controller … configured for: processing the packet in the pipeline, wherein processing the packet comprises: transmitting data to the accelerator from the acceleration-defined stages; causing performance of respective acceleration tasks on the transmitted data in the accelerator; receiving processed data from the accelerator to receiving stages of the pipeline”;
In claims 10 and 21, “[a] network interface controller … configured for: after processing the packet in the pipeline routing the packet toward a destination”, and in claim 35, “[a] network interface controller … configured to: route the packet toward a destination after processing the packet in the packet processing pipeline”;
In claims 10 and 21, “[a] network interface controller … configured for: responsively to the status returning the processed data to the accelerator to perform another acceleration task”, and in claims 35 and 44, “based on the status, receiving the processed data from the electrical circuitry and performing a subsequent acceleration task in the configurable unit of the accelerator”;
In claims 35 and 44, “[a] network interface controller … configured to: process the packet in the packet processing pipeline by performing a task on data in at least one of the plurality of stages in the packet processing pipeline and transmitting data to the accelerator from the electrical circuitry, the transmitted data being associated with the at least one of the plurality of stages requiring acceleration”;
In claims 35 and 44, “an accelerator … configured to: perform an acceleration task on the transmitted data in the accelerator”;
In claims 35 and 44, “an accelerator … configured to: return processed data from the accelerator to the electrical circuitry, the processed data being associated with the at least one of the plurality of stages requiring acceleration”;
In claim 36, “an accelerator … configured to: perform the acceleration task in a configurable unit of the accelerator”;
In claim 36, “an accelerator … configured to: report a status of the acceleration task from the accelerator to the network interface controller and responsive to the status, perform another task on data in at least another one of the plurality of stages in the packet processing pipeline”;
In claim 39, “an accelerator … configured to determine responsively to the metadata whether to perform acceleration on the data”;
In all of these cases, the NIC, accelerator, and host processor are performing a function of a computing means. The NIC and host processor are stated as operating by way of software while the accelerator is preferred to be a FPGA but may also be a GPU. ‘243 Patent at 2:20, 2:52-54, 5:50-51, and 6:55-60.
Under the three-pronged approach above, it is thus determined by the Examiner that 1) the claims use a term used as a substitute for “means” for performing the claimed function; 2) the term is modified by the functional language; and 3) the term is not modified by sufficient structure for performing the claimed function.
Specifically as to prong 3) above, in this particular case the limitations recite “function without reciting sufficient structure for performing that function.” Williamson v. Citrix Online, LLC, 792 F.3d 1339, 1349 (Fed. Cir. 2015) (en banc) (quoting Watts v. XL Systems, Inc., 232 F.3d 877, 880 (Fed. Cir. 2000); see also Personalized Media Communications, LLC v. International Trade Commission, 161 F. 3d 696, 704 (Fed. Cir. 1998). Here the function is one that may be performed by a general-purpose processor and § 112(f) applies as further described below.
For a computer-implemented § 112(f) claim limitation, the specification must disclose an algorithm for performing the claimed specific computer function, or else the claim is indefinite. See Net MoneyIN, Inc. v. Verisign. Inc., 545 F.3d 1359, 1367 (Fed. Cir. 2008). See also In re Aoyama, 656 F.3d 1293, 1297, 99 USPQ2d 1936, 1939 (Fed. Cir. 2011) ("[W]hen the disclosed structure is a computer programmed to carry out an algorithm, ‘the disclosed structure is not the general purpose computer, but rather that special purpose computer programmed to perform the disclosed algorithm.’") (quoting WMS Gaming, Inc. v. Int’l Game Tech., 184 F.3d 1339, 1349, 51 USPQ2d 1385, 1391 (Fed. Cir. 1999)).
To claim a means for performing a specific computer-implemented function and then to disclose only a general purpose computer as the structure designed to perform that function amounts to pure functional claiming. In Aristocrat Techs. Australia PTY Ltd. v. Int’l Game Tech., 521 F.3d 1328, 1336-37, 86 USPQ2d 1235, 1242 (Fed. Cir. 2008). In this instance, the structure corresponding to a § 112(f) claim limitation for a computer-implemented function must include the algorithm needed to transform the general purpose computer or microprocessor disclosed in the specification. Aristocrat, 521 F.3d at 1333, 86 USPQ2d at 1239; Finisar Corp. v. DirecTV Group, Inc., 523 F.3d 1323, 1340, 86 USPQ2d 1609, 1623 (Fed. Cir. 2008); WMS Gaming, Inc. v. Int’l Game Tech., 184 F.3d 1339, 1349, 51 USPQ2d 1385, 1391 (Fed. Cir. 1999). The corresponding structure is not simply a general purpose computer by itself but the special purpose computer as programmed to perform the disclosed algorithm. Aristocrat, 521 F.3d at 1333, 86 USPQ2d at 1239. Thus, the specification must sufficiently disclose an algorithm to transform a general purpose microprocessor to the special purpose computer. See Aristocrat, 521 F.3d at 1338, 86 USPQ2d at 1241. ("Aristocrat was not required to produce a listing of source code or a highly detailed description of the algorithm to be used to achieve the claimed functions in order to satisfy § 112(f). It was required, however, to at least disclose the algorithm that transforms the general purpose microprocessor to a ‘special purpose computer programmed to perform the disclosed algorithm.’" (quoting WMS Gaming, 184 F.3d at 1349, 51 USPQ2d at 1391.)) An algorithm is defined, for example, as "a finite sequence of steps for solving a logical or mathematical problem or performing a task." Microsoft Computer Dictionary, Microsoft Press, 5th edition, 2002. Applicant may express the algorithm in any understandable terms including as a mathematical formula, in prose, in a flow chart, or "in any other manner that provides sufficient structure." Finisar, 523 F.3d at 1340, 86 USPQ2d at 1623; see also Intel Corp. v. VIA Techs., Inc., 319 F.3d 1357, 1366, 65 USPQ2d 1934, 1941 (Fed. Cir. 2003); In re Dossel, 115 F.3d 942, 946-47, 42 USPQ2d 1881, 1885 (Fed. Cir.1997); Typhoon Touch Inc. v. Dell Inc., 659 F.3d 1376, 1385, 100 USPQ2d 1690, 1697 (Fed. Cir. 2011); In re Aoyama, 656 F.3d at 1306, 99 USPQ2d at 1945.
Thus the Examiner looks to the disclosure to construe the claim limitations to cover the corresponding structure described therein and equivalents thereof.
As to element 1 above, looking to the specification, as noted above the NIC is stated as operating by way of software. The description of the claimed function of receiving a packet is disclosed in 10:10-13, which describes the NIC receiving a packet from a network or host at step 1 in FIGS 7-12. This is the algorithm that, along with the general processor, comprises the structure in the claim.
As to element 2 above, looking to the specification, the NIC is stated as operating by way of software. The description of the claimed function of determining that at least a portion of the stages of the pipeline are acceleration-defined stages is described in 10:10-13, which describes the NIC, after receiving a packet from a network or host at step 1 in FIGS 7-12, determining that the data requires acceleration. This is the algorithm that, along with the general processor, comprises the structure in the claim.
As to element 3 above, looking to the specification, as noted above the NIC is stated as operating by way of software. The description of the claimed function of processing the packet in the pipeline, wherein processing the packet comprises transmitting data to the accelerator from the acceleration-defined stages is described in 10:10-15, which describes the NIC transmitting the packets over interface 162 or 164 to the accelerator and receiving packets therefrom. This is the algorithm that, along with the general processor, comprises the structure in the claim.
As to element 4 above, looking to the specification, as noted above the NIC is stated as operating by way of software. The description of the claimed function of, after processing the packet in the pipeline, routing the packet toward a destination is described in 10:22-24, which describes the NIC, after receiving a packet from a network or host at step 1 and processing such including forwarding it to and receiving it from the accelerator in FIGS 7-12, forwarding the packet to the network. This is the algorithm that, along with the general processor, comprises the structure in the claim.
As to element 5 above, looking to the specification, the NIC is stated as operating by way of software. The description of the claimed function of responsively to the status returning the processed data to the accelerator to perform another acceleration task is described in 11:6-9 and FIGS 9 and 10, which describes the NIC determining in step 5 that further acceleration is needed. This is the algorithm that, along with the general processor, comprises the structure in the claim.
As to element 6 above, looking to the specification, as noted above the NIC is stated as operating by way of software. The description of the claimed function of processing the packet in the packet processing pipeline by performing a task on data in at least one of the plurality of stages in the packet processing pipeline and transmitting data to the accelerator from the electrical circuitry, the transmitted data being associated with the at least one of the plurality of stages requiring acceleration is disclosed in 7:52-54 and 8:57-61 and 67-9:2 which describes a NIC which performs a processing step 120 upon receiving it and then transmits the packet to the accelerator, being associated with a stage requiring acceleration. This is the algorithm that, along with the general processor, comprises the structure in the claim.
As to element 7 above, looking to the specification, as noted above the accelerator is preferred to be a FPGA but may also be a GPU. The description of the claimed function of performing an acceleration task in the accelerator is described in 9:17-20, which describes the accelerator performing the specified acceleration task from the NIC. This is the algorithm that, along with the general processor, comprises the structure in the claim.
As to element 8 above, looking to the specification, as noted above the accelerator is preferred to be a FPGA but may also be a GPU. The description of the claimed function of the accelerator returning processed data from the accelerator to the electrical circuitry is described in 9:19-20, which describes the data being returned to the NIC. This is the algorithm that, along with the general processor, comprises the structure in the claim.
As to element 9 above, looking to the specification, as noted above the accelerator is preferred to be a FPGA but may also be a GPU. The description of the claimed function of the accelerator performing the acceleration task in a configurable unit of the accelerator is described in 10:17-19, which describes the data being processed in a configurable unit of the accelerator. This is the algorithm that, along with the general processor, comprises the structure in the claim.
As to element 10 above, looking to the specification, as noted above the accelerator is preferred to be a FPGA but may also be a GPU. The description of the claimed function of the accelerator reporting a status of the acceleration task from the accelerator to the network interface controller is described in 10:19-22, which describes the accelerator returning the data to the NIC with status data. This is the algorithm that, along with the general processor, comprises the structure in the claim.
As to element 11 above, looking to the specification, as noted above the accelerator is preferred to be a FPGA but may also be a GPU. The description of the claimed function of the accelerator determining responsively to the metadata whether to perform acceleration on the data is described in 9:2-6 and 10:12-16, which describes the accelerator determining from the metadata whether and what acceleration tasks need to be performed. This is the algorithm that, along with the general processor, comprises the structure in the claim.
Because this/these claim limitation(s) is/are being interpreted under § 112(f), it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under § 112(f), applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under § 112(f) (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under § 112(f).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 24 and 36 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 24 further limits claim 23, stating that “wherein performing the acceleration task comprises performing the acceleration task in the configurable unit of the accelerator.” However, claim 23 discloses two acceleration tasks and thus claim 24 is indefinite.
Claim 36 further limits claim 35, stating that “wherein performing the acceleration task comprises performing the acceleration task in the configurable unit of the accelerator.” However, claim 35 discloses two acceleration tasks and thus claim 36 is indefinite.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 23 and 35 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 23 and 31 of copending Application No. 17/989,590 in view of U.S. Pat. 8,726,295 B2 to Hoover et al. (“Hoover”). Although the claims at issue are not identical, they are not patentably distinct from each other. This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
As to instant claim 23, it and reference claim 23 are compared below:
Instant ‘587 application claim 23:
23. (New) A method of communication, comprising:
receiving a packet in a network interface controller that is connected to a host and a communications network, the network interface controller comprising electrical circuitry configured as a packet processing pipeline having a plurality of stages, wherein at least one of the plurality of stages requires acceleration;
processing the packet in the packet processing pipeline, wherein processing the packet comprises:
performing a task on data in at least one of the plurality of stages in the packet processing pipeline;
transmitting data to an accelerator from the electrical circuitry, the transmitted data being associated with the at least one of the plurality of stages requiring acceleration;
performing an acceleration task on the transmitted data in a configurable unit of the accelerator;
returning processed data and a status of the acceleration task from the accelerator to the electrical circuitry, the processing data being associated with the at least one of the plurality of stages requiring acceleration; and
based on the status, receiving the processed data from the electrical circuitry and performing a subsequent acceleration task in the configurable unit of the accelerator; and
after processing the packet in the packet processing pipeline, routing the packet toward a destination.
Reference ‘590 application claim 23:
23. (New) A method comprising:
receiving a packet by an integrated circuit having electrical circuitry configured as a packet processing pipeline having a plurality of stages, wherein the integrated circuit is coupled to a host via a host interface and a network via a network interface;
storing the packet in a buffer;
performing a first task on the packet in a first stage of the packet processing pipeline, wherein the first task is a network processing task;
offloading a second task on the packet from the packet processing pipeline to a hardware accelerator coupled to the packet processing pipeline;
performing the second task on the packet by a configurable unit of the hardware accelerator;
performing a third task on the packet in a second stage of the packet processing pipeline after the first stage by the packet processing pipeline;
responsive to a status, performing a fourth task on the packet by the configurable unit of the hardware accelerator; and
routing the packet toward a destination after processing the packet in the packet processing pipeline.
For the most part, the reference claim is narrower than the instant claim, teaching the same as the instant claim only further adding a buffer storage and a third stage of processing. Thus the instant claim being examined is generic to a species claimed in a conflicting patent or application, i.e., the entire scope of the reference claim falls within the scope of the examined claim. The Examiner notes that the instant claim specifies that the circuit is a NIC.
To that end, Hoover discloses an analogous art, namely software or hardware acceleration by way of an accelerator as a stage in a multi-stage processor pipeline. Hoover at FIGS 4 and 5 and at 11:21-37, 13:33-61, and 15:61-65. Hoover discloses that a circuit which may comprise the pipeline may be connected to a NIC. Id.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to utilize such in a NIC, as one of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Further as to integrating the pipeline into the NIC itself instead of the IP Block connected to the NIC, Hoover does, however, refer to the NIC connected to the IP Block as “its [the IP Block’s] network interface controller”. Id. at 8:23-27. For this reason, it would have been obvious to one of ordinary skill in the art to combine the two elements such that the IP Block processor is in the NIC. This is based on the well-known obviousness rationale of making integral. MPEP § 2144.04 V. B., citing In re Larson, 340 F.2d 965, 968, 144 USPQ 347, 349 (CCPA 1965). Further, one of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
As to instant claim 35, it and reference claim 31 are compared below:
Instant ‘587 application claim 35:
35. (New) A network node comprising:
a host processor;
a network interface controller coupled to the host processor and a communications network, the network interface controller comprising electrical circuitry configured as a packet processing pipeline having a plurality of stages, wherein at least one of the plurality of stages requires acceleration; and
an accelerator coupled to the network interface controller, wherein:
the network interface controller is configured to:
receive a packet;
process the packet in the packet processing pipeline by:
performing a task on data in at least one of the plurality of stages in the packet processing pipeline; and
transmitting data to the accelerator from the electrical circuitry, the transmitted data being associated with the at least one of the plurality of stages requiring acceleration;
the accelerator is configured to:
perform an acceleration task on the transmitted data in a configurable unit of the accelerator;
return processed data and a status of the acceleration task from the accelerator to the electrical circuitry, the processed data being associated with the at least one of the plurality of stages requiring acceleration; and
based on the status, receiving the processed data from the electrical circuitry and performing a subsequent acceleration task in the configurable unit of the accelerator,
wherein the network interface controller is further configured to route the packet toward a destination after processing the packet in the packet processing pipeline.
Reference ‘590 application claim 31:
31. (New) A computing system comprising:
a network interface controller (NIC) to implement a packet processing pipeline having a plurality of stages, the NIC comprising a host interface coupled to a host and a network interface coupled to a network; and
a hardware accelerator coupled to the NIC, wherein:
the NIC is to:
receive a packet;
store the packet in a buffer;
perform a first task on the packet in a first stage of the packet processing pipeline, wherein the first task is a network processing task;
offload a second task on the packet from the packet processing pipeline to the hardware accelerator; and
perform a third task on the packet in a second stage of the packet processing pipeline after the first stage;
responsive to a status, offload a fourth task on the packet from the packet processing pipeline to the hardware accelerator; and
route the packet toward a destination after processing the packet in the packet processing pipeline; and
the hardware accelerator is to:
perform the second task on the packet at a configurable unit of the hardware accelerator; and
perform the fourth task on the packet at the configurable unit of the hardware accelerator.
For the most part, the reference claim is narrower than the instant claim, teaching the same as the instant claim only further adding a buffer storage and a third stage of processing. Thus the instant claim being examined is generic to a species claimed in a conflicting patent or application, i.e., the entire scope of the reference claim falls within the scope of the examined claim. The Examiner notes that the instant claim specifies that the system includes the host processor.
To that end, Hoover discloses an analogous art, namely software or hardware acceleration by way of an accelerator as a stage in a multi-stage processor pipeline. Hoover at FIGS 4 and 5 and at 11:21-37, 13:33-61, and 15:61-65. Hoover discloses that a circuit which may comprise the pipeline may be connected to a NIC and to a host processor as part of the whole system. Id.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to utilize the host in the overall system, as one of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Claims 44 and 46 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 31 and 33 of copending Application No. 17/989,590. Although the claims at issue are not identical, they are not patentably distinct from each other. This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
As to instant claim 44, it and reference claim 31 are compared below:
Instant ‘587 application claim 44:
44. (New) A computing system comprising:
a network interface controller coupled to a host processor and to a communications network, the network interface controller comprising electrical circuitry configured as a packet processing pipeline having a plurality of stages, wherein at least one of the plurality of stages requires acceleration;
an accelerator coupled to the network interface controller, wherein:
the network interface controller is configured to:
receive a packet; and
process the packet in the packet processing pipeline by:
performing a task on data in at least one of the plurality of stages in the packet processing pipeline; and
transmitting data to the accelerator from the electrical circuitry, the transmitted data being associated with the at least one of the plurality of stages requiring acceleration;
the accelerator is configured to:
perform an acceleration task on the transmitted data in a configurable unit of the accelerator;
return processed data and a status of the acceleration task from the accelerator to the electrical circuitry, the processed data being associated with the at least one of the plurality of stages requiring acceleration; and
based on the status, receiving the processed data from the electrical circuitry and performing a subsequent acceleration task in the configurable unit of the accelerator,
wherein the network interface controller is further configured to route the packet toward a destination after processing the packet in the packet processing pipeline.
Reference ‘590 application claim 31:
31. (New) A computing system comprising:
a network interface controller (NIC) to implement a packet processing pipeline having a plurality of stages, the NIC comprising a host interface coupled to a host and a network interface coupled to a network; and
a hardware accelerator coupled to the NIC, wherein:
the NIC is to:
receive a packet;
store the packet in a buffer;
perform a first task on the packet in a first stage of the packet processing pipeline, wherein the first task is a network processing task;
offload a second task on the packet from the packet processing pipeline to the hardware accelerator; and
perform a third task on the packet in a second stage of the packet processing pipeline after the first stage;
responsive to a status, offload a fourth task on the packet from the packet processing pipeline to the hardware accelerator; and
route the packet toward a destination after processing the packet in the packet processing pipeline; and
the hardware accelerator is to:
perform the second task on the packet at a configurable unit of the hardware accelerator; and
perform the fourth task on the packet at the configurable unit of the hardware accelerator.
The reference claim is narrower than the instant claim, teaching the same as the instant claim only further adding a buffer storage and a third stage of processing. Thus the instant claim being examined is generic to a species claimed in a conflicting patent or application, i.e., the entire scope of the reference claim falls within the scope of the examined claim. Claim 46 corresponds to reference claim 33.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 5, 7, 10, 12, 14, 16, 23-25, 27, 29, 32, 35-37, 39, 41, 44, and 46 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. 8,726,295 B2 to Hoover et al. (“Hoover”).
As to claim 1, Hoover discloses:
A method of communication, comprising the steps of: receiving a packet in a network interface controller that is connected to a host and a communications network, the network interface controller comprising electrical circuitry configured as a packet processing pipeline having a plurality of stages;
determining in the network interface controller that at least a portion of the stages of the pipeline are acceleration-defined stages;
Hoover discloses a method of communication comprising receiving a packet in a NIC connected to a host and communications network. Hoover at FIGS 2 and 3, elements 108 and 152 and at 3:52-55. The system including the NIC (element 122) further includes a processor 126 (electrical circuitry) running a packet processing pipeline having multiple stages, including at least one acceleration stage. Id. at FIGS 4 and 5 and at 11:21-37, 13:33-61, and 15:61-65.
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Hoover FIG 5 (excerpt).
As at least one of the stages are acceleration-related stages, and the device is aware of this, this reads on determining that one of the stages in the system is an accelerated-defined stage. Hoover at 3:8-13 (“The NOC coprocessor of FIG. 1 is optimized to accelerate particular data processing tasks at the behest of the main processor (156)”).
Hoover does not disclose that this pipeline and pipeline processing is in the NIC itself, rather it is in an IP Block connected directly to the NIC in the expanded set 122. Hoover at FIG 3. Hoover does, however, refer to the NIC connected to the IP Block as “its [the IP Block’s] network interface controller”. Id. at 8:23-27.
That being said, it would have been obvious to one of ordinary skill in the art to combine the two elements such that the IP Block processor is in the NIC. This is based on the well-known obviousness rationale of making integral. MPEP § 2144.04 V. B., citing In re Larson, 340 F.2d 965, 968, 144 USPQ 347, 349 (CCPA 1965). Further, one of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
processing the packet in the pipeline, wherein processing the packet comprises: transmitting data to an accelerator from the acceleration-defined stages; performing respective acceleration tasks on the transmitted data in the accelerator;
Hoover discloses processing the packet in the pipeline includes performing a task on data in one of the stages and transmitting data associated with a stage requiring acceleration to an accelerator where an acceleration task is performed. Hoover at FIG 5 and at 14:52-15:9; note that the accelerator may be part of any stage, such as in stage 2, which means processing occurs first in stage 1 followed by accelerated processing in stage 2. Id. at 16:17-23.
Note further that while the accelerator is primarily disclosed as software, “readers of skill in the art will immediately recognize that an I/O accelerator may also be implemented as hardware aggregation of sequential and non-sequential logic separate from the processor (126) in the IP block (104) where the I/O accelerator has its own processor and is adapted to the network through a low latency, high bandwidth application messaging interconnect (107).” Id. at 16:56-65. This means the processor circuit including the pipeline necessarily forwards the data to the accelerator processor by way of the disclosed connection. Id.
and returning processed data from the accelerator to receiving stages of the pipeline;
Hoover discloses the data associated with the stage requiring acceleration, after passing through the accelerator, returning to the processing pipeline in the circuitry (processor). Hoover at 14:17-15:9.
and after processing the packet in the pipeline routing the packet toward a destination,
Hoover discloses that, after the packet is processed in the pipeline, it is routed toward a destination. Hoover at 9:65-66 and 14:17-51.
wherein performing respective acceleration tasks comprises performing one of the acceleration tasks in a configurable unit of the accelerator;
Hoover discloses that the processing stage units are configurable. Hoover at 13:36-47.
thereafter reporting a status of the one acceleration task from the accelerator to the network interface controller; and responsively to the status returning the processed data to the accelerator to perform another acceleration task.
Hoover discloses reporting a status of a stage processor task to monitor application 640. Hoover at 15:32-48. As such may change the instances of a subsequent stage which may include an accelerated one, this reads on performing another accelerated task responsive to the status.
Further as to claim 3:
The method according to claim 1, wherein for each of the acceleration tasks, the receiving stages differ from the acceleration-defined stages.
Hoover discloses that one of the stages includes acceleration, thus it is an acceleration-defined stage. Hoover further states that after an accelerated stage the data may be returned to a receiving part of the plurality of stages which is not an accelerated stage. Hoover at FIG 5, noting the flow from stage 1 to an instance of stage 2.
Further as to claim 5:
The method according to claim 1, wherein transmitting data to an accelerator comprises the steps of: adding metadata to the data; and determining in the accelerator responsively to the metadata whether to perform acceleration on the data or to direct the data to the communications network.
Hoover discloses that metadata may be added to packet data prior to it being forwarded to a processing stage, including an accelerated one. Hoover at 12:1-18.
Further as to claim 7:
The method according to claim 1, wherein transmitting data to an accelerator comprises transmitting an indication to perform a specified acceleration task.
Hoover discloses that transmitting the data to the accelerator includes an indication to perform a specific acceleration task. Hoover at 16:66-17:10 and 18:16-21.
As to claim 10, Hoover discloses:
A communications apparatus, comprising:
a host processor;
a network interface controller coupled to the host processor and to a communications network, the network interface controller comprising electrical circuitry configured as a packet processing pipeline having a plurality of stages;
Hoover discloses a system for communication comprising a NIC connected to a host processor and communications network for receiving and processing a packet. Hoover at FIGS 2 and 3, elements 108 and 152 and at 3:52-55. The system including the NIC (element 122) further includes a processor 126 (electrical circuitry) running a packet processing pipeline having multiple stages, including at least one acceleration stage. Id. at FIGS 4 and 5 and at 11:21-37, 13:33-61, and 15:61-65.
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Hoover FIG 5 (excerpt).
Hoover does not disclose that this pipeline and pipeline processing is in the NIC itself, rather it is in an IP Block connected directly to the NIC in the expanded set 122. Hoover at FIG 3. Hoover does, however, refer to the NIC connected to the IP Block as “its [the IP Block’s] network interface controller”. Id. at 8:23-27.
That being said, it would have been obvious to one of ordinary skill in the art to combine the two elements such that the IP Block processor is in the NIC. This is based on the well-known obviousness rationale of making integral. MPEP § 2144.04 V. B., citing In re Larson, 340 F.2d 965, 968, 144 USPQ 347, 349 (CCPA 1965). Further, one of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
an accelerator linked to the network interface controller,
Hoover discloses an accelerator coupled to the NIC. Hoover at FIG 5 and at 14:52-15:9. Note further that while the accelerator is primarily disclosed as software, “readers of skill in the art will immediately recognize that an I/O accelerator may also be implemented as hardware aggregation of sequential and non-sequential logic separate from the processor (126) in the IP block (104) where the I/O accelerator has its own processor and is adapted to the network through a low latency, high bandwidth application messaging interconnect (107).” Id. at 16:56-65. This means the processor circuit including the pipeline necessarily forwards the data to the accelerator processor by way of the disclosed connection. Id.
wherein the network interface controller is configured for:
receiving a packet; determining that at least a portion of the stages of the pipeline are acceleration-defined stages; processing the packet in the pipeline, wherein processing the packet comprises: transmitting data to the accelerator from the acceleration-defined stages;
Hoover discloses receiving and processing the packet in the pipeline includes performing a task on data in one of the stages and transmitting data associated with a stage requiring acceleration to an accelerator where an acceleration task is performed. Hoover at FIG 5 and at 14:52-15:9; note that the accelerator may be part of any stage, such as in stage 2, which means processing occurs first in stage 1 followed by accelerated processing in stage 2. Id. at 16:17-23.
As at least one of the stages are acceleration-related stages, and the device is aware of this, this reads on determining that one of the stages in the system is an accelerated-defined stage. Hoover at 3:8-13 (“The NOC coprocessor of FIG. 1 is optimized to accelerate particular data processing tasks at the behest of the main processor (156)”). Further, one of ordinary skill in the art at the time would have understood that the NIC deliberately forwarding data to the accelerator to be accelerated means it is determined that acceleration is necessary.
causing performance of respective acceleration tasks on the transmitted data in the accelerator; and returning processed data from the accelerator to receiving stages of the pipeline;
Hoover discloses that the accelerator performs an acceleration task on the data and, after passing through the accelerator, returns it by way of the accelerator to the processing pipeline in the circuitry (processor). Hoover at 14:17-15:9.
after processing the packet in the pipeline routing the packet toward a destination,
Hoover discloses that, after the packet is processed in the pipeline, it is routed toward a destination by way of the circuitry. Id. at 9:65-66 and 14:17-51.
wherein causing performance of respective acceleration tasks comprises causing performance of one of the acceleration tasks in a configurable unit of the accelerator;
Hoover discloses that the processing stage units are configurable. Hoover at 13:36-47.
causing report of a status of the one acceleration task from the accelerator to the network interface controller; and responsively to the status returning the processed data to the accelerator to perform another acceleration task.
Hoover discloses reporting a status of a stage processor task to monitor application 640. Hoover at 15:32-48. As such may change the instances of a subsequent stage which may include an accelerated one, this reads on performing another accelerated task responsive to the status.
Further as to claim 12:
The apparatus according to claim 10, wherein for each of the acceleration tasks, the receiving stages differ from the acceleration-defined stages.
Hoover discloses that one of the stages includes acceleration, thus it is an acceleration-defined stage. Hoover further states that after an accelerated stage the data may be returned to a receiving part of the plurality of stages which is not an accelerated stage. Hoover at FIG 5, noting the flow from stage 1 to an instance of stage 2.
Further as to claim 14:
The apparatus according to claim 10, wherein transmitting data to an accelerator comprises the steps of: adding metadata to the data; and determining in the accelerator responsively to the metadata whether to perform acceleration on the data or to direct the data to the communications network.
Hoover discloses that metadata may be added to packet data prior to it being forwarded to a processing stage, including an accelerated one. Hoover at 12:1-18.
Further as to claim 16:
The apparatus according to claim 10, wherein transmitting data to the accelerator comprises transmitting an indication to perform a specified acceleration task.
Hoover discloses that transmitting the data to the accelerator includes an indication to perform a specific acceleration task. Hoover at 16:66-17:10 and 18:16-21.
As to claim 23, Hoover discloses:
A method of communication, comprising: receiving a packet in a network interface controller that is connected to a host and a communications network, the network interface controller comprising electrical circuitry configured as a packet processing pipeline having a plurality of stages, wherein at least one of the plurality of stages requires acceleration;
Hoover discloses a method of communication comprising receiving a packet in a NIC connected to a host and communications network. Hoover at FIGS 2 and 3, elements 108 and 152 and at 3:52-55. The system including the NIC (element 122) further includes a processor 126 (electrical circuitry) running a packet processing pipeline having multiple stages, including at least one acceleration stage. Id. at FIGS 4 and 5 and at 11:21-37, 13:33-61, and 15:61-65.
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Hoover FIG 5 (excerpt).
Hoover does not disclose that this pipeline and pipeline processing is in the NIC itself, rather it is in an IP Block connected directly to the NIC in the expanded set 122. Hoover at FIG 3. Hoover does, however, refer to the NIC connected to the IP Block as “its [the IP Block’s] network interface controller”. Id. at 8:23-27.
That being said, it would have been obvious to one of ordinary skill in the art to combine the two elements such that the IP Block processor is in the NIC. This is based on the well-known obviousness rationale of making integral. MPEP § 2144.04 V. B., citing In re Larson, 340 F.2d 965, 968, 144 USPQ 347, 349 (CCPA 1965). Further, one of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
processing the packet in the packet processing pipeline, wherein processing the packet comprises: performing a task on data in at least one of the plurality of stages in the packet processing pipeline; transmitting data to an accelerator from the electrical circuitry, the transmitted data being associated with the at least one of the plurality of stages requiring acceleration;
performing an acceleration task on the transmitted data in a configurable unit of the accelerator;
Hoover discloses processing the packet in the pipeline includes performing a task on data in one of the stages and transmitting data associated with a stage requiring acceleration to an accelerator where an acceleration task is performed. Hoover at FIG 5 and at 14:52-15:9; note that the accelerator may be part of any stage, such as in stage 2, which means processing occurs first in stage 1 followed by accelerated processing in stage 2. Id. at 16:17-23. Hoover discloses that the processing stage units are configurable. Hoover at 13:36-47.
Note further that while the accelerator is primarily disclosed as software, “readers of skill in the art will immediately recognize that an I/O accelerator may also be implemented as hardware aggregation of sequential and non-sequential logic separate from the processor (126) in the IP block (104) where the I/O accelerator has its own processor and is adapted to the network through a low latency, high bandwidth application messaging interconnect (107).” Id. at 16:56-65. This means the processor circuit including the pipeline necessarily forwards the data to the accelerator processor by way of the disclosed connection. Id.
returning processed data and a status from the accelerator to the electrical circuitry, the processing data being associated with the at least one of the plurality of stages requiring acceleration; and
based on the status, receiving the processed data from the electrical circuitry and performing a subsequent acceleration task in the configurable unit of the accelerator; and
Hoover discloses the data associated with the stage requiring acceleration, after passing through the accelerator, returning to the processing pipeline in the circuitry (processor). Hoover at 14:17-15:9. Hoover discloses reporting a status of a stage processor task to monitor application 640. Hoover at 15:32-48.
As such may change the instances of a subsequent stage which may include an accelerated one, this reads on performing another accelerated task responsive to the status.
after processing the packet in the packet processing pipeline, routing the packet toward a destination.
Hoover discloses that, after the packet is processed in the pipeline, it is routed toward a destination. Hoover at 9:65-66 and 14:17-51.
Further as to claim 24:
The method of claim 23, wherein performing the acceleration task comprises performing the acceleration task in the configurable unit of the accelerator.
Hoover discloses that the processing stage units are configurable. Hoover at 13:36-47.
Further as to claim 25:
The method of claim 23, wherein processing the packet further comprises:
reporting a status of the acceleration task from the accelerator to the network interface controller; and
responsive to the status, performing another task on data in at least another one of the plurality of stages in the packet processing pipeline.
Hoover discloses reporting a status of a stage processor task to monitor application 640. Hoover at 15:32-48. As such may change the instances of a subsequent stage which may include an accelerated one, this reads on performing another accelerated task responsive to the status.
Further as to claim 27:
The method of claim 23, wherein the at least one of the plurality of stages requiring acceleration is an acceleration-defined stage, wherein returning the processing data comprises returning the processed data to a receiving stage of the plurality of stages that differs from the acceleration-defined stage.
Hoover discloses that one of the stages includes acceleration, thus it is an acceleration-defined stage. Hoover further states that after an accelerated stage the data may be returned to a receiving part of the plurality of stages which is not an accelerated stage. Hoover at FIG 5, noting the flow from stage 1 to an instance of stage 2.
Further as to claim 29:
The method of claim 23, further comprising:
adding metadata to the data before transmitting the data to the accelerator; and
determining in the accelerator responsively to the metadata whether to perform acceleration on the data.
Hoover discloses that metadata may be added to packet data prior to it being forwarded to a processing stage, including an accelerated one. Hoover at 12:1-18.
Further as to claim 32:
The method of claim 23, wherein transmitting data to the accelerator comprises transmitting an indication to perform the acceleration task.
Hoover discloses that transmitting the data to the accelerator includes an indication to perform a specific acceleration task. Hoover at 16:66-17:10 and 18:16-21.
As to claim 35, Hoover discloses:
A network node comprising:
a host processor;
a network interface controller coupled to the host processor and a communications network, the network interface controller comprising electrical circuitry configured as a packet processing pipeline having a plurality of stages, wherein at least one of the plurality of stages requires acceleration;
Hoover discloses a system for communication comprising a NIC connected to a host processor and communications network for receiving and processing a packet. Hoover at FIGS 2 and 3, elements 108 and 152 and at 3:52-55. The system including the NIC (element 122) further includes a processor 126 (electrical circuitry) running a packet processing pipeline having multiple stages, including at least one acceleration stage. Id. at FIGS 4 and 5 and at 11:21-37, 13:33-61, and 15:61-65.
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Hoover FIG 5 (excerpt).
Hoover does not disclose that this pipeline and pipeline processing is in the NIC itself, rather it is in an IP Block connected directly to the NIC in the expanded set 122. Hoover at FIG 3. Hoover does, however, refer to the NIC connected to the IP Block as “its [the IP Block’s] network interface controller”. Id. at 8:23-27.
That being said, it would have been obvious to one of ordinary skill in the art to combine the two elements such that the IP Block processor is in the NIC. This is based on the well-known obviousness rationale of making integral. MPEP § 2144.04 V. B., citing In re Larson, 340 F.2d 965, 968, 144 USPQ 347, 349 (CCPA 1965). Further, one of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
and; an accelerator coupled to the network interface controller,
Hoover discloses an accelerator coupled to the NIC. Hoover at FIG 5 and at 14:52-15:9. Note further that while the accelerator is primarily disclosed as software, “readers of skill in the art will immediately recognize that an I/O accelerator may also be implemented as hardware aggregation of sequential and non-sequential logic separate from the processor (126) in the IP block (104) where the I/O accelerator has its own processor and is adapted to the network through a low latency, high bandwidth application messaging interconnect (107).” Id. at 16:56-65. This means the processor circuit including the pipeline necessarily forwards the data to the accelerator processor by way of the disclosed connection. Id.
wherein: the network interface controller is configured to:
receive a packet; process the packet in the packet processing pipeline by performing a task on data in at least one of the plurality of stages in the packet processing pipeline; and transmitting data to the accelerator from the electrical circuitry, the transmitted data being associated with the at least one of the plurality of stages requiring acceleration;
Hoover discloses processing the packet in the pipeline includes performing a task on data in one of the stages and transmitting data associated with a stage requiring acceleration to an accelerator where an acceleration task is performed. Hoover at FIG 5 and at 14:52-15:9; note that the accelerator may be part of any stage, such as in stage 2, which means processing occurs first in stage 1 followed by accelerated processing in stage 2. Id. at 16:17-23.
the accelerator is configured to:
perform an acceleration task on the transmitted data in a configurable unit of the accelerator; return processed data and a status of the acceleration task from the accelerator to the electrical circuitry, the processed data being associated with the at least one of the plurality of stages requiring acceleration;
based on the status, receiving the processed data from the electrical circuitry and performing a subsequent acceleration task in the configurable unit of the accelerator;
Hoover discloses that the accelerator performs an acceleration task on the data and, after passing through the accelerator, returns it by way of the accelerator to the processing pipeline in the circuitry (processor). Hoover at 14:17-15:9. Hoover discloses the data associated with the stage requiring acceleration, after passing through the accelerator, returning to the processing pipeline in the circuitry (processor). Hoover at 14:17-15:9. Hoover discloses reporting a status of a stage processor task to monitor application 640. Hoover at 15:32-48. Hoover discloses that the processing stage units are configurable. Hoover at 13:36-47.
As such may change the instances of a subsequent stage which may include an accelerated one, this reads on performing another accelerated task responsive to the status.
wherein the network interface controller is further configured to route the packet toward a destination after processing the packet in the packet processing pipeline.
Hoover discloses that, after the packet is processed in the pipeline, it is routed toward a destination by way of the circuitry. Id. at 9:65-66 and 14:17-51.
Further as to claim 36:
The network node of claim 35, wherein the accelerator is further configured to: perform the acceleration task in the configurable unit of the accelerator; report a status of the acceleration task from the accelerator to the network interface controller, and responsive to the status, perform another task on data in at least another one of the plurality of stages in the packet processing pipeline.
Hoover discloses that the processing stage units are configurable. Hoover at 13:36-47. Hoover further discloses reporting a status of a stage processor task to monitor application 640. Id. at 15:32-48. As such may change the instances of a subsequent stage which may include an accelerated one, this reads on performing another accelerated task responsive to the status.
Further as to claim 37:
The network node of claim 35, wherein the at least one of the plurality of stages requiring acceleration is an acceleration-defined stage, wherein returning the processed data comprises returning the processed data to a receiving stage of the plurality of stages that differs from the acceleration-defined stages.
Hoover discloses that one of the stages includes acceleration, thus it is an acceleration-defined stage. Hoover further states that after an accelerated stage the data may be returned to a receiving part of the plurality of stages which is not an accelerated stage. Hoover at FIG 5, noting the flow from stage 1 to an instance of stage 2.
Further as to claim 39:
The network node of claim 35, wherein:
the network interface controller is further to add metadata to the data before transmitting the data to the accelerator; and
the accelerator is further configured to determine responsively to the metadata whether to perform acceleration on the data.
Hoover discloses that metadata may be added to packet data prior to it being forwarded to a processing stage, including an accelerated one. Hoover at 12:1-18.
Further as to claim 41:
The network node of claim 35, wherein the network interface controller is to transmit an indication to perform the acceleration task.
Hoover discloses that transmitting the data to the accelerator includes an indication to perform a specific acceleration task. Hoover at 16:66-17:10 and 18:16-21.
As to claim 44, Hoover discloses:
A computing system comprising:
a network interface controller coupled to a host processor and to a communications network, the network interface controller comprising electrical circuitry configured as a packet processing pipeline having a plurality of stages, wherein at least one of the plurality of stages requires acceleration;
Hoover discloses a system for communication comprising a NIC connected to a host processor and communications network for receiving and processing a packet. Hoover at FIGS 2 and 3, elements 108 and 152 and at 3:52-55. The system including the NIC (element 122) further includes a processor 126 (electrical circuitry) running a packet processing pipeline having multiple stages, including at least one acceleration stage. Id. at FIGS 4 and 5 and at 11:21-37, 13:33-61, and 15:61-65.
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Hoover FIG 5 (excerpt).
Hoover does not disclose that this pipeline and pipeline processing is in the NIC itself, rather it is in an IP Block connected directly to the NIC in the expanded set 122. Hoover at FIG 3. Hoover does, however, refer to the NIC connected to the IP Block as “its [the IP Block’s] network interface controller”. Id. at 8:23-27.
That being said, it would have been obvious to one of ordinary skill in the art to combine the two elements such that the IP Block processor is in the NIC. This is based on the well-known obviousness rationale of making integral. MPEP § 2144.04 V. B., citing In re Larson, 340 F.2d 965, 968, 144 USPQ 347, 349 (CCPA 1965). Further, one of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
an accelerator coupled to the network interface controller,
Hoover discloses an accelerator coupled to the NIC. Hoover at FIG 5 and at 14:52-15:9. Note further that while the accelerator is primarily disclosed as software, “readers of skill in the art will immediately recognize that an I/O accelerator may also be implemented as hardware aggregation of sequential and non-sequential logic separate from the processor (126) in the IP block (104) where the I/O accelerator has its own processor and is adapted to the network through a low latency, high bandwidth application messaging interconnect (107).” Id. at 16:56-65. This means the processor circuit including the pipeline necessarily forwards the data to the accelerator processor by way of the disclosed connection. Id.
wherein:
the network interface controller is configured to:
receive a packet; and process the packet in the packet processing pipeline by:
performing a task on data in at least one of the plurality of stages in the packet processing pipeline; and transmitting data to the accelerator from the electrical circuitry, the transmitted data being associated with the at least one of the plurality of stages requiring acceleration;
Hoover discloses processing the packet in the pipeline includes performing a task on data in one of the stages and transmitting data associated with a stage requiring acceleration to an accelerator where an acceleration task is performed. Hoover at FIG 5 and at 14:52-15:9; note that the accelerator may be part of any stage, such as in stage 2, which means processing occurs first in stage 1 followed by accelerated processing in stage 2. Id. at 16:17-23.
the accelerator is configured to: perform an acceleration task on the transmitted data in a configurable unit of the accelerator; return processed data and a status from the accelerator to the electrical circuitry, the processed data being associated with the at least one of the plurality of stages requiring acceleration;
based on the status, receiving the processed data from the electrical circuitry and performing a subsequent acceleration task in the configurable unit of the accelerator;
Hoover discloses that the accelerator performs an acceleration task on the data and, after passing through the accelerator, returns it by way of the accelerator to the processing pipeline in the circuitry (processor). Hoover at 14:17-15:9. Hoover discloses the data associated with the stage requiring acceleration, after passing through the accelerator, returning to the processing pipeline in the circuitry (processor). Hoover at 14:17-15:9. Hoover discloses reporting a status of a stage processor task to monitor application 640. Hoover at 15:32-48. Hoover discloses that the processing stage units are configurable. Hoover at 13:36-47.
As such may change the instances of a subsequent stage which may include an accelerated one, this reads on performing another accelerated task responsive to the status.
wherein the network interface controller is further configured to route the packet toward a destination after processing the packet in the packet processing pipeline.
Hoover discloses that, after the packet is processed in the pipeline, it is routed toward a destination by way of the circuitry. Id. at 9:65-66 and 14:17-51.
Further as to claim 46:
The computing system of claim 44, wherein the network interface controller and the accelerator are integrated in an integrated circuit.
Hoover discloses the NIC and accelerator may be integrated in an integrated circuit. Hoover at FIG 6 element 122.
Claims 19-22 are rejected under 35 U.S.C. 103 as being unpatentable over Hoover in view of Olsen et al., “Border Control; Sandboxing accelerators”, 2015 48th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), with a latest publication date of February 16, 20171 (hereinafter “Olsen”).
As to claim 19, Hoover discloses:
A method of communication, comprising the steps of:
receiving a packet in a network interface controller that is connected to a host and a communications network, the network interface controller comprising electrical circuitry configured as a packet processing pipeline having a plurality of stages;
determining in the network interface controller that at least a portion of the stages of the pipeline are acceleration-defined stages;
Hoover discloses a method of communication comprising receiving a packet in a NIC connected to a host and communications network. Hoover at FIGS 2 and 3, elements 108 and 152 and at 3:52-55. The system including the NIC (element 122) further includes a processor 126 (electrical circuitry) running a packet processing pipeline having multiple stages, including at least one acceleration stage. Id. at FIGS 4 and 5 and at 11:21-37, 13:33-61, and 15:61-65.
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Hoover FIG 5 (excerpt).
As at least one of the stages are acceleration-related stages, and the device is aware of this, this reads on determining that one of the stages in the system is an accelerated-defined stage. Hoover at 3:8-13 (“The NOC coprocessor of FIG. 1 is optimized to accelerate particular data processing tasks at the behest of the main processor (156)”).
Hoover does not disclose that this pipeline and pipeline processing is in the NIC itself, rather it is in an IP Block connected directly to the NIC in the expanded set 122. Hoover at FIG 3. Hoover does, however, refer to the NIC connected to the IP Block as “its [the IP Block’s] network interface controller”. Id. at 8:23-27.
That being said, it would have been obvious to one of ordinary skill in the art to combine the two elements such that the IP Block processor is in the NIC. This is based on the well-known obviousness rationale of making integral. MPEP § 2144.04 V. B., citing In re Larson, 340 F.2d 965, 968, 144 USPQ 347, 349 (CCPA 1965). Further, one of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
processing the packet in the pipeline, wherein processing the packet comprises: transmitting data to an accelerator from the acceleration-defined stages;
performing respective acceleration tasks on the transmitted data in the accelerator;
Hoover discloses processing the packet in the pipeline includes performing a task on data in one of the stages and transmitting data associated with a stage requiring acceleration to an accelerator where an acceleration task is performed. Hoover at FIG 5 and at 14:52-15:9; note that the accelerator may be part of any stage, such as in stage 2, which means processing occurs first in stage 1 followed by accelerated processing in stage 2. Id. at 16:17-23.
Note further that while the accelerator is primarily disclosed as software, “readers of skill in the art will immediately recognize that an I/O accelerator may also be implemented as hardware aggregation of sequential and non-sequential logic separate from the processor (126) in the IP block (104) where the I/O accelerator has its own processor and is adapted to the network through a low latency, high bandwidth application messaging interconnect (107).” Id. at 16:56-65. This means the processor circuit including the pipeline necessarily forwards the data to the accelerator processor by way of the disclosed connection. Id.
and returning processed data from the accelerator to receiving stages of the pipeline;
Hoover discloses the data associated with the stage requiring acceleration, after passing through the accelerator, returning to the processing pipeline in the circuitry (processor). Hoover at 14:17-15:9.
and after processing the packet in the pipeline routing the packet toward a destination,
Hoover discloses that, after the packet is processed in the pipeline, it is routed toward a destination. Hoover at 9:65-66 and 14:17-51.
wherein performing respective acceleration tasks comprises performing one of the acceleration tasks in a […] unit of the accelerator;
thereafter reporting a status of the one acceleration task from the accelerator to the network interface controller; and responsively to the status returning the processed data to the accelerator to perform another acceleration task.
Hoover discloses reporting a status of a stage processor task to monitor application 640. Hoover at 15:32-48. As such may change the instances of a subsequent stage which may include an accelerated one, this reads on performing another accelerated task responsive to the status.
Hoover discloses that the processing stage units are configurable. Hoover at 13:36-47. However, Hoover fails to disclose that it is a sandbox unit of the accelerator.
Olsen teaches an analogous art, namely a hardware accelerator connected to a processor for accelerated processing of specific jobs. Olsen at Abstract and Sec. 1, pp. 1-2. Olsen specifies that because they can share access to memory, it is beneficial to sandbox accelerators for security reasons. Id. and at FIG 1 and p. 2 as well as Sec. 3 pp. 4-5. This reads a sandbox unit of an accelerator.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Hoover in such a manner, namely as to configuring the accelerator unit to be sandboxed. Hoover mentions operation on virtual memory, and Olsen states that in such cases sandboxing the accelerator provides security. Further, one of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Further as to claim 20:
The method according to claim 19, wherein the one acceleration task is a decryption of a portion of the packet, and the other acceleration task is an acceleration of the decrypted portion of the packet.
Hoover discloses multiple acceleration tasks as noted above. Olsen discloses that accelerators may be used for cryptographic processes using encryption keys, which one of ordinary skill in the art at the time would have understood includes decryption. Olsen at Sec. 1 pp. 1-2.
As to claim 21:
A communications apparatus, comprising:
a host processor;
a network interface controller coupled to the host processor and to a communications network, the network interface controller comprising electrical circuitry configured as a packet processing pipeline having a plurality of stages;
Hoover discloses a method of communication comprising receiving a packet in a NIC connected to a host and communications network. Hoover at FIGS 2 and 3, elements 108 and 152 and at 3:52-55. The system including the NIC (element 122) further includes a processor 126 (electrical circuitry) running a packet processing pipeline having multiple stages, including at least one acceleration stage. Id. at FIGS 4 and 5 and at 11:21-37, 13:33-61, and 15:61-65.
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Hoover FIG 5 (excerpt).
Hoover does not disclose that this pipeline and pipeline processing is in the NIC itself, rather it is in an IP Block connected directly to the NIC in the expanded set 122. Hoover at FIG 3. Hoover does, however, refer to the NIC connected to the IP Block as “its [the IP Block’s] network interface controller”. Id. at 8:23-27.
That being said, it would have been obvious to one of ordinary skill in the art to combine the two elements such that the IP Block processor is in the NIC. This is based on the well-known obviousness rationale of making integral. MPEP § 2144.04 V. B., citing In re Larson, 340 F.2d 965, 968, 144 USPQ 347, 349 (CCPA 1965). Further, one of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
an accelerator linked to the network interface controller,
Hoover discloses processing the packet in the pipeline includes performing a task on data in one of the stages and transmitting data associated with a stage requiring acceleration to an accelerator where an acceleration task is performed. Hoover at FIG 5 and at 14:52-15:9.
Note further that while the accelerator is primarily disclosed as software, “readers of skill in the art will immediately recognize that an I/O accelerator may also be implemented as hardware aggregation of sequential and non-sequential logic separate from the processor (126) in the IP block (104) where the I/O accelerator has its own processor and is adapted to the network through a low latency, high bandwidth application messaging interconnect (107).” Id. at 16:56-65. This means the processor circuit including the pipeline necessarily forwards the data to the accelerator processor by way of the disclosed connection. Id.
wherein the network interface controller is configured for: receiving a packet;
Hoover discloses a method of communication comprising receiving a packet in a NIC connected to a host and communications network. Hoover at FIGS 2 and 3, elements 108 and 152 and at 3:52-55.
determining that at least a portion of the stages of the pipeline are acceleration-defined stages;
As at least one of the stages are acceleration-related stages, and the device is aware of this, this reads on determining that one of the stages in the system is an accelerated-defined stage. Hoover at 3:8-13 (“The NOC coprocessor of FIG. 1 is optimized to accelerate particular data processing tasks at the behest of the main processor (156)”). Further, one of ordinary skill in the art at the time would have understood that the NIC deliberately forwarding data to the accelerator to be accelerated means it is determined that acceleration is necessary.
processing the packet in the pipeline, wherein processing the packet comprises: transmitting data to the accelerator from the acceleration-defined stages; causing performance of respective acceleration tasks on the transmitted data in the accelerator;
Hoover discloses processing the packet in the pipeline includes performing a task on data in one of the stages and transmitting data associated with a stage requiring acceleration to an accelerator where an acceleration task is performed. Hoover at FIG 5 and at 14:52-15:9; note that the accelerator may be part of any stage, such as in stage 2, which means processing occurs first in stage 1 followed by accelerated processing in stage 2. Id. at 16:17-23.
receiving processed data from the accelerator to receiving stages of the pipeline;
Hoover discloses the data associated with the stage requiring acceleration, after passing through the accelerator, returning to the processing pipeline in the circuitry (processor). Hoover at 14:17-15:9.
after processing the packet in the pipeline routing the packet toward a destination,
Hoover discloses that, after the packet is processed in the pipeline, it is routed toward a destination. Hoover at 9:65-66 and 14:17-51.
Wherein causing performance of respective acceleration tasks comprises causing performance of one of the acceleration tasks in a […] unit of the accelerator; and causing report of a status of the one acceleration task from the accelerator to the network interface controller; and responsively to the status returning the processed data to the accelerator to perform another acceleration task.
Hoover discloses reporting a status of a stage processor task to monitor application 640. Hoover at 15:32-48. As such may change the instances of a subsequent stage which may include an accelerated one, this reads on performing another accelerated task responsive to the status.
Hoover discloses that the processing stage units are configurable. Hoover at 13:36-47. However, Hoover fails to disclose that it is a sandbox unit of the accelerator.
Olsen teaches an analogous art, namely a hardware accelerator connected to a processor for accelerated processing of specific jobs. Olsen at Abstract and Sec. 1, pp. 1-2. Olsen specifies that because they can share access to memory, it is beneficial to sandbox accelerators for security reasons. Id. and at FIG 1 and p. 2 as well as Sec. 3 pp. 4-5. This reads a sandbox unit of an accelerator.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Hoover in such a manner, namely as to configuring the accelerator unit to be sandboxed. Hoover mentions operation on virtual memory, and Olsen states that in such cases sandboxing the accelerator provides security. Further, one of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Further as to claim 22:
The method according to claim 21, wherein the one acceleration task is a decryption of a portion of the packet, and the other acceleration task is an acceleration of the decrypted portion of the packet.
Hoover discloses multiple acceleration tasks as noted above. Olsen discloses that accelerators may be used for cryptographic processes using encryption keys, which one of ordinary skill in the art at the time would have understood includes decryption. Olsen at Sec. 1 pp. 1-2.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Hoover as applied to claim 1 above, and further in view of U.S. Pat. PGPUB 2013/0142205A1 to Munoz.
As to claim 2:
The method according to claim 1, wherein the stages of the pipeline are organized in a hierarchy having levels, further comprising: in each of the levels of the hierarchy configuring the stages thereof by processes executing in respective domains.
Hoover discloses the invention of claim 1 above. Hoover discloses at least three stages in the pipeline, which reads a hierarchy having levels. Hoover does not disclose that in each level, configuring the stages included processes executing in respective domains.
Munoz discloses an analogous art, namely a packet processor including multiple stages including accelerator stages. Munoz at FIG 1 element 100 as well as elements 1061, 106M, 1081, and 108N. Munoz adds that the packet processing including acceleration tasks provides packet scheduling with multiple levels of hierarchy and stages process in different domains. Id. at ¶¶24, 27, and 28.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Hoover in such a manner, namely as to configuring the stages included processes executing in respective domains. One of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Hoover as applied to claim 10 above, and further in view of Munoz.
As to claim 11:
The apparatus according to claim 10, wherein the stages of the pipeline are organized in a hierarchy having levels, further comprising: in each of the levels of the hierarchy configuring the stages thereof by respective processes executing in corresponding domains.
Hoover discloses the invention of claim 10 above. Hoover discloses at least three stages in the pipeline, which reads a hierarchy having levels. Hoover does not disclose that in each level, configuring the stages included processes executing in respective domains.
Munoz discloses an analogous art, namely a packet processor including multiple stages including accelerator stages. Munoz at FIG 1 element 100 as well as elements 1061, 106M, 1081, and 108N. Munoz adds that the packet processing including acceleration tasks provides packet scheduling with multiple levels of hierarchy and stages process in different domains. Id. at ¶¶24, 27, and 28.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Hoover in such a manner, namely as to configuring the stages included processes executing in respective domains. One of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Hoover as applied to claim 23 above, and further in view of Munoz.
As to claim 26:
The method of claim 23, wherein the stages of the packet processing pipeline are organized in a hierarchy having levels, further comprising:
in each of the levels of the hierarchy, configuring the plurality of stages thereof by processes executing in respective domains.
Hoover discloses the invention of claim 23 above. Hoover discloses at least three stages in the pipeline, which reads a hierarchy having levels. Hoover does not disclose that in each level, configuring the stages included processes executing in respective domains.
Munoz discloses an analogous art, namely a packet processor including multiple stages including accelerator stages. Munoz at FIG 1 element 100 as well as elements 1061, 106M, 1081, and 108N. Munoz adds that the packet processing including acceleration tasks provides packet scheduling with multiple levels of hierarchy and stages process in different domains. Id. at ¶¶24, 27, and 28.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Hoover in such a manner, namely as to configuring the stages included processes executing in respective domains. One of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Hoover as applied to claim 1 above, and further in view of U.S. Pat. PGPUB 2017/0180273A1 to Daly et al. (“Daly”).
As to claim 4:
The method according to claim 1, further comprising accessing the network interface controller by a plurality of virtual machines having respective virtual network interface controllers, wherein returning processed data from the accelerator comprises transmitting the processed data from one of the virtual network interface controllers to another of the virtual network interface controllers.
Hoover discloses the invention of claim 1 above. Hoover further discloses that the pipeline may operate within virtual memory, but does not disclose the use of virtual machines forming virtual NICs.
Daly discloses an analogous art, namely a NIC for processing packets including various stages of having a pipeline structure wherein one or more stages may be accelerated. Daly at FIG 1 element 140 and at ¶¶17, 19-20, 31, and 112. Daly further discloses that one or more processing function stages, including accelerated ones, in NIC 140 may be provided by way of virtual machines adapted as VNFs 110, 120, 130 etc., (virtual network interface controllers) that each manage said virtual machines. Id. at ¶¶11 and 18-20.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Hoover in such a manner, namely as to configuring the device to operate as a virtual machine. Hoover mentions operation on virtual memory, which would lead one of ordinary skill in the art to references like Daly in determining how to implement such, and Daly states that doing so increases agility and decreases cost. Daly at ¶¶9-10. Further, one of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Hoover as applied to claim 7 above, and further in view of Daly.
As to claim 8:
The method according to claim 7, wherein transmitting data to an accelerator is performed in one virtual machine, and the indication comprises an instruction to the accelerator to route the processed data to the host for use in another virtual machine.
Hoover discloses the invention of claim 7, and discloses that transmitting the data to the accelerator includes an indication to perform a specific acceleration task. Hoover at 16:66-17:10 and 18:16-21. Hoover further discloses that the pipeline may operate within virtual memory, but does not disclose the use of virtual machines forming virtual NICs.
Daly discloses an analogous art, namely a NIC for processing packets including various stages of having a pipeline structure wherein one or more stages may be accelerated. Daly at FIG 1 element 140 and at ¶¶17-20, 30, 31, and 112. Daly further discloses that one or more processing function stages, including accelerated ones, in NIC 140 may be provided by way of virtual machines adapted as VNFs 110, 120, 130 etc., (virtual network interface controllers) that each manage said virtual machines. Id. at ¶¶11 and 18-20.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Hoover in such a manner, namely as to configuring the device to operate as a virtual machine. Hoover mentions operation on virtual memory, which would lead one of ordinary skill in the art to references like Daly in determining how to implement such, and Daly states that doing so increases agility and decreases cost. Daly at ¶¶9-10. Further, one of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Hoover as applied to claim 10 above, and further in view of Daly.
As to claim 13:
The apparatus according to claim 10, wherein the network interface controller is accessible by a plurality of virtual machines having respective virtual network interface controllers that access the network interface controller, wherein receiving processed data from the accelerator further comprises transmitting the processed data from one of the virtual network interface controllers to another of the virtual network interface controllers.
Hoover discloses the invention of claim 10 above. Hoover further discloses that the pipeline may operate within virtual memory, but does not disclose the use of virtual machines forming virtual NICs.
Daly discloses an analogous art, namely a NIC for processing packets including various stages of having a pipeline structure wherein one or more stages may be accelerated. Daly at FIG 1 element 140 and at ¶¶17, 19-20, 31, and 112. Daly further discloses that one or more processing function stages, including accelerated ones, in NIC 140 may be provided by way of virtual machines adapted as VNFs 110, 120, 130 etc., (virtual network interface controllers) that each manage said virtual machines. Id. at ¶¶11 and 18-20.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Hoover in such a manner, namely as to configuring the device to operate as a virtual machine. Hoover mentions operation on virtual memory, which would lead one of ordinary skill in the art to references like Daly in determining how to implement such, and Daly states that doing so increases agility and decreases cost. Daly at ¶¶9-10. Further, one of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Hoover as applied to claim 16 above, and further in view of Daly.
As to claim 17:
The apparatus according to claim 16, wherein transmitting data to the accelerator is performed in one virtual machine, and the indication comprises an instruction to the accelerator to route the processed data to the host processor for use in another virtual machine.
Hoover discloses the invention of claim 16, and discloses that transmitting the data to the accelerator includes an indication to perform a specific acceleration task. Hoover at 16:66-17:10 and 18:16-21. Hoover further discloses that the pipeline may operate within virtual memory, but does not disclose the use of virtual machines forming virtual NICs.
Daly discloses an analogous art, namely a NIC for processing packets including various stages of having a pipeline structure wherein one or more stages may be accelerated. Daly at FIG 1 element 140 and at ¶¶17-20, 30, 31, and 112. Daly further discloses that one or more processing function stages, including accelerated ones, in NIC 140 may be provided by way of virtual machines adapted as VNFs 110, 120, 130 etc., (virtual network interface controllers) that each manage said virtual machines. Id. at ¶¶11 and 18-20.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Hoover in such a manner, namely as to configuring the device to operate as a virtual machine. Hoover mentions operation on virtual memory, which would lead one of ordinary skill in the art to references like Daly in determining how to implement such, and Daly states that doing so increases agility and decreases cost. Daly at ¶¶9-10. Further, one of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Hoover as applied to claim 23 above, and further in view of Daly.
As to claim 28:
The method of claim 23, further comprising accessing the network interface controller by a plurality of virtual machines having respective virtual network interface controllers, wherein returning the processed data from the accelerator comprises transmitting the processed data from one of the virtual network interface controllers to another of the virtual network interface controllers.
Hoover discloses the invention of claim 23 above. Hoover further discloses that the pipeline may operate within virtual memory, but does not disclose the use of virtual machines forming virtual NICs.
Daly discloses an analogous art, namely a NIC for processing packets including various stages of having a pipeline structure wherein one or more stages may be accelerated. Daly at FIG 1 element 140 and at ¶¶17, 19-20, 31, and 112. Daly further discloses that one or more processing function stages, including accelerated ones, in NIC 140 may be provided by way of virtual machines adapted as VNFs 110, 120, 130 etc., (virtual network interface controllers) that each manage said virtual machines. Id. at ¶¶11 and 18-20.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Hoover in such a manner, namely as to configuring the device to operate as a virtual machine. Hoover mentions operation on virtual memory, which would lead one of ordinary skill in the art to references like Daly in determining how to implement such, and Daly states that doing so increases agility and decreases cost. Daly at ¶¶9-10. Further, one of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Claim 33 is rejected under 35 U.S.C. 103 as being unpatentable over Hoover as applied to claim 32 above, and further in view of Daly.
As to claim 33:
The method of claim 32, wherein transmitting data to the accelerator is performed in one virtual machine, and the indication comprises an instruction to the accelerator to route the processed data to the host for use in another virtual machine.
Hoover discloses the invention of claim 32, and discloses that transmitting the data to the accelerator includes an indication to perform a specific acceleration task. Hoover at 16:66-17:10 and 18:16-21. Hoover further discloses that the pipeline may operate within virtual memory, but does not disclose the use of virtual machines forming virtual NICs.
Daly discloses an analogous art, namely a NIC for processing packets including various stages of having a pipeline structure wherein one or more stages may be accelerated. Daly at FIG 1 element 140 and at ¶¶17-20, 30, 31, and 112. Daly further discloses that one or more processing function stages, including accelerated ones, in NIC 140 may be provided by way of virtual machines adapted as VNFs 110, 120, 130 etc., (virtual network interface controllers) that each manage said virtual machines. Id. at ¶¶11 and 18-20.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Hoover in such a manner, namely as to configuring the device to operate as a virtual machine. Hoover mentions operation on virtual memory, which would lead one of ordinary skill in the art to references like Daly in determining how to implement such, and Daly states that doing so increases agility and decreases cost. Daly at ¶¶9-10. Further, one of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Claim 38 is rejected under 35 U.S.C. 103 as being unpatentable over Hoover as applied to claim 35 above, and further in view of Daly.
As to claim 38:
The network node of claim 35, wherein the network interface controller is accessible by a plurality of virtual machines having respective virtual network interface controllers that access the network interface controller, wherein the accelerator is to return the processed data from the accelerator by transmitting the processed data from one of the virtual network interface controllers to another of the virtual network interface controllers.
Hoover discloses the invention of claim 35 above. Hoover further discloses that the pipeline may operate within virtual memory, but does not disclose the use of virtual machines forming virtual NICs.
Daly discloses an analogous art, namely a NIC for processing packets including various stages of having a pipeline structure wherein one or more stages may be accelerated. Daly at FIG 1 element 140 and at ¶¶17, 19-20, 31, and 112. Daly further discloses that one or more processing function stages, including accelerated ones, in NIC 140 may be provided by way of virtual machines adapted as VNFs 110, 120, 130 etc., (virtual network interface controllers) that each manage said virtual machines. Id. at ¶¶11 and 18-20.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Hoover in such a manner, namely as to configuring the device to operate as a virtual machine. Hoover mentions operation on virtual memory, which would lead one of ordinary skill in the art to references like Daly in determining how to implement such, and Daly states that doing so increases agility and decreases cost. Daly at ¶¶9-10. Further, one of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Claim 42 is rejected under 35 U.S.C. 103 as being unpatentable over Hoover as applied to claim 41 above, and further in view of Daly.
As to claim 42:
The network node of claim 41, wherein the data is transmitted to the accelerator by one virtual machine, and the indication comprises an instruction to the accelerator to route the processed data to the host processor for use in another virtual machine.
Hoover discloses the invention of claim 41 above. Hoover further discloses that transmitting the data to the accelerator includes an indication to perform a specific acceleration task. Hoover at 16:66-17:10 and 18:16-21. Hoover also discloses that the pipeline may operate within virtual memory, but does not disclose the use of virtual machines.
Daly discloses an analogous art, namely a NIC for processing packets including various stages of having a pipeline structure wherein one or more stages may be accelerated. Daly at FIG 1 element 140 and at ¶¶17, 19-20, 31, and 112. Daly further discloses that one or more processing function stages, including accelerated ones, in NIC 140 may be provided by way of virtual machines adapted as VNFs 110, 120, 130 etc., (virtual network interface controllers) that each manage said virtual machines. Id. at ¶¶11 and 18-20. Daly further describes the virtual machines of claim 32 above as routing data to various stages, including an acceleration stage, and further routing to additional machines (reads instruction). Daly at ¶¶18-19 and 30.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Hoover in such a manner, namely as to configuring the device to operate as a virtual machine. Hoover mentions operation on virtual memory, which would lead one of ordinary skill in the art to references like Daly in determining how to implement such, and Daly states that doing so increases agility and decreases cost. Daly at ¶¶9-10. Further, one of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Claims 6 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Hoover as applied to claim 1 above, and further in view of U.S. Pat. PGPUB 2016/0330301A1 to Raindel et al. (“Raindel”).
As to claim 6:
The method according to claim 1, wherein the one acceleration task is a decryption of a portion of the packet, and the other acceleration task is an acceleration of the decrypted portion of the packet.
Hoover discloses the invention of claim 1 above. Hoover fails to disclose that an acceleration task is a decryption of a portion of the packet.
Raindel discloses an analogous art, namely a processing system for packets in a system 20 including a NIC 32 as well as an acceleration stage 26 that packets can be forwarded to for acceleration tasks. Raindel at FIG 1 and at ¶¶41-44. Raindel further discloses that an acceleration task may include decrypting packets. Id. at ¶¶34, 36, and 43.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Hoover in such a manner, namely as to configuring the acceleration tasks to include decryption of packets. One of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
As Hoover discloses multiple accelerator tasks in the pipeline, one of ordinary skill in the art would have understood that the first accelerator task may be decryption of the packet or a portion thereof, and the second accelerator task in the pipeline may be an acceleration task on the decrypted packet data.
As to claim 9:
The method according to claim 1, wherein routing the packet toward a destination comprises routing the packet to the communications network while avoiding transmitting the packet to the host.
Hoover discloses the invention of claim 1 above. Hoover fails to disclose routing the packet to a communications network while avoiding transmitting the packet to the host.
Raindel discloses an analogous art, namely a processing system for packets in a system 20 including a NIC 32 as well as an acceleration stage 26 that packets can be forwarded to for acceleration tasks. Raindel at FIG 1 and at ¶¶41-44. Raindel further discloses that an acceleration task may include encrypting packets to be transmitted to the network by way of connection 38 which avoids the host computer. Id. and further at FIG 6 and ¶¶54 and 65-71.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Hoover in such a manner, namely as to configuring the acceleration tasks to avoid the host. One of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Claims 15 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Hoover as applied to claim 10 above, and further in view of Raindel.
As to claim 15:
The apparatus according to claim 10, wherein the one acceleration task is a decryption of a portion of the packet, and the other acceleration task is an acceleration of the decrypted portion of the packet.
Hoover discloses the invention of claim 10 above. Hoover fails to disclose that an acceleration task is a decryption of a portion of the packet.
Raindel discloses an analogous art, namely a processing system for packets in a system 20 including a NIC 32 as well as an acceleration stage 26 that packets can be forwarded to for acceleration tasks. Raindel at FIG 1 and at ¶¶41-44. Raindel further discloses that an acceleration task may include decrypting packets. Id. at ¶¶34, 36, and 43.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Hoover in such a manner, namely as to configuring the acceleration tasks to include decryption of packets. One of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
As Hoover discloses multiple accelerator tasks in the pipeline, one of ordinary skill in the art would have understood that the first accelerator task may be decryption of the packet or a portion thereof, and the second accelerator task in the pipeline may be an acceleration task on the decrypted packet data.
As to claim 18:
The apparatus according to claim 10, wherein routing the packet toward a destination comprises routing the packet to the communications network while avoiding transmitting the packet to the host processor.
Hoover discloses the invention of claim 10 above. Hoover fails to disclose routing the packet to a communications network while avoiding transmitting the packet to the host.
Raindel discloses an analogous art, namely a processing system for packets in a system 20 including a NIC 32 as well as an acceleration stage 26 that packets can be forwarded to for acceleration tasks. Raindel at FIG 1 and at ¶¶41-44. Raindel further discloses that an acceleration task may include encrypting packets to be transmitted to the network by way of connection 38 which avoids the host computer. Id. and further at FIG 6 and ¶¶54 and 65-71.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Hoover in such a manner, namely as to configuring the acceleration tasks to avoid the host. One of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Claims 30 and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Hoover as applied to claim 23 above, and further in view of Raindel.
As to claim 30:
The method of claim 23, wherein the acceleration task is a decryption of a portion of the packet.
Hoover discloses the invention of claim 23 above. Hoover fails to disclose that the acceleration task is a decryption of a portion of the packet.
Raindel discloses an analogous art, namely a processing system for packets in a system 20 including a NIC 32 as well as an acceleration stage 26 that packets can be forwarded to for acceleration tasks. Raindel at FIG 1 and at ¶¶41-44. Raindel further discloses that an acceleration task may include decrypting packets. Id. at ¶¶34, 36, and 43.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Hoover in such a manner, namely as to configuring the acceleration tasks to include decryption of packets. One of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Further as to claim 31:
The method of claim 30, wherein processing the packet further comprises: transmitting additional data to the accelerator from the electrical circuitry, the additional data being associated with another one of the plurality of stages requiring acceleration; and
performing another acceleration task on the additional data in the accelerator, wherein the acceleration task is a decryption of a portion of the packet, and the other acceleration task is an acceleration of the decrypted portion of the packet.
As noted above as to claim 30, Hoover in view of Raindel discloses performing an accelerator task that includes decrypting a packet, and as noted above as to claim 23, Hoover discloses multiple accelerator tasks in the pipeline. Thus one of ordinary skill in the art would have understood that the first accelerator task may be decryption of the packet or a portion thereof, and the second accelerator task in the pipeline may be an acceleration task on the decrypted packet data.
Claim 34 is rejected under 35 U.S.C. 103 as being unpatentable over Hoover as applied to claim 23 above, and further in view of Raindel.
As to claim 34:
The method of claim 23, wherein routing the packet toward the destination comprises routing the packet to the communications network while avoiding transmitting the packet to the host.
Hoover discloses the invention of claim 23 above. Hoover fails to disclose routing the packet to a communications network while avoiding transmitting the packet to the host.
Raindel discloses an analogous art, namely a processing system for packets in a system 20 including a NIC 32 as well as an acceleration stage 26 that packets can be forwarded to for acceleration tasks. Raindel at FIG 1 and at ¶¶41-44. Raindel further discloses that an acceleration task may include encrypting packets to be transmitted to the network by way of connection 38 which avoids the host computer. Id. and further at FIG 6 and ¶¶54 and 65-71.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Hoover in such a manner, namely as to configuring the acceleration tasks to avoid the host. One of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Claim 40 is rejected under 35 U.S.C. 103 as being unpatentable over Hoover as applied to claim 36 above, and further in view of Raindel.
As to claim 40:
The network node of claim 36, wherein the acceleration task is a decryption of a portion of the packet, and the other acceleration task is an acceleration of the decrypted portion of the packet.
Hoover discloses the invention of claim 36 above. Hoover fails to disclose that an acceleration task is a decryption of a portion of the packet.
Raindel discloses an analogous art, namely a processing system for packets in a system 20 including a NIC 32 as well as an acceleration stage 26 that packets can be forwarded to for acceleration tasks. Raindel at FIG 1 and at ¶¶41-44. Raindel further discloses that an acceleration task may include decrypting packets. Id. at ¶¶34, 36, and 43.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Hoover in such a manner, namely as to configuring the acceleration tasks to include decryption of packets. One of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
As Hoover discloses multiple accelerator tasks in the pipeline, one of ordinary skill in the art would have understood that the first accelerator task may be decryption of the packet or a portion thereof, and the second accelerator task in the pipeline may be an acceleration task on the decrypted packet data.
Claim 43 is rejected under 35 U.S.C. 103 as being unpatentable over Hoover as applied to claim 35 above, and further in view of Raindel.
As to claim 43:
The network node of claim 35, wherein the packet is routed toward the destination by routing the packet to the communications network while avoiding transmitting the packet to the host processor.
Hoover discloses the invention of claim 23 above. Hoover fails to disclose routing the packet to a communications network while avoiding transmitting the packet to the host.
Raindel discloses an analogous art, namely a processing system for packets in a system 20 including a NIC 32 as well as an acceleration stage 26 that packets can be forwarded to for acceleration tasks. Raindel at FIG 1 and at ¶¶41-44. Raindel further discloses that an acceleration task may include encrypting packets to be transmitted to the network by way of connection 38 which avoids the host computer. Id. and further at FIG 6 and ¶¶54 and 65-71.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Hoover in such a manner, namely as to configuring the acceleration tasks to avoid the host. One of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Claim 45 is rejected under 35 U.S.C. 103 as being unpatentable over Hoover as applied to claim 44 above, and further in view of Raindel.
As to claim 45:
The computing system of claim 44, wherein the one acceleration task is a decryption of a portion of the packet, and the other acceleration task is an acceleration of the decrypted portion of the packet.
Hoover discloses the invention of claim 44 above. Hoover fails to disclose that an acceleration task is a decryption of a portion of the packet.
Raindel discloses an analogous art, namely a processing system for packets in a system 20 including a NIC 32 as well as an acceleration stage 26 that packets can be forwarded to for acceleration tasks. Raindel at FIG 1 and at ¶¶41-44. Raindel further discloses that an acceleration task may include decrypting packets. Id. at ¶¶34, 36, and 43.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Hoover in such a manner, namely as to configuring the acceleration tasks to include decryption of packets. One of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
As Hoover discloses multiple accelerator tasks in the pipeline, one of ordinary skill in the art would have understood that the first accelerator task may be decryption of the packet or a portion thereof, and the second accelerator task in the pipeline may be an acceleration task on the decrypted packet data.
Response to Arguments
Applicant provides arguments in his response (“Remarks”).
As to the previous rejection under Double Patenting (Remarks at 16), the Examiner upholds the rejection and the rejection will not be held in abeyance. MPEP § 804 I. B. 1.
As to the Patent Owner’s arguments towards rejections under §102(a)(1) (Remarks at 18-20), the Examiner notes that the previous rejection was under §103 and arguments towards a lack of anticipation by the Hoover reference are not persuasive. However, the Examiner finds Patent Owner’s arguments towards Hoover to be not persuasive under either statute.
As to the returning of a status and acceleration tasks based thereon (the primary focus of Patent Owner’s arguments), the Examiner notes that the Office action cites to at least 15:32-48 of Hoover. This portion of Hoover clearly discloses the determination of a status of a task and performing of subsequent tasks based thereon, stating:
In the pipeline of FIG. 5, for example, where a computer software application (500) is segmented into stages, the stages are load balanced with a number of instances of each stage in dependence upon the performance of the stages. Such load balancing can be carried out, for example, by monitoring the performance of the stages and instantiating a number of instances of each stage in dependence upon the performance of one or more of the stages. Monitoring the performance of the stages can be carried out by configuring each stage to report performance statistics to a monitoring application (640) that in turn is installed and running on another thread of execution on an IP block or host interface processor. Performance statistics can include, for example, time required to complete a data processing task, a number of data processing tasks completed within a particular time period, and so on, as will occur to those of skill in the art.”
Note further Id. at 15:49-60, which further states that “[i]nstantiating a number of instances of each stage in dependence upon the performance of one or more of the stages can be carried out by instantiating, by a host interface processor (105), a new instance of a stage when monitored performance indicates a need for a new instance.”
As to the stages being accelerated stages, Hoover is cited at, among others, 15:61-65 which states that the instances listed above may be accelerated stages. Note also id. at 16:19-23, cited in the rejection, which states that any instance may be an accelerated one.
Note that Hoover discloses as an example an accelerated instance 608 followed by a non-accelerated instance 610. Hoover at FIG 5. Hoover also states that any of the other instances (including 610) may also be accelerated, and that the sending of the data to this further accelerated instance is performed outside of the accelerator, which in the modified invention of Hoover in the rejection above is in the NIC. Id. at 14:52-66. This, given the above teachings, means that in Hoover an accelerated instance may, based on the status of the work produced by the accelerated instance, be further routed to another accelerated instance by the NIC.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Charles Craver whose telephone number is (571) 272-7849. The Examiner can normally be reached on Monday - Friday 8:30-5:30 PT Pacific Time.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Andrew J. Fischer can be reached on 571-272-6779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Signed,
/CHARLES R CRAVER/Reexamination Specialist, Art Unit 3992
Conferees:
/ROBERT J HANCE/Primary Examiner, Art Unit 3992
/M.F/Supervisory Patent Examiner, Art Unit 3992
1 Olsen has a conference date of December 5-9, 2015, but it was added to IEEE Xplore February 16, 2017. See https://ieeexplore.ieee.org/document/7856620.
Prosecution Insights