FINAL REJECTION
This Office action is responsive to the amendment filed December 8, 2025 (“Amendment”).
The instant 17/989,587 application is a reissue application of U.S. Pat. 10,841,243 B2 to Levi et al. (“the ‘243 Patent”), which issued November 17, 2020 from U.S. Pat. App. Ser. No. 16/012,826, filed June 20, 2018, with a domestic priority claim to U.S. Provisional Pat. App. Ser. No. 62,582,997 filed November 8, 2017.
The Examiner has deemed the ‘243 Patent to have an earliest possible effective filing date of November 8, 2017.
Claims 1-22 were originally pending in this application. By way of a preliminary amendment filed with the application, claims 23-43 are added. By way of the Amendment, claims 1-22 are canceled. Thus claims 23-43 are pending.
This action is Final.
Reissue
The Examiner has determined that there are no other continuations, reissues, reexaminations, inter partes reviews, or other AIA trials or appeals currently pending with respect to the ‘243 Patent. A litigation search has determined there to be no pending litigation as to the ‘288 Patent.
Applicant is reminded of the continuing obligation under 37 CFR 1.178(b) to timely apprise the Office of any prior or concurrent proceeding in which Patent No. 10,841,243 is or was involved. These proceedings would include interferences, reissues, reexaminations, and litigation. Applicant is further reminded of the continuing obligation under 37 CFR 1.56, to timely apprise the Office of any information which is material to patentability of the claims under consideration in this reissue application. These obligations rest with each individual associated with the filing and prosecution of this application for reissue. See also MPEP §§ 1404, 1442.01 and 1442.04.
Because the instant ‘243 Patent is deemed not to contain claims having an effective date prior to March 16, 2013, the America Invents Act First Inventor to File (“AIA -FITF”) provisions apply, rather than the pre-AIA provisions. See 35 U.S.C. § 100 (note) and 35 U.S.C. § 100 (pre-AIA ). In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of any statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Reissue Amendment
The Amendment filed December 8, 2025 is objected to because of the following:
New claims 23-43 are not underlined in their entirety, which does not meet 37 CFR 1.173(b)(2) and (d)(2). Please see MPEP § 1453 V. for examples of adding new claims in reissue applications.
Further, the amendment to the specification does not amend the first sentence of the specification to state that more than one reissue application has been filed and identify each of the reissue applications by relationship, application number and filing date as per 37 CFR 1.177. The amendment includes this information but not in the first sentence of the disclosure.
A supplemental paper correctly amending the reissue application is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when § 112(f) is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under § 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with § 112(f). The presumption that the claim limitation is interpreted under § 112(f), is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with § 112(f). The presumption that the claim limitation is not interpreted under § 112(f), is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under § 112(f), except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under § 112(f), except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under § 112(f), because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
In claims 31, and 39 “[a] network interface controller … configured for/is to: receive/receiving a packet”;
In claims 31 and 39, “[a] network interface controller … is configured to/is to: store the packet in a buffer”;
In claims 31 and 39, “an accelerator … configured to: perform a second task on the packet”;
In claims 31 and 39, “[a] network interface controller … is configured to/is to: perform a first task on the packet in a first stage of the packet processing pipeline, wherein the first task is a network processing task”;
In claims 31 and 39, “[a] network interface controller … is configured to/is to: offload a second task on the packet from the packet processing pipeline to the hardware accelerator;”;
In claims 31 and 39, “[a] network interface controller … is configured to/is to: perform a third task on the packet in a second stage of the packet processing pipeline after the first stage”;
In claims 31 and 39, “[a] network interface controller … is configured to/is to: route at least a portion of the packet to a destination after processing the packet in the packet processing pipeline”;
In claims 37 and 42, “[a] network interface controller … is to route the packet to the host via the host interface”;
In all of these cases, the NIC and accelerator are performing a function of a computing means. The NIC is stated as operating by way of software while the accelerator is preferred to be a FPGA but may also be a GPU. ‘243 Patent at 2:20, 2:52-54, 5:50-51, and 6:55-60.
Under the three-pronged approach above, it is thus determined by the Examiner that 1) the claims use a term used as a substitute for “means” for performing the claimed function; 2) the term is modified by the functional language; and 3) the term is not modified by sufficient structure for performing the claimed function.
Specifically as to prong 3) above, in this particular case the limitations recite “function without reciting sufficient structure for performing that function.” Williamson v. Citrix Online, LLC, 792 F.3d 1339, 1349 (Fed. Cir. 2015) (en banc) (quoting Watts v. XL Systems, Inc., 232 F.3d 877, 880 (Fed. Cir. 2000); see also Personalized Media Communications, LLC v. International Trade Commission, 161 F. 3d 696, 704 (Fed. Cir. 1998). Here the function is one that may be performed by a general-purpose processor and § 112(f) applies as further described below.
For a computer-implemented § 112(f) claim limitation, the specification must disclose an algorithm for performing the claimed specific computer function, or else the claim is indefinite. See Net MoneyIN, Inc. v. Verisign. Inc., 545 F.3d 1359, 1367 (Fed. Cir. 2008). See also In re Aoyama, 656 F.3d 1293, 1297, 99 USPQ2d 1936, 1939 (Fed. Cir. 2011) ("[W]hen the disclosed structure is a computer programmed to carry out an algorithm, ‘the disclosed structure is not the general purpose computer, but rather that special purpose computer programmed to perform the disclosed algorithm.’") (quoting WMS Gaming, Inc. v. Int’l Game Tech., 184 F.3d 1339, 1349, 51 USPQ2d 1385, 1391 (Fed. Cir. 1999)).
To claim a means for performing a specific computer-implemented function and then to disclose only a general purpose computer as the structure designed to perform that function amounts to pure functional claiming. In Aristocrat Techs. Australia PTY Ltd. v. Int’l Game Tech., 521 F.3d 1328, 1336-37, 86 USPQ2d 1235, 1242 (Fed. Cir. 2008). In this instance, the structure corresponding to a § 112(f) claim limitation for a computer-implemented function must include the algorithm needed to transform the general purpose computer or microprocessor disclosed in the specification. Aristocrat, 521 F.3d at 1333, 86 USPQ2d at 1239; Finisar Corp. v. DirecTV Group, Inc., 523 F.3d 1323, 1340, 86 USPQ2d 1609, 1623 (Fed. Cir. 2008); WMS Gaming, Inc. v. Int’l Game Tech., 184 F.3d 1339, 1349, 51 USPQ2d 1385, 1391 (Fed. Cir. 1999). The corresponding structure is not simply a general purpose computer by itself but the special purpose computer as programmed to perform the disclosed algorithm. Aristocrat, 521 F.3d at 1333, 86 USPQ2d at 1239. Thus, the specification must sufficiently disclose an algorithm to transform a general purpose microprocessor to the special purpose computer. See Aristocrat, 521 F.3d at 1338, 86 USPQ2d at 1241. ("Aristocrat was not required to produce a listing of source code or a highly detailed description of the algorithm to be used to achieve the claimed functions in order to satisfy § 112(f). It was required, however, to at least disclose the algorithm that transforms the general purpose microprocessor to a ‘special purpose computer programmed to perform the disclosed algorithm.’" (quoting WMS Gaming, 184 F.3d at 1349, 51 USPQ2d at 1391.)) An algorithm is defined, for example, as "a finite sequence of steps for solving a logical or mathematical problem or performing a task." Microsoft Computer Dictionary, Microsoft Press, 5th edition, 2002. Applicant may express the algorithm in any understandable terms including as a mathematical formula, in prose, in a flow chart, or "in any other manner that provides sufficient structure." Finisar, 523 F.3d at 1340, 86 USPQ2d at 1623; see also Intel Corp. v. VIA Techs., Inc., 319 F.3d 1357, 1366, 65 USPQ2d 1934, 1941 (Fed. Cir. 2003); In re Dossel, 115 F.3d 942, 946-47, 42 USPQ2d 1881, 1885 (Fed. Cir.1997); Typhoon Touch Inc. v. Dell Inc., 659 F.3d 1376, 1385, 100 USPQ2d 1690, 1697 (Fed. Cir. 2011); In re Aoyama, 656 F.3d at 1306, 99 USPQ2d at 1945.
Thus the Examiner looks to the disclosure to construe the claim limitations to cover the corresponding structure described therein and equivalents thereof.
As to element 1 above, looking to the specification, as noted above the NIC is stated as operating by way of software. The description of the claimed function of receiving a packet is disclosed in 10:10-13, which describes the NIC receiving a packet from a network or host at step 1 in FIGS 7-12. This is the algorithm that, along with the general processor, comprises the structure in the claim.
As to element 2 above, looking to the specification, as noted above the NIC is stated as operating by way of software. The description of the claimed function of processing the packet in the packet processing pipeline by storing the packet in a buffer is disclosed in 6:10-14 which describes a NIC which performs a processing step of receiving the packet from either the network or the host and storing it in a buffer 60/64. This is the algorithm that, along with the general processor, comprises the structure in the claim.
As to element 3 above, looking to the specification, as noted above the accelerator is preferred to be a FPGA but may also be a GPU. The description of the claimed function of performing an acceleration task in the accelerator is described in 9:17-20, which describes the accelerator performing the specified acceleration task from the NIC. This is the algorithm that, along with the general processor, comprises the structure in the claim.
As to element 4 above, looking to the specification, as noted above the NIC is stated as operating by way of software. The description of the claimed function of performing a first task on the packet in a first stage of the packet processing pipeline, wherein the first task is a network processing task is described in 7:2-18, which describes a first non-accelerated stage 84 in the NIC. This is the algorithm that, along with the general processor, comprises the structure in the claim.
As to element 5 above, looking to the specification, as noted above the NIC is stated as operating by way of software. The description of the claimed function of offload a second task on the packet from the packet processing pipeline to the hardware accelerator is described in 10:10-15, which describes the NIC transmitting the packets over interface 162 or 164 to the accelerator. This is the algorithm that, along with the general processor, comprises the structure in the claim.
As to element 6 above, looking to the specification, as noted above the NIC is stated as operating by way of software. The description of the claimed function of perform a third task on the packet in a second stage of the packet processing pipeline after the first stage is described in 7:23-24, which describes the NIC receiving the packet from the accelerator and performing its own additional stage of processing 82. This is the algorithm that, along with the general processor, comprises the structure in the claim.
As to element 7 above, looking to the specification, as noted above the NIC is stated as operating by way of software. The description of the claimed function of routing at least a portion of the packet to a destination after processing the packet in the packet processing pipeline is described in 7:23-30, which describes the NIC, after receiving a packet from the accelerator and performing another step, forwarding the packet for disposition. This is the algorithm that, along with the general processor, comprises the structure in the claim.
As to element 8 above, looking to the specification, as noted above the NIC is stated as operating by way of software. The description of the claimed function of routing the packet to the host via the host interface is described in FIG 5 step 138 and 9:32-35, which describes the packet being forwarded to the host via . This is the algorithm that, along with the general processor, comprises the structure in the claim.
Because this/these claim limitation(s) is/are being interpreted under § 112(f), it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under § 112(f), applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under § 112(f) (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under § 112(f).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 23, 31, 33, and 39 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 23, 44, and 46 of copending Application No. 17/989,587 in view of U.S. Pat. 8,726,295 B2 to Hoover et al. (“Hoover”). Although the claims at issue are not identical, they are not patentably distinct from each other. This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
As to instant claim 23, it and reference claim 23 are compared below:
Reference ‘587 application claim 23:
23. (New) A method of communication, comprising:
receiving a packet in a network interface controller that is connected to a host and a communications network, the network interface controller comprising electrical circuitry configured as a packet processing pipeline having a plurality of stages, wherein at least one of the plurality of stages requires acceleration;
processing the packet in the packet processing pipeline, wherein processing the packet comprises:
performing a task on data in at least one of the plurality of stages in the packet processing pipeline;
transmitting data to an accelerator from the electrical circuitry, the transmitted data being associated with the at least one of the plurality of stages requiring acceleration;
performing an acceleration task on the transmitted data in a configurable unit of the accelerator;
returning processed data and a status of the acceleration task from the accelerator to the electrical circuitry, the processing data being associated with the at least one of the plurality of stages requiring acceleration; and
based on the status, receiving the processed data from the electrical circuitry and performing a subsequent acceleration task in the configurable unit of the accelerator; and
after processing the packet in the packet processing pipeline, routing the packet toward a destination.
Instant ‘590 application claim 23:
23. (New) A method comprising:
receiving a packet by an integrated circuit having electrical circuitry configured as a packet processing pipeline having a plurality of stages, wherein the integrated circuit is coupled to a host via a host interface and a network via a network interface;
storing the packet in a buffer;
performing a first task on the packet in a first stage of the packet processing pipeline, wherein the first task is a network processing task;
offloading a second task on the packet from the packet processing pipeline to a hardware accelerator coupled to the packet processing pipeline;
performing the second task on the packet by a configurable unit of the hardware accelerator;
performing a third task on the packet in a second stage of the packet processing pipeline after the first stage by the packet processing pipeline;
responsive to a status, performing a fourth task on the packet by the configurable unit of the hardware accelerator; and
routing the packet toward a destination after processing the packet in the packet processing pipeline.
The instant claim requires storing the packet in a buffer and performing a third task in the pipeline.
To that end, Hoover discloses an analogous art, namely software or hardware acceleration by way of an accelerator as a stage in a multi-stage processor pipeline. Hoover at FIGS 4 and 5 and at 3:8-13, 11:21-37, 13:33-61, and 15:61-65. Hoover discloses buffering the packet and also performing a third task on a packet after a first NIC task and an acceleration task. Id. at FIGS 3 and 5 and at 10:24-50.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to utilize such in the instant claim, as one of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Further as to integrating the pipeline into the NIC itself instead of the IP Block connected to the NIC, Hoover does, however, refer to the NIC connected to the IP Block as “its [the IP Block’s] network interface controller”. Id. at 8:23-27. For this reason, it would have been obvious to one of ordinary skill in the art to combine the two elements such that the IP Block processor is in the NIC. This is based on the well-known obviousness rationale of making integral. MPEP § 2144.04 V. B., citing In re Larson, 340 F.2d 965, 968, 144 USPQ 347, 349 (CCPA 1965). Further, one of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
As to instant claim 31, it and reference claim 44 are compared below:
Instant ‘587 application claim 44:
44. (New) A computing system comprising:
a network interface controller coupled to a host processor and to a communications network, the network interface controller comprising electrical circuitry configured as a packet processing pipeline having a plurality of stages, wherein at least one of the plurality of stages requires acceleration;
an accelerator coupled to the network interface controller, wherein:
the network interface controller is configured to:
receive a packet; and
process the packet in the packet processing pipeline by:
performing a task on data in at least one of the plurality of stages in the packet processing pipeline; and
transmitting data to the accelerator from the electrical circuitry, the transmitted data being associated with the at least one of the plurality of stages requiring acceleration;
the accelerator is configured to:
perform an acceleration task on the transmitted data in a configurable unit of the accelerator;
return processed data and a status of the acceleration task from the accelerator to the electrical circuitry, the processed data being associated with the at least one of the plurality of stages requiring acceleration; and
based on the status, receiving the processed data from the electrical circuitry and performing a subsequent acceleration task in the configurable unit of the accelerator,
wherein the network interface controller is further configured to route the packet toward a destination after processing the packet in the packet processing pipeline.
Reference ‘590 application claim 31:
31. (New) A computing system comprising:
a network interface controller (NIC) to implement a packet processing pipeline having a plurality of stages, the NIC comprising a host interface coupled to a host and a network interface coupled to a network; and
a hardware accelerator coupled to the NIC, wherein:
the NIC is to:
receive a packet;
store the packet in a buffer;
perform a first task on the packet in a first stage of the packet processing pipeline, wherein the first task is a network processing task;
offload a second task on the packet from the packet processing pipeline to the hardware accelerator; and
perform a third task on the packet in a second stage of the packet processing pipeline after the first stage;
responsive to a status, offload a fourth task on the packet from the packet processing pipeline to the hardware accelerator; and
route the packet toward a destination after processing the packet in the packet processing pipeline; and
the hardware accelerator is to:
perform the second task on the packet at a configurable unit of the hardware accelerator; and
perform the fourth task on the packet at the configurable unit of the hardware accelerator.
The instant claim requires storing the packet in a buffer and performing a third task in the pipeline.
To that end, Hoover discloses an analogous art, namely software or hardware acceleration by way of an accelerator as a stage in a multi-stage processor pipeline. Hoover at FIGS 4 and 5 and at 3:8-13, 11:21-37, 13:33-61, and 15:61-65. Hoover discloses buffering the packet and also performing a third task on a packet after a first NIC task and an acceleration task. Id. at FIGS 3 and 5 and at 10:24-50.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to utilize such in the instant claim, as one of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Further as to integrating the pipeline into the NIC itself instead of the IP Block connected to the NIC, Hoover does, however, refer to the NIC connected to the IP Block as “its [the IP Block’s] network interface controller”. Id. at 8:23-27. For this reason, it would have been obvious to one of ordinary skill in the art to combine the two elements such that the IP Block processor is in the NIC. This is based on the well-known obviousness rationale of making integral. MPEP § 2144.04 V. B., citing In re Larson, 340 F.2d 965, 968, 144 USPQ 347, 349 (CCPA 1965). Further, one of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Claim 33 corresponds to reference claim 46.
As to instant claim 39, it and reference claim 46 are compared below:
Reference ‘587 application claim 46:
46. (New) A computing system comprising:
a network interface controller coupled to a host processor and to a communications network, the network interface controller comprising electrical circuitry configured as a packet processing pipeline having a plurality of stages, wherein at least one of the plurality of stages requires acceleration;
an accelerator coupled to the network interface controller, wherein:
the network interface controller is configured to:
receive a packet; and
process the packet in the packet processing pipeline by:
performing a task on data in at least one of the plurality of stages in the packet processing pipeline; and
transmitting data to the accelerator from the electrical circuitry, the transmitted data being associated with the at least one of the plurality of stages requiring acceleration;
the accelerator is configured to:
perform an acceleration task on the transmitted data in a configurable unit of the accelerator;
return processed data and a status of the acceleration task from the accelerator to the electrical circuitry, the processed data being associated with the at least one of the plurality of stages requiring acceleration; and
based on the status, receiving the processed data from the electrical circuitry and performing a subsequent acceleration task in the configurable unit of the accelerator,
wherein the network interface controller is further configured to route the packet toward a destination after processing the packet in the packet processing pipeline
wherein the network interface controller and the accelerator are integrated in an integrated circuit.
Instant ‘590 application claim 39:
39. (New) An integrated circuit comprising:
a first port coupled to a network interface;
a second port coupled to a host interface;
a network interface controller (NIC) comprising electrical circuitry configured as a packet processing pipeline having a plurality of stages; and
a hardware accelerator coupled to the packet processing pipeline, wherein:
the NIC is configured to:
receive a packet;
store the packet in a buffer;
perform a first task on the packet in a first stage of the packet processing pipeline, wherein the first task is a network processing task;
and
offload a second task on the packet from the packet processing pipeline to a configurable unit of the hardware accelerator;
the hardware accelerator is configured to perform the second task on the packet; and
the NIC is further configured to:
perform a third task on the packet in a second stage of the packet processing pipeline after the first stage;
responsive to a status, offload a fourth task on the packet from the packet processing pipeline to the configurable unit of the hardware accelerator; and
route at least a portion of the packet to a destination after processing the packet in the packet processing pipeline.
The instant claim requires storing the packet in a buffer and performing a third task in the pipeline as well as ports.
To that end, Hoover discloses an analogous art, namely software or hardware acceleration by way of an accelerator as a stage in a multi-stage processor pipeline. Hoover at FIGS 4 and 5 and at 3:8-13, 11:21-37, 13:33-61, and 15:61-65. Hoover discloses buffering the packet and also performing a third task on a packet after a first NIC task and an acceleration task. Id. at FIGS 3 and 5 and at 10:24-50. Hoover also discloses ports connecting to a host and a network. Id. at FIGS 1 and 2.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to utilize such in the instant claim, as one of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Further as to integrating the pipeline into the NIC itself instead of the IP Block connected to the NIC, Hoover does, however, refer to the NIC connected to the IP Block as “its [the IP Block’s] network interface controller”. Id. at 8:23-27. For this reason, it would have been obvious to one of ordinary skill in the art to combine the two elements such that the IP Block processor is in the NIC. This is based on the well-known obviousness rationale of making integral. MPEP § 2144.04 V. B., citing In re Larson, 340 F.2d 965, 968, 144 USPQ 347, 349 (CCPA 1965). Further, one of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 23, 27, 28, and 30 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Pat. 8,726,295 B2 to Hoover et al. (“Hoover”).
As to claim 23, Hoover discloses:
A method comprising:
receiving a packet by an integrated circuit having electrical circuitry configured as a packet processing pipeline having a plurality of stages, wherein the integrated circuit is coupled to a host via a host interface and a network via a network interface;
Hoover discloses a method of communication comprising receiving a packet in a circuit 100 connected to a host and communications network. Hoover at FIGS 2 and 3, elements 108 and 152 and at 3:52-55. The system further includes a processor 126 (electrical circuitry) running a packet processing pipeline having multiple stages, including at least one acceleration stage. Id. at FIGS 4 and 5 and at 11:21-37, 13:33-61, and 15:61-65. The system is connected to a NIC (element 122) connected to a network and also to a host by way of a host interface 105. Id. at FIG 5.
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Hoover FIG 5 (excerpt).
storing the packet in a buffer;
performing a first task on the packet in a first stage of the packet processing pipeline, wherein the first task is a network processing task;
offloading a second task on the packet from the packet processing pipeline to a hardware accelerator coupled to the packet processing pipeline;
performing the second task on the packet by a configurable unit of the hardware accelerator;
Hoover discloses processing the packet in the pipeline includes storing the packet in a buffer. Hoover at 10:24-50. Hoover further discloses performing a network processing task on data in one of the stages and transmitting data associated with a stage requiring acceleration to an accelerator where an acceleration task is performed. Id. at FIG 5 and at 14:52-15:9; note that the accelerator may be part of any stage, such as in stage 2, which means processing occurs first in stage 1 followed by accelerated processing. Id. at 16:17-17:10. This reads as offloading.
Note further that while the accelerator is primarily disclosed as software, “readers of skill in the art will immediately recognize that an I/O accelerator may also be implemented as hardware aggregation of sequential and non-sequential logic separate from the processor (126) in the IP block (104) where the I/O accelerator has its own processor and is adapted to the network through a low latency, high bandwidth application messaging interconnect (107).” Id. at 16:56-65. This means the processor circuit including the pipeline necessarily forwards the data to the accelerator processor by way of the disclosed connection. Id.
Hoover discloses that the processing stage units are configurable. Hoover at 13:36-47.
performing a third task on the packet in a second stage of the packet processing pipeline after the first stage by the packet processing pipeline;
Hoover discloses the data associated with the stage requiring acceleration, after passing through the accelerator, returning to the processing pipeline in the circuitry (processor). Hoover at 14:17-15:9. Hoover discloses further stages in the pipeline such as stages 2 and 3. Id. at FIGS 4 and 5 and at 11:21-37, 13:33-61, and 15:61-65.
responsive to a status, performing a fourth task on the packet by the configurable unit of the hardware accelerator; and
Hoover discloses reporting a status of a stage processor task to monitor application 640. Hoover at 15:32-48. As such may change the instances of a subsequent stage which may include an accelerated one, this reads on performing another accelerated task responsive to the status. Note Hoover states there may be additional stages i.e. a fourth stage and that it may include an accelerated task in the same manner as the earlier-described offloading. Id. at 14:35-51, stating “Many pipelines according to embodiments of the present invention, however, may include[] many stages and many instances of stages”. Hoover also states that any of the other instances (including 610) may also be accelerated, and that the sending of the data to this further accelerated instance is performed outside of the accelerator, which in the modified invention of Hoover in the rejection above is in the NIC. Id. at 14:52-66.
routing the packet toward a destination after processing the packet in the packet processing pipeline.
Hoover discloses that, after the packet is processed in the pipeline, it is routed toward a destination. Hoover at 9:65-66 and 14:17-51.
Further as to claim 27:
The method of claim 23, wherein routing the packet toward the destination comprises routing the packet to the host via the host interface.
Hoover discloses routing the packets to the host computer via a host interface. Hoover at 6:23-33 and 14:17-38.
Further as to claim 28:
The method of claim 23, wherein routing the packet toward the destination comprises routing the packet to the network via the network interface.
Hoover discloses routing the packets to the network via the network interface. Hoover at 9:9-13.
Further as to claim 30:
The method of claim 23, wherein the integrated circuit comprises the hardware accelerator.
Hoover discloses that the chip 100 includes the hardware accelerator. Hoover at 16:56-65.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 31, 33, 37, 39, and 42 are rejected under 35 U.S.C. 103 as being unpatentable over Hoover.
As to claim 31, Hoover discloses:
A computing system comprising:
a network interface controller (NIC) to implement a packet processing pipeline having a plurality of stages, the NIC comprising a host interface coupled to a host and a network interface coupled to a network;
Hoover discloses a system for communication comprising a NIC connected to a host processor and communications network for receiving and processing a packet. Hoover at FIGS 2 and 3, elements 108 and 152 and at 3:52-55. The system including the NIC (element 122) further includes a processor 126 (electrical circuitry) running a packet processing pipeline having multiple stages, including at least one acceleration stage. Id. at FIGS 4 and 5 and at 11:21-37, 13:33-61, and 15:61-65. The NIC is connected to a host by a host interface and a network by a network interface. Id.
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Hoover FIG 5 (excerpt).
Hoover does not disclose that this pipeline and pipeline processing is in the NIC itself, rather it is in an IP Block connected directly to the NIC in the expanded set 122. Hoover at FIG 3. Hoover does, however, refer to the NIC connected to the IP Block as “its [the IP Block’s] network interface controller”. Id. at 8:23-27.
That being said, it would have been obvious to one of ordinary skill in the art to combine the two elements such that the IP Block processor is in the NIC. This is based on the well-known obviousness rationale of making integral. MPEP § 2144.04 V. B., citing In re Larson, 340 F.2d 965, 968, 144 USPQ 347, 349 (CCPA 1965). Further, one of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
and a hardware accelerator coupled to the NIC,
Hoover discloses an accelerator coupled to the NIC. Hoover at FIG 5 and at 14:52-15:9. Note further that while the accelerator is primarily disclosed as software, “readers of skill in the art will immediately recognize that an I/O accelerator may also be implemented as hardware aggregation of sequential and non-sequential logic separate from the processor (126) in the IP block (104) where the I/O accelerator has its own processor and is adapted to the network through a low latency, high bandwidth application messaging interconnect (107).” Id. at 16:56-65. This means the processor circuit including the pipeline necessarily forwards the data to the accelerator processor by way of the disclosed connection. Id.
wherein: the NIC is to:
receive a packet;
store the packet in a buffer;
perform a first task on the packet in a first stage of the packet processing pipeline, wherein the first task is a network processing task;
offload a second task on the packet from the packet processing pipeline to the hardware accelerator;
Hoover discloses processing the packet in the pipeline includes storing the packet in a buffer. Hoover at 10:24-50. Hoover further discloses performing a network processing task on data in one of the stages and transmitting data associated with a stage requiring acceleration to an accelerator where an acceleration task is performed. Id. at FIG 5 and at 14:52-15:9; note that the accelerator may be part of any stage, such as in stage 2, which means processing occurs first in stage 1 followed by accelerated processing. Id. at 16:17-17:10. This reads as offloading.
Note further that while the accelerator is primarily disclosed as software, “readers of skill in the art will immediately recognize that an I/O accelerator may also be implemented as hardware aggregation of sequential and non-sequential logic separate from the processor (126) in the IP block (104) where the I/O accelerator has its own processor and is adapted to the network through a low latency, high bandwidth application messaging interconnect (107).” Id. at 16:56-65. This means the processor circuit including the pipeline necessarily forwards the data to the accelerator processor by way of the disclosed connection. Id.
and; perform a third task on the packet in a second stage of the packet processing pipeline after the first stage;
Hoover discloses the data associated with the stage requiring acceleration, after passing through the accelerator, returning to the processing pipeline in the circuitry (processor). Hoover at 14:17-15:9. Hoover discloses further stages in the pipeline such as stages 2 and 3. Id. at FIGS 4 and 5 and at 11:21-37, 13:33-61, and 15:61-65.
responsive to a status, offload a fourth task on the packet from the packet processing pipeline to the hardware accelerator; and
Hoover discloses reporting a status of a stage processor task to monitor application 640. Hoover at 15:32-48. As such may change the instances of a subsequent stage which may include an accelerated one, this reads on performing another accelerated task responsive to the status. Note Hoover states there may be additional stages i.e. a fourth stage and that it may include an accelerated task in the same manner as the earlier-described offloading. Id. at 14:35-51, stating “Many pipelines according to embodiments of the present invention, however, may include[] many stages and many instances of stages”. Hoover also states that any of the other instances (including 610) may also be accelerated, and that the sending of the data to this further accelerated instance is performed outside of the accelerator, which in the modified invention of Hoover in the rejection above is in the NIC. Id. at 14:52-66.
and route the packet toward a destination after processing the packet in the packet processing pipeline;
Hoover discloses that, after the packet is processed in the pipeline, it is routed toward a destination. Hoover at 9:65-66 and 14:17-51.
and
the hardware accelerator is to perform the second task on the packet at a configurable unit of the hardware accelerator; and
perform the fourth task on the packet at the configurable unit of the hardware accelerator.
Hoover discloses that the processing stage units are configurable. Hoover at 13:36-47.
Further as to claim 33:
The computing system of claim 31, further comprising an integrated circuit comprising the NIC and the hardware accelerator.
Hoover discloses that a chip 100 includes the hardware accelerator and the NIC. Hoover at 16:56-65.
Further as to claim 37:
The computing system of claim 31, wherein the destination is the host, and wherein the NIC is to route the packet to the host via the host interface.
Hoover discloses routing the packets to the host computer via a host interface. Hoover at 6:23-33 and 14:17-38.
As to claim 39, Hoover discloses:
An integrated circuit comprising:
a first port coupled to a network interface;
a second port coupled to a host interface;
a network interface controller (NIC) comprising electrical circuitry configured as a packet processing pipeline having a plurality of stages;
Hoover discloses a system for communication comprising a NIC connected to a host processor by way of a host interface and communications network by way of a network interface for receiving and processing a packet. Hoover at FIGS 2, 3, and 5, elements 105, 108 and 152 and at 3:52-55. The system including the NIC (element 122) further includes a processor 126 (electrical circuitry) running a packet processing pipeline having multiple stages, including at least one acceleration stage. Id. at FIGS 4 and 5 and at 11:21-37, 13:33-61, and 15:61-65. A port connecting to the host and another port coupled to the host interface would be inherent in this design.
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Hoover FIG 5 (excerpt).
Hoover does not disclose that this pipeline and pipeline processing is in the NIC itself, rather it is in an IP Block connected directly to the NIC in the expanded set 122. Hoover at FIG 3. Hoover does, however, refer to the NIC connected to the IP Block as “its [the IP Block’s] network interface controller”. Id. at 8:23-27.
That being said, it would have been obvious to one of ordinary skill in the art to combine the two elements such that the IP Block processor is in the NIC. This is based on the well-known obviousness rationale of making integral. MPEP § 2144.04 V. B., citing In re Larson, 340 F.2d 965, 968, 144 USPQ 347, 349 (CCPA 1965). Further, one of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
and a hardware accelerator coupled to the packet processing pipeline,
Hoover discloses an accelerator coupled to the NIC. Hoover at FIG 5 and at 14:52-15:9. Note further that while the accelerator is primarily disclosed as software, “readers of skill in the art will immediately recognize that an I/O accelerator may also be implemented as hardware aggregation of sequential and non-sequential logic separate from the processor (126) in the IP block (104) where the I/O accelerator has its own processor and is adapted to the network through a low latency, high bandwidth application messaging interconnect (107).” Id. at 16:56-65. This means the processor circuit including the pipeline necessarily forwards the data to the accelerator processor by way of the disclosed connection. Id.
wherein:
the NIC is configured to:
receive a packet;
store the packet in a buffer;
perform a first task on the packet in a first stage of the packet processing pipeline, wherein the first task is a network processing task; and
offload a second task on the packet from the packet processing pipeline to a configurable unit of the hardware accelerator;
Hoover discloses processing the packet in the pipeline includes storing the packet in a buffer. Hoover at 10:24-50. Hoover further discloses performing a network processing task on data in one of the stages and transmitting data associated with a stage requiring acceleration to an accelerator where an acceleration task is performed. Id. at FIG 5 and at 14:52-15:9; note that the accelerator may be part of any stage, such as in stage 2, which means processing occurs first in stage 1 followed by accelerated processing. Id. at 16:17-17:10. This reads as offloading.
Note further that while the accelerator is primarily disclosed as software, “readers of skill in the art will immediately recognize that an I/O accelerator may also be implemented as hardware aggregation of sequential and non-sequential logic separate from the processor (126) in the IP block (104) where the I/O accelerator has its own processor and is adapted to the network through a low latency, high bandwidth application messaging interconnect (107).” Id. at 16:56-65. This means the processor circuit including the pipeline necessarily forwards the data to the accelerator processor by way of the disclosed connection. Id.
Hoover discloses that the processing stage units are configurable. Hoover at 13:36-47.
the hardware accelerator is configured to perform the second task on the packet;
Hoover discloses that the accelerator performs an acceleration task on the data and, after passing through the accelerator, returns it by way of the accelerator to the processing pipeline in the circuitry (processor). Hoover at 14:17-15:9.
and the NIC is further configured to:
perform a third task on the packet in a second stage of the packet processing pipeline after the first stage;
Hoover discloses the data associated with the stage requiring acceleration, after passing through the accelerator, returning to the processing pipeline in the circuitry (processor). Hoover at 14:17-15:9. Hoover discloses further stages in the pipeline such as stages 2 and 3. Id. at FIGS 4 and 5 and at 11:21-37, 13:33-61, and 15:61-65.
responsive to a status, offload a fourth task on the packet from the packet processing pipeline to the the configurable unit of the hardware accelerator; and
Hoover discloses reporting a status of a stage processor task to monitor application 640. Hoover at 15:32-48. As such may change the instances of a subsequent stage which may include an accelerated one, this reads on performing another accelerated task responsive to the status. Note Hoover states there may be additional stages i.e. a fourth stage and that it may include an accelerated task in the same manner as the earlier-described offloading. Id. at 14:35-51, stating “Many pipelines according to embodiments of the present invention, however, may include[] many stages and many instances of stages”. Hoover also states that any of the other instances (including 610) may also be accelerated, and that the sending of the data to this further accelerated instance is performed outside of the accelerator, which in the modified invention of Hoover in the rejection above is in the NIC. Id. at 14:52-66.
and route at least a portion of the packet to a destination after processing the packet in the packet processing pipeline.
Hoover discloses that, after the packet is processed in the pipeline, it is routed toward a destination. Hoover at 9:65-66 and 14:17-51.
Further as to claim 42:
The integrated circuit of claim 39, wherein the destination is a host, and wherein the NIC is to route the packet to the host via the host interface.
Hoover discloses routing the packets to the host computer via a host interface. Hoover at 6:23-33 and 14:17-38.
Claims 25, 26, and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Hoover as applied to claim 23 above, and further in view of U.S. Pat. PGPUB 2016/0330301A1 to Raindel et al. (“Raindel”).
As to claim 25:
The method of claim 23, wherein the second task is a cryptography task, including encryption or decryption.
Hoover discloses the invention of claim 23 above. Hoover fails to disclose that the acceleration task is a decryption of a portion of the packet.
Raindel discloses an analogous art, namely a processing system for packets in a system 20 including a NIC 32 as well as an acceleration stage 26 that packets can be forwarded to for acceleration tasks. Raindel at FIG 1 and at ¶¶41-44. Raindel further discloses that an acceleration task may include decrypting packets. Id. at ¶¶34, 36, and 43.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Hoover in such a manner, namely as to configuring the acceleration tasks to include decryption of packets. One of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
As to claim 26:
The method of claim 23, wherein the second task is a compression task or a decompression task.
Hoover discloses the invention of claim 23 above. Hoover fails to disclose that the acceleration task is a compression or decompression task.
Raindel discloses an analogous art, namely a processing system for packets in a system 20 including a NIC 32 as well as an acceleration stage 26 that packets can be forwarded to for acceleration tasks. Raindel at FIG 1 and at ¶¶41-44. Raindel further discloses that an acceleration task may include compression and decompression. Id. at ¶¶3, 40, and 50.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Hoover in such a manner, namely as to configuring the acceleration tasks to include compression or decompression. One of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
As to claim 29:
The method of claim 23, wherein routing the packet toward the destination comprises routing the packet to the network via the network interface while avoiding transmitting the packet to the host.
Hoover discloses the invention of claim 23 above. Hoover fails to disclose routing the packet to a communications network while avoiding transmitting the packet to the host.
Raindel discloses an analogous art, namely a processing system for packets in a system 20 including a NIC 32 as well as an acceleration stage 26 that packets can be forwarded to for acceleration tasks. Raindel at FIG 1 and at ¶¶41-44. Raindel further discloses that an acceleration task may include encrypting packets to be transmitted to the network by way of connection 38 which avoids the host computer. Id. and further at FIG 6 and ¶¶54 and 65-71.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Hoover in such a manner, namely as to configuring the acceleration tasks to avoid the host. One of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Claim 32, 35, 36, and 38 are rejected under 35 U.S.C. 103 as being unpatentable over Hoover as applied to claim 31 above, and further in view of Raindel.
As to claim 32:
The computing system of claim 31, wherein the network interface is an Ethernet interface and the host interface is a PCle interface.
Hoover discloses the invention of claim 31 above. Hoover discloses an ethernet network interface at 3:64-4:3 and 24:63-25:2 fails to disclose the host interface is by PCIe.
Raindel discloses an analogous art, namely a processing system for packets in a system 20 including a NIC 32 as well as an acceleration stage 26 that packets can be forwarded to for acceleration tasks. Raindel at FIG 1 and at ¶¶41-44. Raindel further discloses that a host computer may be connected by PCIe to the NIC. Id. at ¶¶41, 83 and 85.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Hoover in such a manner, namely as to utilizing the PCIe bus system to connect to the host. Given that the PCIe bus system was notoriously well-known at the time, one of ordinary skill in the art would have understood the common and beneficial nature of using such a well-known system and further would have found such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
As to claim 35:
The method of claim 31, wherein the second task is a cryptography task, including encryption or decryption.
Hoover discloses the invention of claim 31 above. Hoover fails to disclose that the acceleration task is a decryption of a portion of the packet.
Raindel discloses an analogous art, namely a processing system for packets in a system 20 including a NIC 32 as well as an acceleration stage 26 that packets can be forwarded to for acceleration tasks. Raindel at FIG 1 and at ¶¶41-44. Raindel further discloses that an acceleration task may include decrypting packets. Id. at ¶¶34, 36, and 43.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Hoover in such a manner, namely as to configuring the acceleration tasks to include decryption of packets. One of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
As to claim 36:
The method of claim 31, wherein the second task is a compression task or a decompression task.
Hoover discloses the invention of claim 31 above. Hoover fails to disclose that the acceleration task is a compression or decompression task.
Raindel discloses an analogous art, namely a processing system for packets in a system 20 including a NIC 32 as well as an acceleration stage 26 that packets can be forwarded to for acceleration tasks. Raindel at FIG 1 and at ¶¶41-44. Raindel further discloses that an acceleration task may include compression and decompression. Id. at ¶¶3, 40, and 50.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Hoover in such a manner, namely as to configuring the acceleration tasks to include compression or decompression. One of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
As to claim 38:
wherein the destination is a device coupled to the network, and wherein the NIC is to route the packet to the device via the network interface while avoiding transmitting the packet to the host.
Hoover discloses the invention of claim 31 above. Hoover fails to disclose routing the packet to a communications network while avoiding transmitting the packet to the host.
Raindel discloses an analogous art, namely a processing system for packets in a system 20 including a NIC 32 as well as an acceleration stage 26 that packets can be forwarded to for acceleration tasks. Raindel at FIG 1 and at ¶¶41-44. Raindel further discloses that an acceleration task may include encrypting packets to be transmitted to the network by way of connection 38 which avoids the host computer. Id. and further at FIG 6 and ¶¶54 and 65-71.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Hoover in such a manner, namely as to configuring the acceleration tasks to avoid the host. One of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Claims 40 and 43 are rejected under 35 U.S.C. 103 as being unpatentable over Hoover as applied to claim 39 above, and further in view of Raindel.
As to claim 40:
The integrated circuit of claim 39, wherein the network interface is an Ethernet interface and the host interface is a PCle interface.
Hoover discloses the invention of claim 39 above. Hoover discloses an ethernet network interface at 3:64-4:3 and 24:63-25:2 fails to disclose the host interface is by PCIe.
Raindel discloses an analogous art, namely a processing system for packets in a system 20 including a NIC 32 as well as an acceleration stage 26 that packets can be forwarded to for acceleration tasks. Raindel at FIG 1 and at ¶¶41-44. Raindel further discloses that a host computer may be connected by PCIe to the NIC. Id. at ¶¶41, 83 and 85.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Hoover in such a manner, namely as to utilizing the PCIe bus system to connect to the host. Given that the PCIe bus system was notoriously well-known at the time, one of ordinary skill in the art would have understood the common and beneficial nature of using such a well-known system and further would have found such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
As to claim 43:
The integrated circuit of claim 39, wherein the destination is a device, and wherein the NIC is to route the packet to the device via the network interface while avoiding transmitting the packet to a host via the host interface.
Hoover discloses the invention of claim 39 above. Hoover fails to disclose routing the packet to a communications network while avoiding transmitting the packet to the host.
Raindel discloses an analogous art, namely a processing system for packets in a system 20 including a NIC 32 as well as an acceleration stage 26 that packets can be forwarded to for acceleration tasks. Raindel at FIG 1 and at ¶¶41-44. Raindel further discloses that an acceleration task may include encrypting packets to be transmitted to the network by way of connection 38 which avoids the host computer. Id. and further at FIG 6 and ¶¶54 and 65-71.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Hoover in such a manner, namely as to configuring the acceleration tasks to avoid the host. One of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Hoover as applied to claim 23 above, and further in view of U.S. Pat. 6,157,955 to Narad et al. (“Narad”)
As to claim 24:
The method of claim 23, wherein the network processing task comprises at least one of packet parsing, packet classification, or network address translation.
While disclosing the invention of claim 23, Hoover fails to disclose that the network processing task comprises parsing, classification, or NAT.
Narad discloses in an analogous art, namely a packet processing computer platform (FIG 1), that a NIC may operate according a pipelined processor scheme where certain stages are for classification. Narad at Abstract and at 3:46-65. Narad discloses that this system works with coupled accelerator processors as well for encryption functions. Id. and at 4:1-2.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Hoover in such a manner, namely as to configuring the network tasks to include classification. Narad discloses this as a use of such a system as Hoover and that they may be optimize for the functions. Further, One of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Claim 34 is rejected under 35 U.S.C. 103 as being unpatentable over Hoover as applied to claim 31 above, and further in view of Narad.
As to claim 34:
The computing system of claim 31, wherein the network processing task comprises at least one of packet parsing, packet classification, or network address translation.
While disclosing the invention of claim 31, Hoover fails to disclose that the network processing task comprises parsing, classification, or NAT.
Narad discloses in an analogous art, namely a packet processing computer platform (FIG 1), that a NIC may operate according a pipelined processor scheme where certain stages are for classification. Narad at Abstract and at 3:46-65. Narad discloses that this system works with coupled accelerator processors as well for encryption functions. Id. and at 4:1-2.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Hoover in such a manner, namely as to configuring the network tasks to include classification. Narad discloses this as a use of such a system as Hoover and that they may be optimize for the functions. Further, one of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Claim 41 is rejected under 35 U.S.C. 103 as being unpatentable over Hoover as applied to claim 39 above, and further in view of Narad.
As to claim 41:
The integrated circuit of claim 39, wherein the network processing task comprises at least one of packet parsing, packet classification, or network address translation, and wherein the second task comprises at least one of a cryptography task, including encryption or decryption, a compression task, or a decompression task.
Hoover discloses the invention of claim 39 above. Hoover fails to disclose that the acceleration task is a cryptography task including encryption, decryption, compression, or decompression and the network task is a parsing, classification, or NAT task.
Narad discloses in an analogous art, namely a packet processing computer platform (FIG 1), that a NIC may operate according a pipelined processor scheme where certain stages are for classification. Narad at Abstract and at 3:46-65. Narad discloses that this system works with coupled accelerator processors as well for encryption functions. Id. and at 4:1-2.
Therefore it would have been obvious to one of ordinary skill in the art at the time of the invention to modify Hoover in such a manner, namely as to configuring the network tasks to include classification. Narad discloses this as a use of such a system as Hoover and that they may be optimize for the functions. Further, one of ordinary skill in the art would have understood such to merely be an example of combining prior art elements according to known methods to yield predictable results. MPEP § 2143 I. A., citing KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Response to Arguments
Applicant provides arguments in his response (“Remarks”).
As to the previous rejection under Double Patenting (Remarks at 9), the Examiner upholds the rejection and the rejection will not be held in abeyance. MPEP § 804 I. B. 1.
As to the Patent Owner’s arguments towards rejections under §102(a)(1) (Remarks at 11-14), the Examiner finds Patent Owner’s arguments towards Hoover to be not persuasive.
As to the returning of a status and acceleration tasks based thereon (the primary focus of Patent Owner’s arguments), the Examiner notes that the Office action cites to at least 15:32-48 of Hoover. This portion of Hoover clearly discloses the determination of a status of a task and performing of subsequent tasks based thereon, stating:
In the pipeline of FIG. 5, for example, where a computer software application (500) is segmented into stages, the stages are load balanced with a number of instances of each stage in dependence upon the performance of the stages. Such load balancing can be carried out, for example, by monitoring the performance of the stages and instantiating a number of instances of each stage in dependence upon the performance of one or more of the stages. Monitoring the performance of the stages can be carried out by configuring each stage to report performance statistics to a monitoring application (640) that in turn is installed and running on another thread of execution on an IP block or host interface processor. Performance statistics can include, for example, time required to complete a data processing task, a number of data processing tasks completed within a particular time period, and so on, as will occur to those of skill in the art.”
Note further Id. at 15:49-60, which further states that “[i]nstantiating a number of instances of each stage in dependence upon the performance of one or more of the stages can be carried out by instantiating, by a host interface processor (105), a new instance of a stage when monitored performance indicates a need for a new instance.”
As to the stages being accelerated stages, Hoover is cited at, among others, 15:61-65 which states that the instances listed above may be accelerated stages. Note also id. at 16:19-23, cited in the rejection, which states that any instance may be an accelerated one.
Note that Hoover discloses as an example an accelerated instance 608 followed by a non-accelerated instance 610. Hoover at FIG 5. Hoover also states that any of the other instances (including 610) may also be accelerated, and that the sending of the data to this further accelerated instance is performed outside of the accelerator, which in the modified invention of Hoover in the rejection above is in the NIC. Id. at 14:52-66. This, given the above teachings, means that in Hoover an accelerated instance may, based on the status of the work produced by the accelerated instance, be further routed to another accelerated instance by the NIC.
Further, Patent Owner’s arguments that Hoover fails to disclose performing a network processing task are not persuasive, as the Examiner asserts that processing packets in a network reads on a “network processing task”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Charles Craver whose telephone number is (571) 272-7849. The Examiner can normally be reached on Monday - Friday 8:30-5:30 PT Pacific Time.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Andrew J. Fischer can be reached on 571-272-6779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Signed,
/CHARLES R CRAVER/Reexamination Specialist, Art Unit 3992
Conferees:
/ROBERT J HANCE/Primary Examiner, Art Unit 3992 /M.F/Supervisory Patent Examiner, Art Unit 3992
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