DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Amendments filed on12/08/2025, wherein Claim 1 has been amended. Claims 2 and 3 were cancelled. Claims 16 and 17 are new. Claims 1 and 4-17 are pending.
Response to Arguments
Regarding 35 USC 103 rejection for Claim 1: Applicant's arguments filed on 12/08/2025, with respect to 35 USC 103 rejection for Claim 1, have been fully considered and found persuasive. The 35 USC 103 rejection is withdrawn for Claims 1, 4-8, and 16.
Regarding 35 USC 103 rejection for Independent Claim 9:
Applicant argues: “Both Chung and Lim only mention that the latch circuit will set
a discharging path on only one side. Specifically, Chung's latch circuit (202, 204) in FIG. 3A does not set the discharging path on the right side (node 212), and Lim's latch circuit 210 does not set the discharging path on the right side. Therefore, a person skilled in the art will not be motivated to modify Chung's power up reset circuit by using Lim's circuit to obtain the feature of the amended claim 9: "at least one first discharging path coupled to the first node, configured to discharge charges of the first node; and at least one second discharging path coupled to the second node, configured to discharge charges of the second node. Chung's elements 202 and 204 form a latch circuit, and its two nodes 210 and 212 must be at two different voltage levels (i.e., 0 and 1, respectively). Therefore, a person of ordinary skill in the art would not have the motivation to provide discharging paths at both nodes 210 and 212 in the Chung reference, as doing so would interfere with the original operation of the circuit”.
Examiner respectfully disagrees. In Claim 9, applicant states: “at least one first discharging path coupled to the first node, configured to discharge charges of the first node; and at least one second discharging path coupled to the second node, configured to discharge charges of the second node”,
Chung’s Fig. 3A clearly shows “at least one first discharging path coupled to the first node, configured to discharge charges of the first node” (e.g., path 202 - 212 - 208 - ground) and “at least one second discharging path coupled to the second node, configured to discharge charges of the second node” (e.g., path 206 - 210 - 218 - ground). The rest of Applicant’s arguments is about the features not shown in Claim 9.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 9 and 12-15 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by US20050174154 to Chung (hereinafter Chung).
Regarding Claim 9: Chung discloses:
“A glitch detector” (Fig. 3A; Abstract - “The invention discloses a power up reset circuit (i.e. glitch detector, added by examiner). A power supply voltage follower connected to a power supply is used for proportionally following an increase of a supply voltage to output a power up reset signal.”), comprising:
“a first inverter connected between a supply voltage and a ground voltage; a second inverter connected between the supply voltage and the ground voltage” (Fig. 3A; para 0021 – “The PUR circuit 200 includes, but not limited to, a power supply voltage follower connected to a power supply, and a pulse generation control circuit coupled to the same. The power supply voltage follower is collectively represented by inverters 202 and 204”),
“configured to receive a first signal at a first node to generate a second signal to a second node, configured to receive the second signal at the second node to generate the first signal to the first node” (Fig. 3A, first node 210, second node 212; para 0022 – “The output lead of the inverter 202 is connected to the input lead of the inverter 204 via a node 210. The output lead of the inverter 204 is connected to the input lead of the inverter 202 via a node 212.”);
“at least one first discharging path coupled to the first node, configured to discharge charges of the first node” (Fig. 3A, transistor 218 providing first discharging path for the first node 210; para 0025 – “The threshold voltage would equal to the summation of individual threshold voltages of the PMOS transistors 216 and NMOS 218 plus an additional voltage drop across the PMOS transistor 220. This will then allow a node 222 to have a voltage level that meets the design margin, thereby turning on the transistor 218 and further pulling the node 210 low to ground”; and
“and at least one second discharging path coupled to the second node, configured to discharge charges of the second node” (Fig. 3A; para 0022 – “The output lead of the inverter 204 is connected to the input lead of the inverter 202 via a node 212… The capacitor 208 is connected between the node 212 and ground (i.e. second discharging path, added by examiner). The capacitors 206 and 208 are coupled to VDD and GND, respectively”; see also para 0024).
Regarding Claim 12: Chung discloses the glitch detector of Claim 9.
Chung further discloses:
“wherein the at least one first discharging path discharges the charges of the first node” (Fig. 3A, transistor 218 providing first discharging path for the first node 210; para 0025 – “The threshold voltage would equal to the summation of individual threshold voltages of the PMOS transistors 216 and NMOS 218 plus an additional voltage drop across the PMOS transistor 220. This will then allow a node 222 to have a voltage level that meets the design margin, thereby turning on the transistor 218 and further pulling the node 210 low to ground”); and
“the at least one second discharging path discharges the charges of the second node when the supply voltage suffers an under-voltage glitch” (para 0025 – “This will then allow a node 222 to have a voltage level that meets the design margin, thereby turning on the transistor 218 and further pulling the node 210 low to ground… This will activate the flipping of the state of the presser latch to low. The PUR signal at the output of the inverter 214 will go low subsequently and produce a reset pulse”; para 0026 – “To ensure proper design margins, the capacitors 206 and 208 are preferably made of metal fringe capacitors or zero threshold voltage MOS devices such that the sufficient capacitance can be guaranteed even when VDD is very low… An NMOS transistor 224 provides a leakage path to keep the node 222 at least one PMOS diode drop below VDD (i.e. the under-voltage glitch, added by examiner)”).
Regarding Claim 13: Chung discloses the glitch detector of Claim 9.
Chung further discloses:
“wherein the at least one first discharging path comprises a first P-type transistor and a first N-type transistor, the first P-type transistor is configured to selectively provide a current path between the supply voltage and the first node, and the first N-type transistor is configured to selectively provide a current path between the ground voltage and the first node” (Figs. 3A and 3B; para 0023 – “The devices 216, 220, 224, and 226 constitute a level detection circuit. The PMOS transistor 216 (i.e. P-type transistor, added by examiner) is coupled between the power supply and the PMOS transistor 220, with its gate connected to its drain. The PMOS transistor 220 has a grounded gate and a drain connected to a gate of the NMOS transistor 218 (i.e. N-type transistor, added by examiner) via a node 222. The NMOS transistor 218 is connected between the node 210 and ground. A capacitor 226 and NMOS transistor 224 are coupled between the node 222 and ground”).
Regarding Claim 14: Chung discloses the glitch detector of Claim 13.
Chung further discloses:
“wherein the at least one second discharging path comprises a second P-type transistor and a second N-type transistor, the second P-type transistor is configured to selectively provide a current path between the supply voltage and the second node, and the second N-type transistor is configured to selectively provide a current path between the ground voltage and the second node” (Fig. 3A – P-type transistors 216 and 220; N-type transistors 218 and 224; para 0023 – “The devices 216, 220, 224, and 226 constitute a level detection circuit. The PMOS transistor 216 is coupled between the power supply and the PMOS transistor 220, with its gate connected to its drain. The PMOS transistor 220 has a grounded gate and a drain connected to a gate of the NMOS transistor 218 via a node 222. The NMOS transistor 218 is connected between the node 210 and ground. A capacitor 226 and NMOS transistor 224 are coupled between the node 222 and ground.”).
Regarding Claim 15: Chung discloses the glitch detector of Claim 14.
Chung further discloses:
“wherein each of the first P-type transistor, the first N-type transistor, the second P-type transistor and the second N-type transistor is a diode-connected transistor” (para 0025 – “The NMOS transistor 224, with gate grounded, provides small leakage current to determine the threshold voltage of the PMOS transistor 216 that is connected as a diode”; para 0026 – “An NMOS transistor 224 provides a leakage path to keep the node 222 at least one PMOS diode drop below VDD. A small capacitor 226 acts as a noise filter for VDD glitches.”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 10, 11, and 17 are rejected under 35 U.S.C. 103 as being obvious over Chung in view of US5457414 to Inglis et al. (hereinafter Inglis).
Regarding Claim 10: Chung discloses the glitch detector of Claim 9.
Chung does not specifically disclose:
“further comprising: a warning signal generator, coupled to the first node or the second node, configured to determine whether the supply voltage suffers an under-voltage glitch according to a voltage level of the first signal or a voltage level of the second signal, to determine whether to output a warning signal”.
However, Inglis discloses:
“further comprising: a warning signal generator, coupled to the first node or the second node, configured to determine whether the supply voltage suffers an under-voltage glitch according to a voltage level of the first signal or a voltage level of the second signal, to determine whether to output a warning signal” (Fig. 1; Col. 2, lines 22 – 39 – “Referring to FIG. 1, a block diagram of an illustrative embodiment of the invention is shown. During normal operation, the loss sensor samples VDD (primary power source) at a given rate and compares this with VBAT (backup battery source). If VDD is lower than VBAT (interpreted as a voltage level of the first signal, added by examiner) a warning signal (ENA) is set, to indicate this condition, and the loss sensor output (VISO) is switched to draw power from VBAT rather than VDD. … The illustrative circuit embodiment includes 5 logic blocks. They are the CLKGEN (Clock Generator) 10, VLD (VDD Loss Detector) 11, LSG (Loss of Signal Generator) 12, GDT (Glitch Detector) 13, and PWS (Power Switch) 14. The voltage VISO powers all the devices in the LSG and GDT blocks (12,13) as indicated”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a glitch detector disclosed by Chung, as taught by Inglis, in order to efficiently and quickly detect the under-voltage glitch and output the warning signal.
Regarding Claim 11: Chung/Inglis combination discloses the glitch detector of Claim 10.
Chung does not specifically disclose:
“wherein when the supply voltage does not suffer an under-voltage glitch, the first signal has a first logical value, the second signal has a second logical value different from the first logical value; and after the supply voltage suffers the under-voltage glitch, the warning signal generator determines that the supply voltage suffers the under-voltage glitch by detecting if the first signal changes to the second logical value, or by detecting if the second signal changes to the first logical value”.
However, Ingles discloses:
“wherein when the supply voltage does not suffer an under-voltage glitch, the first signal has a first logical value, the second signal has a second logical value different from the first logical value; and after the supply voltage suffers the under-voltage glitch, the warning signal generator determines that the supply voltage suffers the under-voltage glitch by detecting if the first signal changes to the second logical value, or by detecting if the second signal changes to the first logical value” (Col. 4, lines 30 – 59 – “The GDT block also generates a reset pulse RST to the LSG block if a glitch is detected on VDD. This condition is detected if, in any sampling period, node VSW has been set low by the LSG and SOUT is also low. If a glitch occurred on the VDD input then VSW would be low and SOUT would be high resulting in a low output from gate 70. This low output is latched by 71 and no reset pulse is generated in the same sampling period that the glitch occurred. If, in the subsequent sample period, the glitch is no longer present then both VSW and SOUT will be low. CKB would then clock the high output of gate 70 into latch 71. The output of latch 71 is qualified by NAND gate 72 according to CKC (FIG. 4) to generate a low reset pulse (RST low). This pulse resets VSW back to high (FIG. 5), indicating that the VDD is greater than VBAT. In summary, the RST signal is normally high, but goes low after 2 clock cycles when VDD goes greater than VBAT.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a glitch detector disclosed by Chung/Inglis combination, as taught by Inglis, in order to efficiently and quickly detect the under-voltage glitch and output the warning signal.
Regarding Claim 17: Chung/Inglis combination discloses the glitch detector of Claim 11.
Chung does not specifically disclose:
“wherein after the warning signal is generated, the first signal is reset to have the first logical value, the second signal is reset to have the second logical value”.
However, Inglis discloses:
“wherein after the warning signal is generated, the first signal is reset to have the first logical value, the second signal is reset to have the second logical value” (Col. 4, lines 30 – 59 – “The GDT block also generates a reset pulse RST to the LSG block if a glitch is detected on VDD. This condition is detected if, in any sampling period, node VSW has been set low by the LSG and SOUT is also low. If a glitch occurred on the VDD input then VSW would be low and SOUT would be high resulting in a low output from gate 70. This low output is latched by 71 and no reset pulse is generated in the same sampling period that the glitch occurred. If, in the subsequent sample period, the glitch is no longer present then both VSW and SOUT will be low. CKB would then clock the high output of gate 70 into latch 71. The output of latch 71 is qualified by NAND gate 72 according to CKC (FIG. 4) to generate a low reset pulse (RST low). This pulse resets VSW back to high (FIG. 5), indicating that the VDD is greater than VBAT. In summary, the RST signal is normally high, but goes low after 2 clock cycles when VDD goes greater than VBAT.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a glitch detector disclosed by Chung/Inglis combination, as taught by Inglis, in order to efficiently and quickly detect the under-voltage glitch and output the warning signal.
Allowable Subject Matter
Claims 1, 4-8, and 16 are allowed.
The following is a statement of reasons for the indication of allowable subject matter.
In regards to independent Claim 1, the teachings of Chung, Lim, Kim, Nakamura, and Xue combined show all the elements of the claim except “after the supply voltage suffers the under-voltage glitch and the supply voltage returns to a normal voltage level, the first signal changes to the second logical value and is maintained at the second logical value, and the second signal changes to the first logical value and is maintained at the first logical value after the under-voltage glitch, and the warning signal generator determines that the supply voltage suffers the under-voltage glitch by detecting if the first signal changes to the second logical value, or by detecting if the second signal changes to the first logical value”, in combination with the rest of the claim limitations as claimed and defined by the applicant.
Claims 4-8 and 16 are allowed as being dependent on allowed Claim 1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US20030226082A1 to Kim et al. (hereinafter Kim) discloses voltage-glitch detection device and method for securing integrated circuit device from voltage glitch attack.
US20080252474A1 to Nakamura et al. (hereinafter Nakamura) discloses proximity sensor and proximity sensing method.
US20210048455A1 to Xue et al. (hereinafter Xue) discloses power glitch signal detection circuit, security chip and electronic apparatus.
US5428252 to Walker et al. (hereinafter Walker) discloses power supply interruption detection and response system for a microcontroller.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lyudmila Zaykova-Feldman whose telephone number is (469)295-9269. The examiner can normally be reached 8:30am - 5:30pm CT, Monday through Friday.
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/LYUDMILA ZAYKOVA-FELDMAN/Examiner, Art Unit 2857
/LINA CORDERO/Primary Examiner, Art Unit 2857