DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Applicant's arguments filed 02/11/2026 regarding the prior art rejections of Claims 1 – 20 have been fully considered, but they are not persuasive.
The Examiner disagrees MacGarry in view of Kleveland does teach and disclose the emphasized portions of claim 1. MacGarry teaches a BIST controller for the maintenance operations for training events. However, the BIST testing can also trigger other testing one skilled in the art could conclude the claimed limitation. (0055, issue a trigger to the BIST controller 170 to trigger performance of the BIST maintenance operation. This means that the BIST maintenance operation can be performed during a period of time when no active pending access requests can be processed anyway, and accordingly no such contention issues arise.)
MacGarry does not teach away from runtime testing. (0032 & 0074, As such, accesses to such a cache structure may significantly reduce, or stop, during periods where the physical layer interface is being subjected to the training operation, due to the fact that no active access requests are processed during that period. This period hence also represents a suitable period of time for performing maintenance tasks in respect of the storage elements within the cache structure, and accordingly the trigger from the control circuitry can be propagated on to such a cache structure to initiate those maintenance tasks during that period. Where the runtime of the required maintenance tasks is mismatched with the timing required for performing the training operation, the maintenance circuitry can be configured to perform partial maintenance so as to only test certain parts of the SRAM memory array during each physical layer training process, so that over a number of iterations of the training operation the entire SRAM array can be tested.)
Kleveland cures any deficiencies because Kleveland teaches a memory device with background built-in self-test BBIST comprising: a plurality of memory blocks, a memory buffer for temporarily unloading data from the plurality of memory blocks, and a memory block a stress controller for temporarily unloading the data on the memory buffer control applied stress testing of the one of the memory blocks. said stress testing of the one error in the plurality of the memory blocks to be tested. One skilled in the art could conclude the claimed invention.
Claims 2 – 11 which depend from amended claim 1, have been considered and rejected.
Claims 13 – 17 which depend from amended claim 12, have been considered and rejected.
Claims 19 – 20 which depend from amended claim 18, have been considered and rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over MacGarry (US 2017/0371560 A1) in view of Kleveland (CN 104412327 A).
In regards to claim 1, MacGarry teaches:
A device comprising: an interface to communicate with processing logic, the processing logic to access a memory; (0004, memory access execution circuitry to issue to a physical layer interface access requests selected from the storage device) and logic to schedule runtime testing of the memory in multiple built-in self-test (BIST) testing phases, wherein the logic is also to: (0047, A scheduler circuit 120 is used to perform scheduling operations in respect of the contents of the pending access request buffer(s) in order to determine the order in which to issue the pending access requests to the memory device);
MacGarry fails to teach:
trigger, responsive to initiation of a BIST testing phase from among the multiple BIST testing phases, memory BIST testing of a subset of memory locations BIST testing phase; and in response to completion of the memory BIST testing BIST testing phase, send a notification to the processing logic to resume access to the memory.
However, Kleveland teaches:
trigger, responsive to initiation of a BIST testing phase from among the multiple BIST testing phases, memory BIST testing of a subset of memory locations BIST testing phase; (0107 & 0009, access circuit (e.g., circuits 544, 545 and 546) has adjustable or selectable energy level similar to the entire memory block of a BIST memory block. granularity can selectively permit the target memory under test (TMUT); phase-change memory (PRAM)) and in response to completion of the memory BIST testing BIST testing phase, send a notification to the processing logic to resume access to the memory. (0081, different fault or weakness pattern can determine different repair mode of each background diagnostic module, which is the background restore module and/or notification of the host for execution. notification of the host can be in any form, such as a flag in an error register, handshake protocol and interrupt signal).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the method of MacGarry which teaches the device with a scheduler of phases with the teaching of Kleveland which teaches trigger memory built-in self-test testing in order initiate self tests based clock signals (Kleveland: 0134, BIST flow chart 1020-1 to external request 1021-A or an internal request 1021-B starts. the internal request 1021-B can be default BIST scheme, wherein the predetermined regular intervals test in a given number of cycles, the elapsed time event (e.g., interrupt, initialization or stop) and/or any combination of these items.).
In regards to claim 2, MacGarry in view of Kleveland teaches the device of claim 1.
MacGarry fails to teach:
wherein: execution of the memory BIST testing during runtime includes preservation of data stored at the subset of memory locations.
However, Kleveland teaches:
wherein: execution of the memory BIST testing during runtime includes preservation of data stored at the subset of memory locations. (0069, Picture of the brushing operation 2C and 2D memory portion in the retrieval operation, opportunities to read and followed by error detection and correction (EDC) algorithm processing the memory part, and comparing it with the original stored data to identify and replace any erroneous bits.)
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the method of MacGarry which teaches the device with a scheduler of phases with the teaching of Kleveland which teaches trigger memory built-in self-test testing in order initiate self tests based clock signals (Kleveland: 0134, BIST flow chart 1020-1 to external request 1021-A or an internal request 1021-B starts. the internal request 1021-B can be default BIST scheme, wherein the predetermined regular intervals test in a given number of cycles, the elapsed time event (e.g., interrupt, initialization or stop) and/or any combination of these items.).
In regards to claim 3, MacGarry in view of Kleveland teaches the device of claim 1.
MacGarry fails to teach:
wherein: a state of the subset of memory locations is the same before and after the
However, Kleveland teaches:
wherein: a state of the subset of memory locations is the same before and after the (0074, mapping with the eFUSE address and TMUT from the BIST address to determine whether a match exists)
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the method of MacGarry which teaches the device with a scheduler of phases with the teaching of Kleveland which teaches trigger memory built-in self-test testing in order initiate self tests based clock signals (Kleveland: 0134, BIST flow chart 1020-1 to external request 1021-A or an internal request 1021-B starts. the internal request 1021-B can be default BIST scheme, wherein the predetermined regular intervals test in a given number of cycles, the elapsed time event (e.g., interrupt, initialization or stop) and/or any combination of these items.).
In regards to claim 4, MacGarry in view of Kleveland teaches the device of claim 1.
MacGarry teaches:
wherein: the logic is to schedule the runtime testing of all memory locations of the memory that are eligible for testing in the BIST testing multiple phases, wherein one of multiple subsets of memory locations is to be tested in each of the multiple BIST testing phases (0054, the BIST controller 170 can update its records to identify that that series of cells has passed the test. If any cells fail the test, then that fail condition can be flagged to a suitable agent such as a firmware agent, that can then run a process to invalidate the affected SRAM cell or cells, and ideally utilize redundant cells instead. It will be appreciated that due to the multiple write and read sequences required).
In regards to claim 5, MacGarry in view of Kleveland teaches the device of claim 1.
MacGarry teaches:
wherein: the processing logic is to resume access to the memory between successive BIST testing phases (0034, by allowing the scheduling circuitry to perform such maintenance tasks in the period where the physical layer interface is being trained, the maintenance circuitry can perform such maintenance tasks without introducing any contention with respect to the live data access traffic).
In regards to claim 6, MacGarry in view of Kleveland teaches the device of claim 1.
MacGarry teaches:
wherein: the logic to schedule the runtime testing is to: request, during runtime, that the processing logic pause access to the memory, and cause a memory BIST controller to test the subset of memory locations of the memory in the BIST testing phase while the processing logic's access to the memory is paused (0038, and to then schedule those access requests for processing within the memory device 40).
In regards to claim 7, MacGarry in view of Kleveland teaches the device of claim 1.
MacGarry teaches:
further comprising: a register to store a value to indicate a number of memory locations to test in one of the multiple BIST testing phases; wherein the logic is to trigger the memory BIST testing in the BIST testing phase for the number of memory locations indicated by the register (0023, update the control register value to that predetermined value).
In regards to claim 8, MacGarry in view of Kleveland teaches the device of claim 1.
MacGarry teaches:
wherein: after completion of the runtime testing of all the memory locations of the memory that are eligible for testing, the logic is to repeat scheduling of the runtime testing of memory (0072, At this point, no trigger will have been received, and the process will then proceed to step 355 where the normal operation of the scheduler is resumed).
In regards to claim 9, MacGarry in view of Kleveland teaches the device of claim 1.
MacGarry teaches:
wherein: the processing logic includes (0053, In one embodiment a built-in self-test (BIST) controller 170 is provided for performing periodic checks on the SRAM cells in order to determine the presence of any hard errors, indicating faults in the operation of individual SRAM cells).
In regards to claim 10, MacGarry in view of Kleveland teaches the device of claim 1.
MacGarry fails to teach:
further comprising: a register to store a value to indicate a frequency at which to schedule the runtime testing; wherein the logic is to trigger the memory BIST testing in the multiple BIST testing phases at the frequency indicated by the register.
However, Kleveland teaches:
further comprising: a register to store a value to indicate a frequency at which to schedule the runtime testing; wherein the logic is to trigger the memory BIST testing in the multiple BIST testing phases at the frequency indicated by the register. (0081, different fault or weakness pattern can determine different repair mode of each background diagnostic module)
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the method of MacGarry which teaches the device with a scheduler of phases with the teaching of Kleveland which teaches trigger memory built-in self-test testing in order initiate self tests based clock signals (Kleveland: 0134, BIST flow chart 1020-1 to external request 1021-A or an internal request 1021-B starts. the internal request 1021-B can be default BIST scheme, wherein the predetermined regular intervals test in a given number of cycles, the elapsed time event (e.g., interrupt, initialization or stop) and/or any combination of these items.).
In regards to claim 11, MacGarry in view of Kleveland teaches the device of claim 1.
MacGarry fails to teach:
further comprising: a second interface with an error handler; wherein the logic is to report errors to an error handler via the second interface.
However, Kleveland teaches:
further comprising: a second interface with an error handler; wherein the logic is to report errors to an error handler via the second interface. (0081, notification of the host can be in any form, such as a flag in an error register, handshake protocol and interrupt signal. Alternatively, the microcontroller may execute the flowchart operation of FIG. 11 executes the diagnosis code)
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the method of MacGarry which teaches the device with a scheduler of phases with the teaching of Kleveland which teaches trigger memory built-in self-test testing in order initiate self tests based clock signals (Kleveland: 0134, BIST flow chart 1020-1 to external request 1021-A or an internal request 1021-B starts. the internal request 1021-B can be default BIST scheme, wherein the predetermined regular intervals test in a given number of cycles, the elapsed time event (e.g., interrupt, initialization or stop) and/or any combination of these items).
In regards to claim 12, MacGarry in view of Kleveland teaches the system on a chip. The claim corresponds to claim 1 as analyzed accordingly.
In regards to claim 13, MacGarry in view of Kleveland teaches the device of claim 1.
MacGarry teaches:
wherein: the SOC includes multiple partitions, each of the multiple partitions including partition memory and partition processing logic; and the logic is also to: (0041, in some embodiments the memory device is partitioned into multiple parts) request that the partition processing logic of a partition pause access to the partition memory during runtime, and in response to completion of the memory BIST testing BIST testing phase, send the notification to the partition processing logic to resume access to the partition memory (0065, Thereafter, the process may return to step 200, or optionally step 220 may be implemented where the training circuitry notifies the SRAM maintenance circuitry that the training operation is complete. That information could then be used by the maintenance circuitry (whether that be the BIST controller 170 or the scheduler 120) to terminate the ongoing maintenance operation, since once the training operation is complete, the memory controller 30 can return to live operation where the pending access requests can again begin to be processed for issuance to the memory device 40).
In regards to claim 14, MacGarry in view of Kleveland teaches the system on a chip of claim 12. The claim corresponds to claim 2 as analyzed accordingly.
In regards to claim 15, MacGarry in view of Kleveland teaches the system on a chip of claim 12. The claim corresponds to claim 3 as analyzed accordingly.
In regards to claim 16, MacGarry in view of Kleveland teaches the system on a chip of claim 12. The claim corresponds to claim 4 as analyzed accordingly.
In regards to claim 17, MacGarry in view of Kleveland teaches the system on a chip of claim 12. The claim corresponds to claim 5 as analyzed accordingly.
In regards to claim 18, MacGarry teaches:
A non-transitory machine-readable medium having instructions stored thereon configured to be executed on one or more processors to perform a method comprising: (0047 & 0054, A scheduler circuit 120 is used to perform scheduling operations in respect of the contents of the pending access request buffer(s) in order to determine the order in which to issue the pending access requests to the memory device. This can take into account the structure and organization of the memory device in order to seek to optimize the performance of the memory accesses. The BIST controller 170 can update its records to identify that that series of cells has passed the test. If any cells fail the test, then that fail condition can be flagged to a suitable agent such as a firmware agent, that can then run a process to invalidate the affected SRAM cell or cells, and ideally utilize redundant cells instead. It will be appreciated that due to the multiple write and read sequences required).
MacGarry fails to teach:
triggering, responsive to initiation of a phase from among multiple BIST testing phase, memory BIST testing of subsets of memory locations of the memory during runtime, wherein during the BIST testing phase, testing of a subset of memory locations in [[a]] the BIST testing phase, cause access to the memory to resume between successive BIST testing phases.
However, Kleveland teaches:
triggering, responsive to initiation of a phase from among multiple BIST testing phase, memory BIST testing of subsets of memory locations of the memory during runtime, wherein during the BIST testing phase, the memory is paused; and in response to completion of the memory BIST testing of a subset of memory locations in [[a]] the BIST testing phase, cause access to the memory to resume between successive BIST testing phases. (0107 & 0009, access circuit (e.g., circuits 544, 545 and 546) has adjustable or selectable energy level similar to the entire memory block of a BIST memory block. granularity can selectively permit the target memory under test (TMUT); phase-change memory (PRAM)).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the method of MacGarry which teaches the device with a scheduler of phases with the teaching of Kleveland which teaches trigger memory built-in self-test testing in order initiate self tests based clock signals (Kleveland: 0134, BIST flow chart 1020-1 to external request 1021-A or an internal request 1021-B starts. the internal request 1021-B can be default BIST scheme, wherein the predetermined regular intervals test in a given number of cycles, the elapsed time event (e.g., interrupt, initialization or stop) and/or any combination of these items.).
In regards to claim 19, MacGarry in view of Kleveland teaches the non-transitory machine-readable medium of claim 18.
MacGarry teaches:
wherein: triggering the memory BIST testing for a subset of memory locations includes: sending a request during runtime to a functional module to pause access to the memory, and causing a memory BIST controller to test the subset of memory locations of the memory while access to the memory is paused during the BIST testing phase. (0047, A scheduler circuit 120 is used to perform scheduling operations in respect of the contents of the pending access request buffer(s) in order to determine the order in which to issue the pending access requests to the memory device. This can take into account the structure and organization of the memory device in order to seek to optimize the performance of the memory accesses).
In regards to claim 20, MacGarry in view of Kleveland teaches the non-transitory machine-readable medium of claim 18. The claim corresponds to claim 2 as analyzed accordingly.
Prior Art Made of Record
The prior art mode of record and not relied upon is considered pertinent to
Applicant’s disclosure:
Lo (US 2013/0326294 A1): A three-dimensional (3-D) memory includes: multiple memory dies, each having at least one memory bank and a built-in self-test (BIST) circuit; and a plurality of channels, for electrically connecting the memory dies. In a synchronous test, one of the memory dies is selected as a master die. The BIST circuit of the master die sends an enable signal via the channels to the memory dies under test. The BIST circuit in each of the memory dies is for testing memory banks on the same memory die or on different memory dies.
Response to Arguments
Applicant's arguments filed 02/11/2026 regarding the prior art rejections of Claims 1 – 20 have been fully considered, but they are not persuasive.
The Remarks argue that:
Claims 1- 20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. Pub. No. 2017 /0371560 to MacGarry et al. ("MacGarry") in view of CN Pat. No. 104412327 to Kleveland ("Kleveland").
A portion of claim 1, as currently amended, recites:
"an interface to communicate with processing logic, the processing logic to access a memory; and
logic to schedule runtime testing of the memory in multiple built-in self-test (BIST) testing phases, wherein the logic is also to: trigger, responsive to initiation of a BIST testing phase from among the multiple BIST testing phases, memory BIST testing of a subset of memory locations, the processing logic to pause access to the memory during the BIST testing phase; and in response to completion of the memory BIST testing of the subset of the memory locations in the BIST testing phase, send a notification to the processing logic to resume access to the memory."
(Emphasis added).
Applicant submits that MacGarry in view of Kleveland fails to teach or disclose at least the
above-emphasized portions of claim 1. First, MacGarry only describes triggering maintenance operations responsive to training events to train a physical layer or connection to a memory device. For example, see paragraph [0023]. Therefore, MacGarry does not describe "trigger, responsive to initiation of a BIST test phase" as recited above for claim 1. Second, MacGarry mentions both in paragraphs [0021] and [0074] that these training events are during downtime and that maintenance operations only occur during that downtime. In other words, MacGarry teaches away from runtime testing as recited above for claim 1. Kleveland was not cited to cure the above-described deficiencies of MacGarry and Applicant submits that Kleveland does not cure the above-described deficiencies of MacGarry. Thus, MacGarry in view of Kleveland fails to support prima facie 35 U.S.C. 103 rejection of claim 1, as currently amended. Independent claims 12 and 18, as currently amended, include similar subject matter as emphasized above for claim 1. Also, claims 2-11, 13-17, and 19-20 depend on claims 1, 12 or 18. Therefore, Applicant requests that the 35 U.S.C. 103 rejections of claims 1-20 be withdrawn.
Conclusion
Applicant's arguments filed 02/11/2026 regarding the prior art rejections of Claims 1 – 20 have been fully considered, but they are not persuasive.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/V.P./Examiner, Art Unit 2111
/GUERRIER MERANT/Primary Examiner, Art Unit 2111 5/11/2026
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