Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This Office Action responds to the Amendment filed on 10/30/2025 and IDS filed 12/02/2025. Applicant’s remarks are addressed in the Response to Applicant’s Remarks section cited below.
Claims 1-20 are pending.
Double Patenting
3. A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
4. Claim 18 is provisionally rejected under 35 U.S.C. 101 as claiming the same invention as that of claim 20 of copending Application No. 17/846,341 (reference application). This is a provisional statutory double patenting rejection since the claims directed to the same invention have not in fact been patented.
5. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
6. Claims 1, 4-10, and 12-17 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 5, 6-11, 15, 16, 17, and 19 of copending Application No. 17/846,341 in view of Brandonisio (U.S. Pub. No. 2020/0328750 A1). The copending application discloses receiving a circuit representation comprising a node and a feedback representation associated with the node; simulating operation of a circuit in the circuit representation; and in response to the simulated circuit generating an output at the node associated with the feedback representation, providing simulated feedback to the simulated circuit at the node that correspond to the correspond to the limitations of the current application, however the copending application does not disclose that the feedback representation is a mixed signal. However, Brandonisio discloses a mixed signal feedback representation (See Figure 7 & Para [0050]-[0057], i.e. PLL model 720…emulate a first actual internal PLL … received from digital PLL…on a first estimated analog PLL). Therefore, it obvious to incorporate the teaching of Brandonisio into the copending application because it would optimize a device for better performance (See Para [0001]).
This is a provisional nonstatutory double patenting rejection.
Claim Rejections - 35 USC § 102
7. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
8. Claim(s) 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Brandonisio (U.S. Pub. No. 2020/0328750 A1).
As per claim 18, Brandonisio discloses:
An emulation model comprising:
a circuit representation comprising a node (See Figure 7 & Para [0050]-[0057], i.e. PLL model 720…emulate a first actual internal PLL … received from digital PLL…on a first estimated analog PLL –[prior art emulate PLL include digital and analog being the mixed signal, prior art emulate a PLL signal being the node as cited above]); and
a feedback representation associated with the node of the circuit representation (See Figure 7 & Para [0050]-[0057], i.e. PLL model 720…emulate a first actual internal PLL … received from digital PLL…on a first estimated analog PLL –[prior art emulate PLL include digital and analog being the mixed signal, prior art emulate a PLL signal being the node as cited above]),
wherein the feedback representation is configured to provide feedback to a circuit in the circuit representation (See Figure 7, i.e. prior art feedback from &7344 in 730 to block 720 & See Para [0050]-[0057], i.e. minimizer 734 is also configured to update the estimated analog PLL parameter) in response to the circuit generating a signal at the node (See Figure 7, i.e. output from DCO 722 & See Para [0050]-[0057]).
As per claim 19, Brandonisio discloses all of the features of claim 18 as discloses above wherein Brandonisio also discloses equivalence constraints for one or more components of the circuit representation and the feedback representation (See Figure 7 & Para [0050]-[0057], i.e. PLL model 720…emulate a first actual internal PLL … received from digital PLL…on a first estimated analog PLL –[prior art apply similar input (constraint) to both 720 and 730 – considered as equivalence constraints]).
As per claim 20, Brandonisio discloses all of the features of claim 19 as discloses above wherein Brandonisio also discloses wherein the equivalence constraints are manually configurable (See Figure 7 & Para [0050]-[0057], i.e. PLL model 720…emulate a first actual internal PLL … received from digital PLL…on a first estimated analog PLL, See Para [0017], i.e. configured to emulate one or more internal PLL signals).
Allowable Subject Matter
9. Claims 2, 3, and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
10. Claims 1, 4-10, and 12-17 would be allowable if overcome the rejection(s) under Double Patenting, set forth in this Office action.
11. The following is a statement of reasons for the indication of allowable subject matter: Applicant’s remarks (Pages 6-10) with respect to claims 1-17 are persuasive.
Response to Applicant’s Remarks
12. With respect to Applicant’s remarks, the following are addressed:
Applicant’s arguments (Pages 6-10 of Remarks filed 10/30/2025), with respect to independent claims 1 and 10 have been considered and are persuasive. Claims 1 and 10 are now indicated as being allowable if to overcome the rejection(s) under Double Patenting, set forth in this Office action.
The rejection of claims 18-20 is maintained under prior art Brandonisio (U.S. Pub. No. 2020/0328750 A1), as the arguments that the prior art does not teach “receiving a circuit representation comprising a node and a mixed signal feedback representation associated with the node; simulating operation of a circuit in the circuit representation to generate a simulated circuit; and in response to the simulated circuit generating an output at the node associated with the mixed signal feedback representation, providing simulated mixed signal feedback to the simulated circuit at the node” does not apply to independent claim 18, as independent claim 18 is not directed to any simulation and/or having simulation circuit.
With respect to claim 18, prior art Brandonisio teach having a circuit representation comprising a node (See Figure 7, i.e. 722 is considered as the circuit presentation). Because Figure 7 illustrated a block diagram of a circuit, it is considered as the circuit representation of the claim.
Prior art Brandonisio also teach a feedback representation associated with the node of the circuit representation (See Figure 7, i.e. feedback 730).
Prior art Brandonisio also teach wherein the feedback representation is configured to provide feedback to a circuit in the circuit representation (See Figure 7, i.e. prior art feedback from &7344 in 730 to block 720 & See Para [0050]-[0057], i.e. minimizer 734 is also configured to update the estimated analog PLL parameter) in response to the circuit generating a signal at the node (See Figure 7, i.e. output from DCO 722 & See Para [0050]-[0057]).
Therefore, prior art Brandonisio have been shown to discloses the limitations of independent claim 18 – therefore the rejection of claims 18-20 is maintained under prior art Brandonisio as cited above.
Double Patenting rejection of claims 1, 4-10, and 12-18 are maintained as cited above, as Applicant’s did not file Terminal Disclaimer in the current application.
Conclusion
13. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
14. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NHA T NGUYEN whose telephone number is (571)270-1405. The examiner can normally be reached M-F 8:00AM-5:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NHA T NGUYEN/Primary Examiner, Art Unit 2851