Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This Office Action responds to the Request For Continued Examination filed on 7/02/2026 and IDS filed on 7/02/2026. Claims 1-20 are pending.
Remarks
Applicant’s arguments with respect to claim(s) 18-20 have been considered but are moot in view of new ground of rejection as cited below:
Claim(s) 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Verma (U.S. Pub. No. 2018/0225394 A1) in view of Verambally et al. (“Optimising Design Verification Using Machine Learning: An Open Source Solution”, by Samhita Varambally B. and Naman Sehgal, arXiv, December 4, 2020).
Double Patenting rejection of the claims have been withdrawn, as Applicant filed Terminal Disclaimer.
Claims 1-17 are now indicated as allowed.
The rejection of claims 18-20 are as cited below under the new ground of rejection. This office action is Non-Final.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Verma (U.S. Pub. No. 2018/0225394 A1) in view of Verambally et al. (“Optimising Design Verification Using Machine Learning: An Open Source Solution”, by Samhita Varambally B. and Naman Sehgal, arXiv, December 4, 2020).
As per claim 18, Verma discloses:
An emulation model (See Figure 3 & Para [0017], i.e. the design verification tool 300 can be implemented in an emulation system) comprising:
a circuit representation comprising a node, the circuit representation comprising a data representation of a circuit (See Para [0018], i.e. circuit design 301, which can describe an electronic device both in terms of an exchange of data signals between components in the electronic device… circuit design 301 can model the electronic device at a register transfer level (RTL), for example, with code in a hardware description language (HDL)); and
test bench associated with the node of the circuit representation (See Para [0019], i.e. The design verification tool 300 can receive a test bench 302 capable of defining test stimulus, for example, clock signals, activation signals, power signals, control signals, and data signals that, when grouped, may form test bench transactions capable of prompting operation of the circuit design 301 in a verification environment, such as a simulation environment or an emulation environment),
Verma does not teaches: a feedback representation associated with the node of the circuit representation, wherein the feedback representation is configured to provide feedback to the node of the circuit representation in response to the circuit generating a signal at the node.
However, Verambally teaches: a feedback representation associated with the node of the circuit representation, wherein the feedback representation is configured to provide feedback to the node of the circuit representation in response to the circuit generating a signal at the node (See Figure 1, i.e. test bench & Section III, i.e. C. Evaluation… a multiplexer is used to switch to the ML based inputs received through feedback from the model during the verification test phase [Verambally teaches that test bench include feedback loop (See Figure 1), that would feedback stimulus response to DUT (circuit design – data representation) in response to the circuit generating a signal at the node, therefore the combination of Verambally into Verma, would allow test bench of Verma to include the feedback representation as cited above]).
Therefore, it would have been obvious to a person of ordinary skill in the
art at the effective filing date of the invention incorporate the teaching of Verambally into
the teaching of Verma because it would allow engineer to employs machine learning to
increase efficiency in catching bugs and speeds up a complete verification cycle by
accelerating coverage convergence of a circuit design (See Section I. Introduction).
As per claim 19, Verma and Verambally discloses all of the features of claim 18 as discloses above wherein Verambally also discloses equivalence constraints for one or more components of the circuit representation and the feedback representation (See Section II & III, i.e. Coverage driven Constrained Random Stimuli, as directed tests on the increasingly large and complex SoCs).
As per claim 20, Verma and Verambally discloses all of the features of claim 19 as discloses above wherein Verambally also discloses wherein the equivalence constraints are manually configurable (See Section II & III, i.e. In Constrained Random Verification, one often has to manually update constraints in order to target coverage holes and hit corner cases).
Allowable Subject Matter
Claims 1-17 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: The prior art does not teach the limitations recited in independent claims 1 and 10, wherein claims 2-9 depend on claim 1 – wherein claims 11-17 depend on independent claim 10.
Conclusion
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/NHA T NGUYEN/Primary Examiner, Art Unit 2851
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