DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Claims 1-20 are currently pending in the application filed November 22, 2022.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 11/22/2022 have been considered by the Examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to show 324D in Figure 3 as described in the specification. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the multiple images involving multiple chips must be shown or the feature(s) canceled from the claim 8. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
“An adversary can conceivable replace” should be “An adversary can conceivably replace”
“One of more different wafer features” should be written as “one or more different wafer features”
“cab be a notch” should be “can be a notch”
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier, as explained in MPEP § 2181, subsection I (note that the list of generic placeholders below is not exhaustive, and other generic placeholders may invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph):
A. The Claim Limitation Uses the Term "Means" or "Step" or a Generic Placeholder (A Term That Is Simply A Substitute for "Means")
With respect to the first prong of this analysis, a claim element that does not include the term "means" or "step" triggers a rebuttable presumption that 35 U.S.C. 112(f) does not apply. When the claim limitation does not use the term "means," examiners should determine whether the presumption that 35 U.S.C. 112(f) does not apply is overcome. The presumption may be overcome if the claim limitation uses a generic placeholder (a term that is simply a substitute for the term "means"). The following is a list of non-structural generic placeholders that may invoke 35 U.S.C. 112(f): "mechanism for," "module for," "device for," "unit for," "component for," "element for," "member for," "apparatus for," "machine for," or "system for." Welker Bearing Co., v. PHD, Inc., 550 F.3d 1090, 1096, 89 USPQ2d 1289, 1293-94 (Fed. Cir. 2008); Mass. Inst. of Tech. v. Abacus Software, 462 F.3d 1344, 1354, 80 USPQ2d 1225, 1228 (Fed. Cir. 2006); Personalized Media, 161 F.3d at 704, 48 USPQ2d at 1886–87; Mas-Hamilton Group v. LaGard, Inc., 156 F.3d 1206, 1214-1215, 48 USPQ2d 1010, 1017 (Fed. Cir. 1998). Note that there is no fixed list of generic placeholders that always result in 35 U.S.C. 112(f) interpretation, and likewise there is no fixed list of words that always avoid 35 U.S.C. 112(f) interpretation. Every case will turn on its own unique set of facts.
Such claim limitation(s) is/are:
A. "A wafer verification system" in claims 11 and 20 and dependent claims described in paragraph [0006] and implemented on hardware disclosed in paragraphs [0006] (“The system includes a wafer imaging system, disposed at each of a plurality of foundries performing the split manufacturing of a wafer, for capturing images of one or more different wafer features during manufacturing using a fiducial marker. The system further includes a hardware processor, disposed at each of the plurality of foundries except a first foundry, for comparing the images from one stage to a next stage for at least two stages of manufacturing to verify a wafer identification based on a matching of the one of more different wafer features from the one stage to the next stage.”)
B. " a wafer imaging system" in claims 11 and 20 and dependent claims are not described in the specifications. Read 112A and 112B below for more information.
Claim Rejections - 35 USC § 112
Regarding §112(a):
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Section IV. of §2181 reads: DETERMINING WHETHER 35 U.S.C. 112(a) or Pre-AIA 35 U.S.C. 112, FIRST PARAGRAPH SUPPORT EXISTS
“When a claim containing a computer-implemented 35 U.S.C. 112(f) claim limitation is found to be indefinite under 35 U.S.C. 112(b) for failure to disclose sufficient corresponding structure (e.g., the computer and the algorithm) in the specification that performs the entire claimed function, it will also lack written description under section 112(a). See MPEP § 2163.03, subsection VI. Examiners should further consider whether the disclosure contains sufficient information regarding the subject matter of the claims as to enable one skilled in the pertinent art to make and use the full scope of the claimed invention in compliance with the enablement requirement of section 112(a). See MPEP § 2161.01, subsection III, and MPEP § 2164.08.”
“Wafer Imaging System” and derivations thereof raises concerns with discerning the type of imaging system used to capture the images of one or more different wafer features during manufacturing using fiducial marker. The wafer image system additionally lacks support in the specification for the corresponding structure, material, or acts and does not disclose support to one of ordinary skill in the art for making and using the components of the wafer imaging system. Thus, the device or material performing the functionality, as well as the claimed functionality lack written description.
Regarding §112(b):
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Section II of §2181 reads:
II. DESCRIPTION NECESSARY TO SUPPORT A CLAIM LIMITATION WHICH INVOKES 35 U.S.C. 112(f) or Pre-AIA 35 U.S.C. 112, SIXTH PARAGRAPH
A. The Corresponding Structure Must Be Disclosed In the Specification Itself in a Way That One Skilled In the Art Will Understand What Structure Will Perform the Recited Function
The proper test for meeting the definiteness requirement is that the corresponding structure (or material or acts) of a means- (or step-) plus-function limitation must be disclosed in the specification itself in a way that one skilled in the art will understand what structure (or material or acts) will perform the recited function. See Atmel Corp. v. Information Storage Devices, Inc., 198 F.3d 1374, 1381, 53 USPQ2d 1225, 1230 (Fed. Cir. 1999).
As can be seen from the citations of the specification and the written description failing to contain sufficient information regarding the subject matter of the claims as to enable one skilled in the pertinent art to make and use the full scope of the claimed invention, the specification fails to set forth the corresponding structure, material, or acts in compliance with 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph, and the claim limitation cannot "be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.” “Wafer Imaging System” additionally lacks support in the specification for the corresponding structure, material, or acts, and does not disclose sufficient corresponding structure performing the entire claimed function to one of ordinary skill in the art for making and using the components of the unit which necessitate this unit.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 7, 8, 11 and 17 are rejected under 35 U.S.C. 102 as being unpatentable over Lie (US11079337B1).
Regarding Claim 1, Lie teaches;
A method of wafer verification (Lie, [Col 1 line 51];” In one aspect of the invention, a method for wafer authentication is provided.”) for split manufacturing, comprising: (Lie, Col 1 line 20;” a given device design can become 20 compromised by means of introducing different masks and/ or different wafers with slight changes in the design at one or more point during the fabrication process in an untrusted fabrication model. Thus, verification of the device design is an important step during fabrication.”)
capturing images (Lie, [Col 3 Line 10]; “this detection process can involve taking images of the wafer during each level of the fabrication process.”) of one or more different wafer features during manufacturing using a fiducial marker; (Lie, Col 4 line 27;” In step 102, reference structures are placed across the chips. Preferably, placement of the reference structures occurs at each level of fabrication of the chips on the wafer or, optionally, at critical levels of the process.”
and comparing the images from one stage to a next stage (Lie, [Col 5 line 41];] level N+1 fabrication) for at least two stages of manufacturing to verify a wafer identification based on a matching of the one of more different wafer features from the one stage to the next stage. (Lie, [ Col 5 Line 38];” For instance, overlay/scatterometry measurements of the reference structures placed across the chips at level N can be made after level N fabrication, and again after level N+1 fabrication. The wafer is then authenticated if, and only if, the overlay/scatterometry measurements made at these two different points in the fabrication flow are the same or can be correlated. This ensures that it is the same wafer being processed both at level N and at level N+1.”)
Regarding Claim 7, Lie teaches:
wherein the fiducial mark (Lie, [Col 4 Line 27];” In step 102, reference structures are placed across the chips.”) is placed on the images for reference location and reproducibility. (Lie, [Col 4 Line 45]; “In step 106, overlay and/or scatterometry measurements of the reference structures are performed.”)
Regarding Claim 8, Lie teaches:
wherein said capturing step captures multiple images involving multiple chips in order to enhance a uniqueness of a wafer identification. (Lie, [Col 4 Line 64];” Given the above overview of the present techniques, FIG. 65 2 is a diagram illustrating placement of the present reference structures (e.g., overlay marks and/or scatterometry macros) across chips at each level of the fabrication flow for fingerprinting and authentication via overlay and scatterometry measurement. “)
Regarding Claim 11, Lie teaches:
A wafer verification system for split manufacturing, comprising: (Lie, [Col 10 Line 52]; “The present invention may be a system, a method, and/or a computer program product.”)
a wafer imaging system, disposed at each of a plurality of foundries (Lie, col 1 line 28;” Further, a foundry typically provides sampling of the output, rather than a comprehensive design verification.”) performing the split manufacturing of a wafer, for capturing images of one or more different wafer features during manufacturing using a fiducial marker; (Lie, [Col 4 line 27];” In step 102, reference structures are placed across the chips. Preferably, placement of the reference structures occurs at each level of fabrication of the chips on the wafer or, optionally, at critical levels of the process.”)
and a hardware processor (Lie, [Col 11 Line 66]; “These computer readable program instructions may be provided to a processor of a general-purpose computer”), disposed at each of the plurality of foundries except a first foundry, for comparing the images from one stage to a next stage for at least two stages of manufacturing to verify a wafer identification based on a matching of the one of more different wafer features from the one stage to the next stage. (Lie, [Col 5 Line 38];” For instance, overlay/scatterometry measurements of the reference structures placed across the chips at level N can be made after level N fabrication, and again after level N+1 fabrication. The wafer is then authenticated if, and only if, the overlay/scatterometry measurements made at these two different points in the fabrication flow are the same or can be correlated. This ensures that it is the same wafer being processed both at level N and at level N+1.”)
Regarding Claim 17, Lie teaches:
wherein the wafer imaging system at different ones of the plurality of foundries (Lie, [Col 1 line 28];” Further, a foundry typically provides sampling of the output, rather than a comprehensive design verification.”) captures multiple images involving multiple chips in order to enhance a uniqueness of a wafer identification. (Lie, [Col 4 Line 64];” Given the above overview of the present techniques, FIG. 65 2 is a diagram illustrating placement of the present reference structures (e.g., overlay marks and/or scatterometry macros) across chips at each level of the fabrication flow for fingerprinting and authentication via overlay and scatterometry measurement. “)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2, 3, 6, 12, 13, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Lie (US11079337B1) further in view of Stokkan (Investigation of the Grain Boundary Character and Dislocation Density of Different Types of High Performance Mult crystalline Silicon).
Regarding Claim 2, Lie fails to teach:
wherein the one or more different wafer features comprise a grain distribution.
Stokkan teaches:
wherein the one or more different wafer features comprise a grain distribution. (Stokkan, [Page 2 Paragraph 2]; “Grain boundaries have a different structure and composition than before; whereas the large majority of grain boundaries used to be coincidence site lattice (CSL) boundaries, particularly of the Σ3 type, currently a much larger proportion of random angle grain boundaries (RAGB) is present.”)
Before the time of filing, it would have been obvious to one of ordinary skill in the art to combine Lie with Stokkan. The motivation for the combination is to be able include wafer with various grain distribution. (Stokkan, figure 2)
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Regarding claim 3, Lie fails to teach:
wherein the grain distribution comprises a grain distribution parameter selected from the group consisting of grain shapes and grain sizes.
Stokkan teaches:
wherein the grain distribution comprises a grain distribution parameter selected from the group consisting of grain shapes (Stokkan, [Page 10 Paragraph 2]; “The latter two also have a prolonged grain shape; “) and grain sizes. (Stokkan, [Page 4 Paragraph 4]; “A visual impression of the grain size …grain images (IGI)”)
Before the time of filing, it would have been obvious to one of ordinary skill in the art to combine Lie with Stokkan. The motivation for the combination is to be able include various grain distribution consisting of grain shapes and grain sizes. (Stokkan, figure 1)
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Regarding Claim 6, Lie fails to teach:
wherein the one or more different wafer features comprise a grain crystallographic structure.
Stokkan teaches:
wherein the one or more different wafer features comprise a grain crystallographic structure. (Stokkan, [Page 4 Paragraph 5]; “…where all individual grains are coloured with a unique colour, independent of the crystal orientation”.)
Before the time of filing, it would have been obvious to one of ordinary skill in the art to combine Lie with Stokkan. The motivation for the combination is to be able include wafer with grain crystallographic structure. (Stokkan, [Page 4 Paragraph 5]; “In these IGIs, all crystals of different orientation are defined as grains”)
Regarding Claim 12, Lie fails to teach:
wherein the one or more different wafer features comprise a grain distribution.
Stokkan teaches:
wherein the one or more different wafer features comprise a grain distribution. (Fraser, [Page 2 Paragraph 2]; “Grain boundaries have a different structure and composition than before; whereas the large majority of grain boundaries used to be coincidence site lattice (CSL) boundaries, particularly of the Σ3 type, currently a much larger proportion of random angle grain boundaries (RAGB) is present.”)
Before the time of filing, it would have been obvious to one of ordinary skill in the art to combine Lie with Stokkan. The motivation for the combination is to be able include wafer with various grain distribution. (Stokkan, figure 2)
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Regarding claim 13, Lie fails to teach:
wherein the grain distribution comprises a grain distribution parameter selected from the group consisting of grain shapes and grain sizes.
Stokkan teaches:
wherein the grain distribution comprises a grain distribution parameter selected from the group consisting of grain shapes (Stokkan, [Page 10 Paragraph 2]; “The latter two also have a prolonged grain shape; “) and grain sizes. (Stokkan, [Page 4 Paragraph 4]; “A visual impression of the grain size …grain images (IGI)”)
Before the time of filing, it would have been obvious to one of ordinary skill in the art to combine Lie with Stokkan. The motivation for the combination is to be able include various grain distribution consisting of grain shapes and grain sizes. (Stokkan, figure 1)
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Regarding Claim 16, Lie fails to teach:
wherein the one or more different wafer features comprise a grain crystallographic structure.
Stokkan teaches:
wherein the one or more different wafer features comprise a grain crystallographic structure. (Stokkan, [Page 4 Paragraph 5]; “…where all individual grains are coloured with a unique colour, independent of the crystal orientation”.)
Before the time of filing, it would have been obvious to one of ordinary skill in the art to combine Lie with Stokkan. The motivation for the combination is to be able include wafer with grain crystallographic structure. (Stokkan, [Page 4 Paragraph 5]; “In these IGIs, all crystals of different orientation are defined as grains”)
Claims 4, 5, 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Lie (US11079337B1) further in view of Art 2 (Wafer-Level Test Design for Reliability - Chip Scale Review)
Regarding Claim 4, Lie fails to teach:
wherein the one or more different wafer features comprise an electrical test probe mark distribution
Art 2 teaches:
wherein the one or more different wafer features comprise an electrical test probe mark distribution. (Art 2, [Page 12 Col 2 Paragraph 5]; “Probe mark inspection is a “go, no-go” check that is performed as an all-surface inspection just on the wafer”)
Before the time of filing, it would have been obvious to one of ordinary skill in the art to combine Lie with Art 2. The motivation for the combination is to be able include wafer with Electrical test probe mark distribution. (Art 2, [Page 3 Col 1 Paragraph 2];” Probe mark analysis takes the probe card and evaluates how it works in the whole system;”)
Regarding Claim 5, Lie fails to teach:
wherein the one or more different wafer features comprise wafer bevel edge characteristics.
Art 2 teaches:
wherein the one or more different wafer features comprise wafer bevel edge characteristics. (Art 2, [Page 16 Col 1 Paragraph 4]; “Wafers are beveled on the edge for a number of reasons.”)
Before the time of filing, it would have been obvious to one of ordinary skill in the art to combine Lie with Art 2. The motivation for the combination is to be able include wafer with bevel edge characteristics. (Art 2, [Page 3 Col 1 Paragraph 2];” … the “device” wafers have their beveled edges trimmed away”)
Regarding Claim 14, Lie fails to teach:
wherein the one or more different wafer features comprise an electrical test probe mark distribution.
Art 2 teaches:
wherein the one or more different wafer features comprise an electrical test probe mark distribution. (Art 2, [Page 12 Col 2 Paragraph 5]; “Probe mark inspection is a “go, no-go” check that is performed as an all-surface inspection just on the wafer”)
Before the time of filing, it would have been obvious to one of ordinary skill in the art to combine Lie with Art 2. The motivation for the combination is to be able include wafer with Electrical test probe mark distribution. (Art 2, [Page 3 Col 1 Paragraph 2];” Probe mark analysis takes the probe card and evaluates how it works in the whole system;”)
Regarding Claim 15, Lie fails to teach:
wherein the one or more different wafer features comprise wafer bevel edge characteristics.
Art 2 teaches:
wherein the one or more different wafer features comprise wafer bevel edge characteristics. (Art 2, [Page 16 Col 1 Paragraph 4]; “Wafers are beveled on the edge for a number of reasons.”)
Before the time of filing, it would have been obvious to one of ordinary skill in the art to combine Lie with Art 2. The motivation for the combination is to be able include wafer with bevel edge characteristics. (Art 2, [Page 3 Col 1 Paragraph 2];” … the “device” wafers have their beveled edges trimmed away”)
Claims 9, 10, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lie (US11079337B1) further in view of Zhang (An On-Chip Dynamically Obfuscated Wrapper for Protecting Supply Chain Against IP and IC Piracies).
Regarding Claim 9, Lie fails to teach:
wherein the method is performed across multiple foundries, with each of the multiple foundries performing said comparing step.
Zhang teaches:
wherein the method is performed across multiple foundries (Zhang, [Page 2457 Paragraph 1];” The FEOL layers are fabricated in an untrusted foundry where the IC designer does not reveal the full design to keep the original functionality of the circuit unknown. On the other hand, the BEOL layers are fabricated in a trusted foundry”), with each of the multiple foundries performing said comparing step (Zhang, [Page 2461 Col 1 Paragraph 4];” If the footprint does not match the reported test result, the activation request Fig. 6. Stages of DOST-based test methodology. will be refused as shown by the IC marked with ECID2 shown in Fig. 9.”)
Before the time of filing, it would have been obvious to one of ordinary skill in the art to combine Lie with Zhang. The motivation for the combination is to be able comparing step in multiple foundries (Zhang, Figure 9)
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Regarding Claim 10, Lie fails to teach:
wherein each of the multiple foundries creates its own unique fingerprint based on the one or more different wafer features,
and wherein a subsequent processing of the wafer by a subsequent foundry removes a prior fingerprint and creates a new unique fingerprint for use in an evaluation by a next foundry.
Zhang teaches:
wherein each of the multiple foundries creates its own unique fingerprint based on the one or more different wafer features, (Zhang, [Page 2466 Col 1 Paragraph 2];” the structural test footprints are unpredictable and unique from device to device and not manageable by the foundry”)
and wherein a subsequent processing of the wafer by a subsequent foundry removes a prior fingerprint and creates a new unique fingerprint for use in an evaluation by a next foundry. (Zhang, [Page 2459 Col 1 Paragraph 1];” After the test time window, because of aging, the output of AS-PUF is changed from temporary fingerprint to a significantly different aged fingerprint”)
Before the time of filing, it would have been obvious to one of ordinary skill in the art to combine Lie with Zhang. The motivation for the combination is to be able to remove a prior fingerprint and create a new fingerprint as mentioned in the art when different aged fingerprint was created. (Zhang, [Page 2459 Col 2 Paragraph 1]; “from temporary fingerprint to a significantly different aged fingerprint.”)
Regarding Claim 18, Lie fails to teach:
wherein each of the plurality of foundries creates its own unique fingerprint based on the one or more different wafer features.
Zhang teaches:
wherein each of the plurality of foundries creates its own unique fingerprint based on the one or more different wafer features. (Zhang, [Page 2466 Col 1 Paragraph 2];” the structural test footprints are unpredictable and unique from device to device and not manageable by the foundry”)
Before the time of filing, it would have been obvious to one of ordinary skill in the art to combine Lie with Zhang. The motivation for the combination is to be able create new fingerprint from one or more different wafer features. (Zhang, [Page 2457 Col 1 Paragraph 2]; “Usually, the unique fingerprint generated by an on chip physical unclonable function”)
Regarding Claim 19, Lie fails to teach:
wherein a subsequent processing of the wafer by a subsequent foundry removes a prior fingerprint and creates a new unique fingerprint for use in an evaluation by a next foundry.
Zhang teaches:
wherein a subsequent processing of the wafer by a subsequent foundry removes a prior fingerprint and creates a new unique fingerprint for use in an evaluation by a next foundry. (Zhang, [Page 2459 Col 1 Paragraph 1];” After the test time window, because of aging, the output of AS-PUF is changed from temporary fingerprint to a significantly different aged fingerprint”)
Before the time of filing, it would have been obvious to one of ordinary skill in the art to combine Lie with Zhang. The motivation for the combination is to be able to remove a prior fingerprint and create a new fingerprint as mentioned in the art when different aged fingerprint was created. (Zhang, [Page 2459 Col 2 Paragraph 1]; “from temporary fingerprint to a significantly different aged fingerprint.”)
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Lie (US11079337B1), Art 2 (Wafer-Level Test Design for Reliability - Chip Scale Review) and Stokkan (Investigation of the Grain Boundary Character and Dislocation Density of Different Types of High Performance Mult crystalline Silicon)
Regarding Claim 20, Lie teaches:
A wafer verification system for split manufacturing, comprising: (Lie, [Col 10 Line 52]; “The present invention may be a system, a method, and/or a computer program product.”)
a wafer imaging system, disposed at each of a plurality of foundries (Lie, col 1 line 28;” Further, a foundry typically provides sampling of the output, rather than a comprehensive design verification.”) performing the split manufacturing of a wafer, for capturing images of one or more different wafer features during manufacturing using a fiducial marker; and (Lie, [Col 4 line 27];” In step 102, reference structures are placed across the chips. Preferably, placement of the reference structures occurs at each level of fabrication of the chips on the wafer or, optionally, at critical levels of the process.”
a hardware processor (Lie, [Col 11 Line 66]; “These computer readable program instructions may be provided to a processor of a general-purpose computer”), disposed at each of the plurality of foundries except a first foundry, for comparing the images from one stage to a next stage for at least two stages of manufacturing to verify a wafer identification based on a matching of the one of more different wafer features from the one stage to the next stage. (Lie, [Col 5 Line 38];” For instance, overlay/scatterometry measurements of the reference structures placed across the chips at level N can be made after level N fabrication, and again after level N+1 fabrication. The wafer is then authenticated if, and only if, the overlay/scatterometry measurements made at these two different points in the fabrication flow are the same or can be correlated. This ensures that it is the same wafer being processed both at level N and at level N+1.”)
Lie fails to teach:
wherein the one or more different wafer features are selected from the group consisting of a grain distribution
Stokkan teaches:
wherein the one or more different wafer features are selected from the group consisting of a grain distribution, (Stokkan, [Page 2 Paragraph 2]; “Grain boundaries have a different structure and composition than before; whereas the large majority of grain boundaries used to be coincidence site lattice (CSL) boundaries, particularly of the Σ3 type, currently a much larger proportion of random angle grain boundaries (RAGB) is present.”)
Before the time of filing, it would have been obvious to one of ordinary skill in the art to combine Lie with Stokkan. The motivation for the combination is to be able include wafer with various grain distribution. (Stokkan, figure 2)
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Stokkan fails to teach:
an electrical test probe mark distribution,
Art 2 teaches:
an electrical test probe mark distribution, (Art 2, [Page 12 Col 2 Paragraph 5]; “Probe mark inspection is a “go, no-go” check that is performed as an all-surface inspection just on the wafer”)
wafer bevel edge characteristics, (Art 2, [Page 16 Col 1 Paragraph 4]; “Wafers are beveled on the edge for a number of reasons.”)
Before the time of filing, it would have been obvious to one of ordinary skill in the art to combine Lie with Stokkan and Art 2. The motivation for the combination is to be able include wafer with Electrical test probe mark distribution (Art 2, [Page 3 Col 1 Paragraph 2];” Probe mark analysis takes the probe card and evaluates how it works in the whole system;”) and wafer edge beveled characteristics (Art 2, [Page 3 Col 1 Paragraph 2];” … the “device” wafers have their beveled edges trimmed away”)
Combination of Lie, Art 2 and, Stokkan teaches:
and a grain crystallographic structure. (Stokkan, [Page 4 Paragraph 5]; “…where all individual grains are coloured with a unique colour, independent of the crystal orientation”.)
Before the time of filing, it would have been obvious to one of ordinary skill in the art to combine Lie and Art 2 with Stokkan. The motivation for the combination is to be able include wafer with grain crystallographic structure. (Stokkan, [Page 4 Paragraph 5]; “In these IGIs, all crystals of different orientation are defined as grains”)
Conclusion
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/SHIVANGI SARKAR/Examiner, Art Unit 2666
/EMILY C TERRELL/Supervisory Patent Examiner, Art Unit 2666