DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 9 is objected to because of the following informalities:
Claim 9 line 1 change “obtaning” to “obtaining”.
Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding claim 1, at Step 1, the claim is directed to a method, which is a statutory category of invention (Process).
At Step 2A Prong 1, Examiner notes that the claims are directed towards an abstract idea. The claim language has been reproduced below:
A method performing floating-point operations, the method comprising: obtaining operands, wherein each of the operands is expressed in a floating-point format (mathematical relationship);
calculating a gain based on a range of operand exponents for the operands (mathematical calculation);
generating intermediate values by applying the gain to the operands (mathematical calculation), wherein each of the intermediate values is expressed in a fixed-point format (mathematical relationship);
generating a fixed-point result value by performing an arithmetic operation on the intermediate values (mathematical calculation), wherein the fixed-point result value is expressed in the fixed-point format (mathematical relationship);
and generating a floating-point output value from the fixed-point result value (mathematical calculation), wherein the floating-point output value is expressed in the floating-point format (mathematical relationship).
At Step 2A Prong 2, the additional elements are bolded above. The additional elements do not integrate the abstract ideas into a practical application because they are recited at a high level of generality and do not impose any meaningful limits on practicing the abstract ideas. See MPEP 2106.05(f). The limitation “obtaining operands” is merely an insignificant extra-solution activity of data gathering. Even when viewed in combination, these additional elements do not integrate the recited judicial exception into a practical application and the claim is directed to the judicial exception.
At Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception As set forth in step 2A prong 2 analysis, the functions of “obtaining operands” is recognized by the courts as well-understood routine and conventional. See MPEP 2106.05(d)(II). Even when considered in combination, these additional elements represent mere instructions to apply an exception and insignificant extra-solution activity, which do not provide an inventive concept. The claim is not eligible.
Regarding claims 2-11, the claims merely recite functions for calculating the gain, generating the fixed-point result, generating the floating-point output value, and obtaining of the operands that further mathematically limit the mathematical concepts, or provide additional mathematical functions, of claim 1, They do not include additional elements that would require further analysis under steps 2A prong 2 and step 2B.
Regarding claim 12, at Step 1, the claim is directed to a system, which is a statutory category of invention (Machine).
At Step 2A Prong 1, Examiner notes that the claims are directed towards an abstract idea. The claim language has been reproduced below:
A system performing floating-point operations, the system comprising: a gain calculation circuit configured to obtain operands and calculate a gain based on a range of operand exponents (mathematical calculation), wherein each of the operands is expressed in a floating-point format (mathematical relationship);
a normalization circuit configured to generate intermediate values by applying the gain to the operands (mathematical calculation), wherein each of the intermediate values is expressed in a fixed-point format (mathematical relationship);
a fixed-point operation circuit configured to generate a fixed-point result value by performing an arithmetic operation on the intermediate values (mathematical calculation), wherein the fixed-point result value is expressed in the fixed-point format (mathematical relationship);
and a post-processing circuit configured to transform the fixed-point result value into a floating-point output value (mathematical calculation), wherein the floating-point output value is expressed in the floating-point format (mathematical relationship).
At Step 2A Prong 2, the additional elements are bolded above. The additional elements do not integrate the abstract ideas into a practical application because the computer elements, which are recited at a high level of generality, provide conventional computer functions that do not impose any meaningful limits on practicing the abstract ideas. See MPEP 2106.05(f). The limitations “gain calculation circuit”, “normalization circuit”, “fixed-point operation circuit”, and “post-processing circuit” are merely recited at a high level of generality that they are the equivalent of reciting “apply it” to the judicial exception. The limitation “obtain operands” is merely an insignificant extra-solution activity of data gathering. Even when viewed in combination, these additional elements do not integrate the recited judicial exception into a practical application and the claim is directed to the judicial exception.
At Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception. As set forth in step 2A prong 2 analysis, the functions of “obtain operands” is recognized by the courts as well-understood routine and conventional. See MPEP 2106.05(d)(II). Furthermore, the “gain calculation circuit”, “normalization circuit”, “fixed-point operation circuit”, and “post-processing circuit” are the equivalent of adding the words “apply it” to the judicial exception and are mere instructions to implement the abstract idea on a computer. Even when considered in combination, these additional elements represent mere instructions to apply an exception and insignificant extra-solution activity, which do not provide an inventive concept. The claim is not eligible.
Regarding claims 13-19, the claims merely recite functions for calculating the gain, generating the fixed-point result, generating the floating-point output value, and obtaining of the operands that further mathematically limit the mathematical concepts, or provide additional mathematical functions, of claim 1, They do not include additional elements that would require further analysis under steps 2A prong 2 and step 2B.
Regarding claim 20, the claim is directed to a system with a processor and a non-transitory storage medium that would execute the method of claim 1. All steps performed by the system of claim 20 execute the method in claim 1 as configured. The analysis of claim 1 applies equally to claim 20.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 9, 12, 19-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kaul et al. (US 20190294415 A1, hereinafter “Kaul”, provided in IDS filed 11/22/2022).
As per claim 1, Kaul teaches A method performing floating-point operations, the method comprising: obtaining operands, wherein each of the operands is expressed in a floating-point format (Kaul: Fig. 1; [0013]);
calculating a gain based on a range of operand exponents for the operands (Kaul: Fig. 1 element 30; [0014], wherein “maxexp” corresponds to the gain);
generating intermediate values by applying the gain to the operands, wherein each of the intermediate values is expressed in a fixed-point format (Kaul: [0016]);
and generating a floating-point output value from the fixed-point result value, wherein the floating-point output value is expressed in the floating-point format (Kaul: [0015]).
As per claim 9, Kaul teaches The method of claim 1, wherein the obtaning of the operands includes, for each of the operands: adding exponents of a pair of input values to generate a sum of exponents of the pair of input values (Kaul: Fig. 1, the addition of ea and eb);
and multiplying fractions of the pair of input values to generate a product of the fractions, wherein each of the pair of input values is expressed in the floating-point format (Kaul: Fig. 1 the multiplication of ma and mb).
As per claim 12, the claim is directed to a system that implements the same or similar features as the method of claim 1, and is therefore rejected for at least the same reasons therein. Furthermore, Kaul teaches “a gain calculation circuit” (Kaul: Fig. 1 element 30), “a normalization circuit” (Kaul: Fig. 1 global alignment section), “a fixed-point operation circuit” (Kaul: Fig. 1 Adder tree), and “a post-processing circuit” (Kaul: Fig. 1 Fixed-Point to FP32).
As per claim 19, the claim is directed to a system that implements the same or similar features as the method of claim 9, and is therefore rejected for at least the same reasons therein.
As per claim 20, the claim is directed to a system that implements the same or similar features as the method of claim 1, and is therefore rejected for at least the same reasons therein. Furthermore, Quesada teaches “a processor” (Kaul: [0018]) and “a non-transitory storage medium storing instructions” (Kaul: [0018]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3, 5, 13-14, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Kaul in view of Yi et al. (US 20220137922 A1, hereinafter “Yi”).
As per claim 2 Kaul teaches The method of claim 1,
However, while Kaul discloses using the maxexp to shift and convert the floating-point products ([0014]), Kaul does not teach wherein the calculating of the gain includes: obtaining a maximum value and a minimum value of the operand exponents; and calculating the gain based on a difference between the maximum value and the minimum value of the operand exponents.
Yi teaches wherein the calculating of the gain includes: obtaining a maximum value and a minimum value of the operand exponents (Yi: Fig. 8; [0087]);
and calculating the gain based on a difference between the maximum value and the minimum value of the operand exponents (Yi: [0088], equations 10-12, wherein the logarithm of a floating-point number is correlated to the exponent value of the floating-point number).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the maxexp calculation of Kaul with the scale factor calculation of Yi. One would have been motivated to combine these references because both references disclose calculating factors for floating-point to fixed-point conversion, and combining prior art elements according to known methods to yield predictable results (generating the factor for alignment).
As per claim 3, Kaul/Yi further teaches The method of claim 2, wherein the maximum value and the minimum value of the operand exponents are a maximum exponent and a minimum exponent of the floating-point format, respectively (Yi: [0087]).
As per claim 5, Kaul teaches The method of claim 1,
However, while Kaul discloses using the maxexp to shift and convert the floating-point products ([0014]), Kaul does not teach wherein the calculating of the gain based on the range of operand exponents includes calculating the gain based on a number of digits of the fixed-point format.
Yi teaches wherein the calculating of the gain based on the range of operand exponents includes calculating the gain based on a number of digits of the fixed-point format (Yi: Fig. 8 element 820; [0090]).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the maxexp calculation of Kaul with the scale factor calculation of Yi for at least the same reasons as discussed above in claim 2.
As per claims 13-14, the claims are directed to a system that implements the same or similar features as the method of claims 2-3, respectively, and are therefore rejected for at least the same reasons therein.
As per claim 16, the claim is directed to a system that implements the same or similar features as the method of claim 5, and is therefore rejected for at least the same reasons therein.
Claims 6, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kaul in view of StackOverflow (“How to calculate sum and average of positive o only negative integers the user inputs”, hereinafter “Stack”).
As per claim 6, Kaul teaches The method of claim 1,
However, while Kaul discloses an adder tree, Kaul does not explicitly disclose how the addition is performed. Thus, Kaul does not teach wherein the generating of the fixed-point result value by performing the arithmetic operation on the intermediate values includes: calculating a first sum of positive intermediate values among the intermediate values; calculating a second sum of negative intermediate values among the intermediate values; and calculating a sum of the intermediate values based on a difference between the first sum and the second sum.
Stack teaches wherein the generating of the fixed-point result value by performing the arithmetic operation on the intermediate values includes: calculating a first sum of positive intermediate values among the intermediate values (Stack: Zdzisław Śliwiński’s answer positiveSum);
calculating a second sum of negative intermediate values among the intermediate values (Stack: Zdzisław Śliwiński’s answer negativeSum);
and calculating a sum of the intermediate values based on a difference between the first sum and the second sum (Stack: Zdzisław Śliwiński’s answer final std::cout).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the adder tree of Kaul with the method of adding of Stack. One would have been motivated to combine these references because both references disclose adding multiple positive and negative values, and combining prior art elements according to known methods to yield predictable results (a method of adding mixed signed values).
As per claim 17, the claim is directed to a system that implements the same or similar features as the method of claim 6, and is therefore rejected for at least the same reasons therein.
Claims 7, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kaul in view of Pugh et al. (US 20210042087 A1, hereinafter “Pugh”).
As per claim 7, Kaul teaches The method of claim 1,
However, Kaul does not teach wherein the generating of the floating-point output value from the fixed-point result value includes: counting a number of continuous zeros including a most significant bit and excluding a sign bit of the fixed-point result value to generate a counted value; and calculating an exponent and a fraction of the floating-point output value based on the gain and the counted value.
Pugh teaches wherein the generating of the floating-point output value from the fixed-point result value includes: counting a number of continuous zeros including a most significant bit and excluding a sign bit of the fixed-point result value to generate a counted value (Pugh: Fig. 19 element 1920; [0100], [0104]);
and calculating an exponent and a fraction of the floating-point output value based on the gain and the counted value (Pugh: Fig. 19 elements 1925, 1930, 1935; [0097]; [0102]).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the Fixed-Point to FP32 conversion of Kaul with the fixed to floating-point conversion of Pugh. One would have been motivated to combine these references because both references disclose converting from fixed-point to floating-point, and the conversion method of Pugh reduces delay (Pugh: [0104]).
As per claim 18, the claim is directed to a system that implements the same or similar features as the method of claim 7, and is therefore rejected for at least the same reasons therein.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kaul in view of IEEE (IEEE Standard for Floating-Point Arithmetic, hereinafter “IEEE”).
As per claim 8, Kaul teaches The method of claim 1, wherein the generating of the floating-point output value from the fixed-point result value includes: setting the floating point output value to a value expressed in the floating-point format (Kaul: [0015]);
However, Kaul does not explicitly disclose handling floating-point exceptions. Thus, Kaul does not teach and indicating one of positive infinity and negative infinity, if the fixed-point result value exceeds a range of the floating-point format.
IEEE teaches and indicating one of positive infinity and negative infinity, if the fixed-point result value exceeds a range of the floating-point format (IEEE: pg. 21 convertFromInt; Section 7).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the Fixed-Point to FP32 conversion of Kaul with the exception handling of IEEE. One would have been motivated to combine these references because both references disclose converting to floating-point, and combining prior art elements according to known methods to yield predictable results (handling exceptions from the conversion).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kaul in view of Brunie (US 20200409661 A1, hereinafter “Brunie”, provided in IDS filed 06/16/2026).
As per claim 10, Kaul teaches The method of claim 9, and shifting the product of the fractions based on the sum of exponents of the pair of input values (Kaul: Fig. 1 alignment units).
However, Kaul does not teach wherein the obtaining of the operands further includes, for each of the operands: determining a sign bit based on sign bits of the pair of input values;
Brunie teaches wherein the obtaining of the operands further includes, for each of the operands: determining a sign bit based on sign bits of the pair of input values (Brunie: Fig. 5);
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the floating-point multiplication of Kaul with the floating-point multiplication of Brunie. One would have been motivated to combine these references because both references disclose multiplication of floating-point numbers, and combining prior art elements according to known methods to yield predictable results (handling signed floating-point values).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kaul in view of Barat Quesada (US 20160188293 A1, hereinafter “Quesada”).
As per claim 11, Kaul teaches The method of claim 1,
However, while Kaul discusses using fixed-point values, Kaul does not explicitly discuss the fixed-point format. Thus, Kaul does not teach wherein the fixed-point format is a sign-magnitude format.
Quesada teaches wherein the fixed-point format is a sign-magnitude format (Quesada: Fig. 5 element 502).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the fixed-point format of Kaul with the fixed-point format of Quesada. One would have been motivated to combine these references because both references disclose calculating floating-point to fixed-point conversion, and combining prior art elements according to known methods to yield predictable results (the format of the fixed-point values).
Allowable Subject Matter
Claims 4, 15, would be allowable if rewritten to overcome the rejections under 35 USC 101 set forth in this Office Action and in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claims 4, 15, the prior art of record does not teach or suggest a combination as claimed including: the calculating of the gain based on the difference between the maximum value and the minimum value of the operand exponents includes subtracting 1 from a difference between a maximum exponent of the half-precision floating-point format and a minimum exponent of the half-precision floating-point format.
Yi discloses finding the differences of the logarithms of cmin and cmax (equiations 10-12), correlating to the differences of the minimum and maximum exponents. Yi does not suggest further subtraction for determining the scale factor. Therefore, Yi does not teach or suggest a combination as claimed including the limitations identified above.
Kaul discloses methods of calculating the maximum exponent (Fig. 3). Kaul does not suggest using a range with the minimum exponent for determining the factor. Therefore, Kaul does not teach or suggest a combination as claimed including the limitations identified above.
Quesada discloses using a scale factor to convert floating-point values to fixed-point values (Fig. 2). Quesada does not suggest how the scale factors are computed. Therefore, Quesada does not teach or suggest a combination as claimed including the limitations identified above.
Wegener et al. (US 20130262539 A1, hereinafter “Wegener”) discloses determining the maximum floating-point value in a set to compute a scale factor for conversion (Fig. 8). Wegener does not suggest using a range with the minimum exponent for determining the scale factor. Therefore, Wegener does not teach or suggest a combination as claimed including the limitations identified above.
Conclusion
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/P.N.L./
Phat LeExaminer, Art Unit 2182 (571) 272-0546
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
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