Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 23-30, 32-46 are presented for examination.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/12/26 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 23, 26, 28, 30, 32-38, 43, 45 are rejected under 35 U.S.C. 103 as being unpatentable over Yasin et al., US Patent Application Publication 2014/0380027 (hereinafter Yasin) in view of Hinton et al., US Patent 5,721,855 (hereinafter Hinton), further in view of Gschwind et al., US Patent Application Publication 2015/0347133 (hereinafter Gschwind).
Regarding claim 23, Yasin teaches:
A processor comprising: decode circuitry to decode a plurality of branch instructions (see e.g. para. [0037]), including a first branch instruction and a second branch instruction (see e.g. para. [0086]); execution circuitry coupled to the decode circuitry, the execution circuitry to execute the plurality of branch instructions, including the first branch instruction and the second branch instruction (see e.g. para. [0086]); and a plurality of registers to store branch information associated with the plurality of branch instructions, the plurality of registers including a first register to store branch information associated with the first branch instruction (see e.g. figs. 1-2, para. [0021-6]), and a second register to store branch information associated with the second branch instruction (see e.g. figs. 1-2, para. [0021-6]), the first register comprising: a count field to store a cycle count associated with the first branch instruction (see e.g. para. [0014]); a misprediction field to store branch prediction information associated with the first branch instruction (see e.g. para. [0025]).
Yasin fails to explicitly teach a type field to store branch type information to indicate a call branch type of the first branch instruction when set to a first value, and to indicate a return branch type of the first branch instruction when set to a second value.
Hinton teaches using a branch type field to indicate a call branch type and a return branch type using different values (see e.g. col. 13 lines 15-23, col. 14 line 66 – col. 15 line 12).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Yasin and Hinton to include a type field to store branch type information to indicate a call branch type of the first branch instruction when set to a first value, and to indicate a return branch type of the first branch instruction when set to a second value. This would have provided more granularity to the branch predictions to improve the flexibility of the system such as when special operations are performed for a call or return such as in Hinton.
Yasin in view of Hinton fails to explicitly teach an abort field to store abort information associated with the first branch instruction, and a transaction field, separate from the abort field, to store transactional information associated with the first branch instruction.
Gschwind teaches an abort field (see e.g. para. [0071-2]) and a transaction field separate from the abort field storing information associated with a first branch instruction (see e.g. para. [0185], [0188-9]).
While Gschwind teaches the TX status bit being within a separate TX status register, the single status bit could easily be incorporated within the same register as other status information with no change in its functionality. Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Yasin, Hinton, and Gschwind to an abort field to store abort information associated with the first branch instruction, and a transaction field, separate from the abort field, to store transactional information associated with the first branch instruction. This would have provided additional information for analysis so that corrective action could be taken to improve instruction execution. Tracking and constraining transactional areas would have also provided a benefit such as discussed by Gschwind: “Advantageously, constrained transactions have desirable properties because of the burden removed from programmers.” (see para. [0114]).
Regarding claim 26, Yasin in view of Hinton and Gschwind teaches or suggests:
The processor of claim 23, wherein the first register is a 64-bit register (see e.g. Yasin para. [0029]).
Regarding claim 28, Yasin in view of Hinton and Gschwind teaches or suggests:
The processor of claim 23, wherein the transaction field is a 1-bit field (see e.g. Gschwind para. [0185], [0188-9]).
Regarding claim 30, Yasin in view of Hinton and Gschwind teaches or suggests:
The processor of claim 23, wherein the branch prediction information is to indicate whether a branch of the first branch instruction was mispredicted (see e.g. Yasin para. [0025]).
Regarding claim 32, Yasin in view of Hinton and Gschwind teaches or suggests:
The processor of claim 23, wherein the abort field is a 1-bit field (see e.g. Gschwind para. [0071], a single bit can indicate an abort and what caused it).
Regarding claim 33, Yasin in view of Hinton and Gschwind teaches or suggests:
The processor of claim 23, wherein the plurality of registers are also to store: a source address for the first branch instruction; and a target address for the first branch instruction (see e.g. Yasin para. [0014], [0021-6]).
Regarding claim 34, Yasin in view of Hinton and Gschwind teaches or suggests:
The processor of claim 23, further comprising a counter to count cycles corresponding to the cycle count (see e.g. Yasin para. [0014]).
Regarding claim 35, Yasin in view of Hinton and Gschwind teaches or suggests:
The processor of claim 23, wherein the first register further comprises a plurality of additional fields to store additional information associated with the first branch instruction (see e.g. Yasin para. [0025]).
Regarding claim 36, Yasin in view of Hinton and Gschwind teaches or suggests:
The processor of claim 23, wherein the transactional information is to indicate whether the first branch instruction is in a transactional region (see e.g. Gschwind para. [0185], [0188-9]).
Regarding claim 37, Yasin in view of Hinton and Gschwind teaches or suggests:
The processor of claim 23, wherein the cycle count is based on a number of clock cycles since branch information was provided for a branch instruction immediately prior to the first branch instruction (see e.g. Yasin para. [0014]).
Claim 38 is rejected for reasons corresponding to those given above for claim 23 (see also e.g. Yasin para. [0016], SoC).
Claims 43, 45 are rejected for reasons corresponding to those given above for claims 23, 33-34, 37 (see also e.g. Yasin para. [0064], storage).
Claims 24-25, 39-40, 44 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Yasin in view of Hinton and Gschwind, further in view of Chen et al., US Patent Application Publication 2016/0092230 (hereinafter Chen-Yang).
Regarding claim 24, Yasin in view of Hinton and Gschwind teaches or suggests:
The processor of claim 23.
While Hinton teaches using different values to distinguish between each branch type (see e.g. col. 14 line 66 – col. 15 line 12), Yasin in view of Hinton and Gschwind fails to explicitly teach wherein the type field is to store the branch type information to indicate any one of at least seven different branch types for the first branch instruction by at least seven different corresponding values of the type field.
Chen-Yang teaches a type field to indicate any one of at least seven different branch types (see e.g. para. [0022], call/return, direct/indirect, conditional/unconditional, loop).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Yasin, Hinton, Gschwind and Chen-Yang such that the type field is to store the branch type information to indicate any one of at least seven different branch types for the first branch instruction by at least seven different corresponding values of the type field. This would have provided an advantage of being able to monitor the performance and track predictions for commonly executed branch types to more accurately analyze/predict branch performance.
Regarding claim 25, Yasin in view of Hinton and Gschwind teaches or suggests:
The processor of claim 23.
Hinton teaches using different values to distinguish between each branch type (see e.g. col. 14 line 66 – col. 15 line 12). Yasin in view of Hinton and Gschwind fails to explicitly teach wherein the call branch type is an indirect call branch type, and the type field is to store the branch type information to indicate a direct call branch type of the first branch instruction when set to a third value, to indicate a conditional branch type of the first branch instruction when set to a fourth value, to indicate an indirect jump branch type of the first branch instruction when set to a fifth value, and to indicate a direct jump branch type of the first branch instruction when set to a sixth value.
Chen-Yang teaches a type field to indicate additional branch types (see e.g. para. [0022], call/return, direct/indirect, conditional/unconditional, loop).
Using different values for each branch type such as in Hinton would readily apply to these additional common branch types. Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Yasin, Hinton, Gschwind and Chen-Yang such that the call branch type is an indirect call branch type, and the type field is to store the branch type information to indicate a direct call branch type of the first branch instruction when set to a third value, to indicate a conditional branch type of the first branch instruction when set to a fourth value, to indicate an indirect jump branch type of the first branch instruction when set to a fifth value, and to indicate a direct jump branch type of the first branch instruction when set to a sixth value. This would have provided an advantage of being able to monitor the performance and track predictions for commonly executed branch types to more accurately analyze/predict branch performance.
Claims 39-40 are rejected for reasons corresponding to those given above for claims 24-25 (see also e.g. Yasin para. [0016], [0036], SoC, graphics processing).
Claim 44 is rejected for reasons corresponding to those given above for claims 24-25 (see also e.g. Yasin para. [0064], storage).
Claims 27, 29, 41-42, 46 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Yasin in view of Hinton and Gschwind, further in view of In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976).
Regarding claim 27, Yasin in view of Hinton and Gschwind teaches or suggests:
The processor of claim 23.
Yasin in view of Hinton and Gschwind fails to explicitly teach wherein the type field comprises 4 bits.
In re Rinehart describes that the mere scaling of a prior art process capable of being scaled, if such were the case, would not establish patentability in a claim to an old process so scaled. 531 F.2d at 1053, 189 USPQ at 148.
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Yasin, Hinton, Gschwind, and In re Rinehart such that the type field comprises 4 bits. This would have provided the clearly predictable result of performing the exact same functionality on a different sized field. This also would have provided increased flexibility in being able to denote more branching types.
Regarding claim 29, Yasin in view of Hinton and Gschwind teaches or suggests:
The processor of claim 23.
Yasin in view of Hinton and Gschwind fails to explicitly teach wherein the misprediction field is a 1-bit field.
In re Rinehart describes that the mere scaling of a prior art process capable of being scaled, if such were the case, would not establish patentability in a claim to an old process so scaled. 531 F.2d at 1053, 189 USPQ at 148.
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Yasin, Hinton, Gschwind and In re Rinehart such that the misprediction field is a 1-bit field. This would have provided the clearly predictable result of performing the exact same functionality on a different sized field. This also would have provided an efficient use of space by only using a single bit to indicate whether something is mispredicted or not.
Claims 41-42 are rejected for reasons corresponding to those given above for claims 27, 29 (see also e.g. Yasin fig. 6-7, para. [0016], [0036], SoC, audio, display).
Claim 46 is rejected for reasons corresponding to those given above for claims 27, 29 (see also e.g. Yasin fig. 6-7, communication device).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 23-46 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-18 of U.S. Patent No. 10,592,244. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the ‘244 patent and the claims of the instant application have substantially overlapping scope.
Response to Arguments
Applicant’s arguments regarding the amended “abort field” and “transaction field” limitations have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Gschwind.
Conclusion
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/JOHN M LINDLOF/Primary Examiner, Art Unit 2183