DETAILED ACTION
This Office Action, based on application 17/992,609 filed 22 November 2022, is filed in response to applicant’s amendment and remarks filed 27 January 2026. Claims 1, 3-8, 10-15, and 17-23 are currently pending and have been fully considered below.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s remarks, submitted 27 January 2026 in response to the Office Action mailed 20 August 2025, have been fully considered below.
Claim Rejections under 35 U.S.C. § 103
The applicant traverses the prior art rejection alleging cited prior art fails to disclose “mark the entry associated with the invalidated line of the cache array as a recently invalidated entry”. The applicant asserts invalidating a directory entry, as discussed in CUMMINGS, is not marking the entry associated with the invalidated line of the cache array ‘as a recently invalidated entry’ as recited. In response, the Office asserts CUMMINGS teaches the limitation for reasons previously cited in conjunction with the prior art rejection to Claim 21 in the Office Action mailed 20 August 2025 as pre-amended Claim 21 recited a similar limitation. While the applicant alleges CUMMINGS invalidation is not equivalent to applicant’s claimed ‘recently’ invalidation, the Office respectfully notes the claim language merely indicates an intended use of the marking to which the Office maintains fully meets the conditions of the marking as claimed. Applicant’s claimed ‘recently’ invalidated fails to recite when or how the entry is no longer ‘recently’ invalidated; thus, fails to provide any claimed distinction as to when to determine recency of the validation. Finally, applicant’s specification at ¶[0069] recites “transaction module 108 … can reclaim … entries of the partial line-based probe filter that support the region-based probe filter and that are marked as recently invalidated by setting of the spare state encoding”. Thus, the Office asserts the new limitation incorporated into Claim 1 is merely a redundant limitation as the claim is already limited to ‘set … a spare state encoding indicating an invalidation of the line of the cache array’.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 4, 8, 11, 15, and 18 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception without significantly more. Patent Eligibility is determined as set forth under the 2019 Patent Eligibility Guidelines (see MPEP § 2106). The analysis of the claims in view of the guidelines are presented below.
Claim 1:
Regarding Step 1, the claim is directed to a machine (or manufacture). Thus, the claim is directed to one of the four categories of invention.
Regarding Step 2A Prong 1, this part of the eligibility analysis evaluates whether the claim recites a judicial exception. The claim includes the following limitations:
A computing device, comprising: at least one circuit configured to:
set, in response to detecting invalidation of a line of a cache array, a spare state encoding in an entry of a partial line-based probe filter, the spare state encoding indicating an invalidation of the line of the cache array; and
mark the entry associated with the invalidated line of the cache array as a recently invalidated entry;
process a cache transaction related to the cache array; and
search one or more entries of the partial line-based probe filter for a hit based on the cache transaction, the partial line-based probe filter including at least a recently invalidated entry and a valid entry.
The Office submits the underlined portions above recite a judicial exception. The underlines portions of limitations (2), (3), and (5) are directed to a series of steps to modify a data structure (cache directory) to set an invalidation of a cache line and search the data structure to determine whether a match between an incoming address and the addresses of the data structure is found. Specifically, limitations (2) and (3) involves searching one or more fields of the data structure to find an address that matches the line being invalidated, and modifying an associated validity bit or field. ¶[0069] of applicant’s specification recites “transaction module 108 … can reclaim … entries of the partial line-based probe filter that support the region-based probe filter and that are marked as recently invalidated by setting of the spare state encoding”; thus, even though limitation (3) is directed to marking the entry as a ‘recently invalidated entry’, the limitation is deemed redundant since the specification explicitly states that the marking is performed by setting the spare state encoding. Limitation (5), similar to limitations (2) and (3), involves searching one or more fields of the data structure to determine whether a match is found between a reference address (from a cache transaction) and the addresses in the fields of the data structure. The Office asserts the process of searching a cache directory and changing settings of the cache directory as falling within the “Mental Processes” grouping of abstract ideas as the limitations may practically be performed in the human mind, including for example, observations, evaluations, judgements, and opinions (MPEP 2106.04(a)(2)(III)).
The Office has determined the claim recites a judicial exception requiring further analysis in Step 2A Prong 2.
Regarding Step 2A Prong 2, this part of the eligibility analysis evaluates whether the claim as a whole integrates the recited judicial exception into a practical application of the exception. This evaluation is performed by (a) identifying whether there are any additional elements recited in the claim beyond the judicial exception, and (b) evaluating those additional elements individually and in combination to determine whether the claim as a whole integrates the exception into a practical application. Besides the abstract idea of the claim, the claim further recites the following additional elements (underlined):
A computing device, comprising: at least one circuit configured to:
set, in response to detecting invalidation of a line of a cache array, a spare state encoding in an entry of a partial line-based probe filter, the spare state encoding indicating an invalidation of the line of the cache array; and
mark the entry associated with the invalidated line of the cache array as a recently invalidated entry;
process a cache transaction related to the cache array; and
search one or more entries of the partial line-based probe filter for a hit based on the cache transaction, the partial line-based probe filter including at least a recently invalidated entry and a valid entry.
Limitation (4) recites the additional element that a cache transaction is processed. The Office asserts the action of processing a cache transaction such as a read or write of the cache is an insignificant extra-solution activity of the abstract idea as the processing may be interpreted as a mere form of data gathering (MPEP 2106.05(g)). Limitations (1) through (5) recite an additional element of a computing device comprising a circuit that controls a cache array. The Office asserts the claimed ‘computing device’ as an additional element is recited at a high-level of generality (e.g. the host system is not limited to comprise any particular or specialized components) such that the broadest reasonable interpretation of the ‘computing device’ is a generic computer. Accordingly, the additional element does not integrate the abstract idea into a practical application because the computing device or cache does not impose any meaningful limits on practicing the abstract idea (MPEP 2106.05(f)). Finally, the Office notes the claim is merely directed to changing entries of a cache directory and searching the cache directory without further being limited to doing anything with the result of performing any of the cache directory modifications or performing the search; as such, the Office asserts the claim is not directed to any sort of improvement of the functioning of the computer.
Thus, the Office has determined that the noted additional elements fail to integrate the recited judicial exception into a practical application requiring further analysis in Step 2B.
Regarding Step 2B, this part of the eligibility analysis evaluates the additional elements of the claim to determine whether they amount to an inventive concept. As noted in the analysis of Step 2A Prong 2, the Office has determined those additional elements.
Regarding Limitation (4), the courts have recognized, similar to ‘process{ing} a cache transaction’, that computer functions including “storing and retrieving information in memory” to be well-understood, routine, and conventional functions when they are claimed in merely a generic manner or as insignificant extra-solution activity (MPEP 2106.05(d)(II)). Furthermore, the additional element of a ‘computing device’ controlling a cache is recited at a high-level of generality such that the system may be interpreted as a generic computer; thus, the claim amounts to no more than mere instructions to apply the identified abstract idea using a generic computer (MPEP 2106.05(f)).
As such, the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception and thus is not patent eligible.
Claims 8 and 15:
Similar to the analysis of Claim 1 above:
Claims 8 and 15 are directed to a machine (or manufacture) and method (or process), respectively; thus, the claims are directed to one of the four categories of invention.
Both Claims 8 and 15 recite similar configurations or processes of the computing device of Claim 1; thus, both Claims 8 and 15 recite the judicial exception of Claim 1.
Beyond the computing device of Claim 1, both Claims 8 and 15 recite additional elements considered under Step 2A Prong 2. Claim 8 is directed to a system comprising a processor and memory; Claim 15 is directed to a method implemented by a processor. Similar to the analysis of the ‘computing device’ under Step 2A Prong 2 of Claim 1, the additional elements are recited at a high-level of generality such that the broadest reasonable interpretation of the additional elements comprise a generic computer; the Office asserts the claims amount to no more than mere instructions to apply the identified abstract idea using a generic computer (MPEP 2106.05(f)). Thus, the additional elements fail to integrate the recited judicial exception into a practical application.
Beyond the method of Claim 1, both Claims 8 and 15 further recite additional elements considered under Step 2B. Similar to the analysis of the ‘computing device’ under Step 2B of Claim 1, the additional elements are recited at a high-level of generality such that the system may be interpreted as a generic computer; thus, the claim amounts to no more than mere instructions to apply the identified abstract idea using a generic computer (MPEP 2106.05(f)). Thus, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Claims 4, 11, and 18:
Claims 4, 11, and 18, dependent on Claims 1, 8, and 15 respectively, each have been found to further expand upon the identified abstract idea of their respective parent claim (e.g. the additional limitations of the claims are being evaluated under Step 2A Prong 1 and do not recite any ‘additional elements’ for consideration under Step 2A Prong 2 or Step 2B).
Claims 4, 11, and 18 further limits the process/configuration of the respective parent claim to include a reclamation detection to which the Office asserts may be characterized as a simple observation.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1, 3, 8, 10, 15, 17, 22, and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over CUMMINGS et al (US PGPub 2010/0268884) in further view of BLAKE et al (US Patent 5,752,264).
With respect to Claim 1, CUMMINGS discloses a computing device, comprising:
at least one circuit configured to:
set, in response to detecting invalidation of a line of a cache array (¶[0053] – “Referring now to block 530, for a partial cache line store request, the RD machine of L3 cache returns the target partial cache line to the merge buffer. L3 cache also invalidates the directory entry corresponding to target partial cache line to release its copy of the partial cache line because the partial cache line store request completes a read-modify-write cycle {analogous to ‘detect invalidation’} used to update the partial cache line (block 532).”), a spare state encoding in an entry of a partial line-based probe filter, the spare state encoding indicating an invalidation of the line of the cache array (¶[0053] – “L3 cache also invalidates the directory entry corresponding to target partial cache line to release its copy of the partial cache line”);
mark the entry associated with the invalidated line of the cache array as a recently invalidated entry (¶[0053] – “L3 cache also invalidates the directory entry corresponding to target partial cache line to release its copy of the partial cache line”; ¶[0043] – “Directory entry 300 further includes valid bits. V0 302 and V1 304, which are used when a partial cache line resides in the corresponding storage location in data array 260 to indicate which half of the cache line is valid in L3 cache 232”);
process a cache transaction related to the cache array (Fig 6, Block 600 – “L3 Snoop” => Block 602 – “Partial Cache Line Prefetch?” => YES; ¶[0055]); and
search one or more entries of the partial line-based probe filter for a hit based on the cache transaction (¶[0056] – “If … the SN machine 274 determines at block 602 that the snooped command is a partial cache line prefetch command, SN machine determines {analogous to ‘search one or more entries …’} at blocks 606 and 608 whether or not the directory 262 {analogous to ‘the partial line-based probe filter’} indicates that the partial cache line prefetch command hits a partial or full cache line within L3 cache 232”).
CUMMINGS may not explicitly disclose the partial line-based probe filter including at least a recently invalidated entry and a valid entry.
However, BLAKE discloses the partial line-based probe filter including at least a recently invalidated entry and a valid entry (Col 18, Lines 59-67 – “on a directory search for a bus fetch command and the storage address is found to be in an ‘invalid’ state (4a) {aka ‘a recently invalidated entry’} or a ‘Hit with no conflict’ (4b) {aka ‘a valid entry’}, no further action is made by this L2 for completing the snoop operation {analogous to ‘refrain from initiating a multicast probe’})”.
CUMMINGS and BLAKE are analogous art because they are from the same field of endeavor of cache coherency systems. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of CUMMINGS and BLAKE before him or her, to modify the cache directory of CUMMINGS to include both ‘recently invalidated’ and ‘valid’ entries in the cache directory as taught by BLAKE. A motivation for doing so would have been properly maintain cache statuses as a part of a cache coherency protocol for maintaining storage integrity in a system that has multiple clusters of multiple processors connected via a shared bus (Col 18, Lines 44-59). Therefore, it would have been obvious to combine CUMMINGS and BLAKE to obtain the invention as specified in the instant claims.
With respect to Claim 8, CUMMINGS discloses a system comprising:
at least one physical processor (Fig 1, Processing Unit 104); and
physical memory comprising computer-executable instructions (¶[0065]) that, when executed by the at least one physical processor, cause the at least one physical processor to:
set, in response to detecting invalidation of a line of a cache array (¶[0053] – “Referring now to block 530, for a partial cache line store request, the RD machine of L3 cache returns the target partial cache line to the merge buffer. L3 cache also invalidates the directory entry corresponding to target partial cache line to release its copy of the partial cache line because the partial cache line store request completes a read-modify-write cycle {analogous to ‘detect invalidation’} used to update the partial cache line (block 532).”), a spare state encoding in an entry of a partial line-based probe filter, the spare state encoding indicating an invalidation of the line of the cache array (¶[0053] – “L3 cache also invalidates the directory entry corresponding to target partial cache line to release its copy of the partial cache line”);
mark the entry associated with the invalidated line of the cache array as a recently invalidated entry (¶[0053] – “L3 cache also invalidates the directory entry corresponding to target partial cache line to release its copy of the partial cache line”; ¶[0043] – “Directory entry 300 further includes valid bits. V0 302 and V1 304, which are used when a partial cache line resides in the corresponding storage location in data array 260 to indicate which half of the cache line is valid in L3 cache 232”);
process a cache transaction related to the cache array (Fig 6, Block 600 – “L3 Snoop” => Block 602 – “Partial Cache Line Prefetch?” => YES; ¶[0055]); and
search one or more entries of the partial line-based probe filter for a hit based on the cache transaction (¶[0056] – “If … the SN machine 274 determines at block 602 that the snooped command is a partial cache line prefetch command, SN machine determines {analogous to ‘search one or more entries …’} at blocks 606 and 608 whether or not the directory 262 {analogous to ‘the partial line-based probe filter’} indicates that the partial cache line prefetch command hits a partial or full cache line within L3 cache 232”).
CUMMINGS may not explicitly disclose (a) the partial line-based probe filter including at least a recently invalidated entry and a valid entry.
However, BLAKE discloses the partial line-based probe filter including at least a recently invalidated entry and a valid entry (Col 18, Lines 59-67 – “on a directory search for a bus fetch command and the storage address is found to be in an ‘invalid’ state (4a) {aka ‘a recently invalidated entry’} or a ‘Hit with no conflict’ (4b) {aka ‘a valid entry’}, no further action is made by this L2 for completing the snoop operation {analogous to ‘refrain from initiating a multicast probe’})”.
CUMMINGS and BLAKE are analogous art because they are from the same field of endeavor of cache coherency systems. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of CUMMINGS and BLAKE before him or her, to modify the cache directory of CUMMINGS to include both ‘recently invalidated’ and ‘valid’ entries in the cache directory as taught by BLAKE. A motivation for doing so would have been properly maintain cache statuses as a part of a cache coherency protocol for maintaining storage integrity in a system that has multiple clusters of multiple processors connected via a shared bus (Col 18, Lines 44-59). Therefore, it would have been obvious to combine CUMMINGS and BLAKE to obtain the invention as specified in the instant claims.
With respect to Claim 15, CUMMINGS discloses a computer-implemented method comprising:
setting, in response to detecting invalidation of a line of a cache array (¶[0053] – “Referring now to block 530, for a partial cache line store request, the RD machine of L3 cache returns the target partial cache line to the merge buffer. L3 cache also invalidates the directory entry corresponding to target partial cache line to release its copy of the partial cache line because the partial cache line store request completes a read-modify-write cycle {analogous to ‘detect invalidation’} used to update the partial cache line (block 532).”), by at least one processor and in response to the detected invalidation, a spare state encoding in an entry of a partial line-based probe filter, the spare state encoding indicating an invalidation of the line of the cache array (¶[0053] – “L3 cache also invalidates the directory entry corresponding to target partial cache line to release its copy of the partial cache line”);
marking the entry associated with the invalidated line of the cache array as a recently invalidated entry (¶[0053] – “L3 cache also invalidates the directory entry corresponding to target partial cache line to release its copy of the partial cache line”; ¶[0043] – “Directory entry 300 further includes valid bits. V0 302 and V1 304, which are used when a partial cache line resides in the corresponding storage location in data array 260 to indicate which half of the cache line is valid in L3 cache 232”);
processing, by the at least one processor, a cache transaction related to the cache array (Fig 6, Block 600 – “L3 Snoop” => Block 602 – “Partial Cache Line Prefetch?” => YES; ¶[0055]); and
search one or more entries of the partial line-based probe filter for a hit based on the cache transaction (¶[0056] – “If … the SN machine 274 determines at block 602 that the snooped command is a partial cache line prefetch command, SN machine determines {analogous to ‘search one or more entries …’} at blocks 606 and 608 whether or not the directory 262 {analogous to ‘the partial line-based probe filter’} indicates that the partial cache line prefetch command hits a partial or full cache line within L3 cache 232”).
CUMMINGS may not explicitly disclose the partial line-based probe filter including at least a recently invalidated entry and a valid entry.
However, BLAKE discloses the partial line-based probe filter including at least a recently invalidated entry and a valid entry (Col 18, Lines 59-67 – “on a directory search for a bus fetch command and the storage address is found to be in an ‘invalid’ state (4a) {aka ‘a recently invalidated entry’} or a ‘Hit with no conflict’ (4b) {aka ‘a valid entry’}, no further action is made by this L2 for completing the snoop operation {analogous to ‘refrain from initiating a multicast probe’})”.
CUMMINGS and BLAKE are analogous art because they are from the same field of endeavor of cache coherency systems. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of CUMMINGS and BLAKE before him or her, to modify the cache directory of CUMMINGS to include both ‘recently invalidated’ and ‘valid’ entries in the cache directory as taught by BLAKE. A motivation for doing so would have been properly maintain cache statuses as a part of a cache coherency protocol for maintaining storage integrity in a system that has multiple clusters of multiple processors connected via a shared bus (Col 18, Lines 44-59). Therefore, it would have been obvious to combine CUMMINGS and BLAKE to obtain the invention as specified in the instant claims.
With respect to Claims 3, 10, and 17, the combination of CUMMINGS and BLAKE disclose the device/system/method of each respective parent claim.
CUMMINGS further discloses resetting, in response to a detection of an allocation of the line in the cache array based on an operation type corresponding to a cacheable request, the spare state encoding in the recently invalidated entry of the partial line-based probe filter in a manner that transitions the recently invalidated entry of the partial line-based probe filter to a valid state (¶[0048] – “At block 412, the PF machine 272 determines if the coherence response to the partial cache line prefetch command indicates the partial cache line was sourced from an IMC 206 in an exclusive coherence state. If so, the PF machine 272 installs the partial cache line in data array 260 of L3 cache 232 and sets coherence state field 306 and one of valid bits 302, 304 of the corresponding directory entry 300 as described above with reference to FIG. 3 and Table I (blocks 414 and 416)”).
With respect to Claim 22, the combination of CUMMINGS and BLAKE disclose the computing device of claim 1.
CUMMINGS further discloses wherein, in response to the detecting the invalidation of the line of the cache array, the at least one circuit is further configured to avoid setting a dedicated invalid bit to indicate that the recently invalidated entry is invalid (¶[0043] – “Directory entry 300 further includes valid bits. V0 302 and V1 304, which are used when a partial cache line resides in the corresponding storage location in data array 260 to indicate which half of the cache line is valid in L3 cache 232. Those skilled in the art will appreciate that with additional valid bits, it would be possible to separately indicate validity for smaller portions of the full cache line”).
With respect to Claim 23, the combination of CUMMINGS and BLAKE disclose the computing device of claim 1.
CUMMINGS further discloses wherein: the recently invalidated entry has an address tag corresponding to an address of the invalidated line of the cache array (Fig 3; ¶[0043] – “directory entry 300 includes an address tag 308 that indicates the real address of the cache line present in the data array 260 at the storage location corresponding to this directory entry 300”).
BLAKE further discloses the hit matches the address of the invalidated line of the cache array (Col 18, Lines 7-26 – “The L2 performs the directory search to check the status of the storage address in the L2 cache … If the directory search finds the status to be a ‘Hit with No Conflict’ …”).
Claim(s) 4-6, 11-13, and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over CUMMINGS in further view of BLAKE and KALYANASUNDHARAM et al (US PGPub 2019/0188137).
With respect to Claims 4, 11, and 18, , the combination of CUMMINGS and BLAKE disclose the device/system/method of each respective parent claim.
CUMMINGS or BLAKE may not explicitly disclose detecting reclamation of a region-based probe filter.
However, KALYANASUNDHARAM discloses detecting reclamation of a region-based probe filter (Abstract – “According, the system include a region-based cache directory to track regions which have at least one cache line cached in any cache subsystem in the system … If a reference count of a given entry goes to zero, the cache directory reclaims the given entry”).
CUMMINGS, BLAKE, and KALYANDASUNDHARAM are analogous art because they are from the same field of endeavor of cache coherency systems. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of CUMMINGS, BLAKE, and KALYANDASUNDHARAM before him or her, to modify the cache directory of the combination of CUMMINGS and BLAKE to include region-based entries as taught by KALYANDASUNDHARAM. A motivation for doing so would have been to reduce the size of the cache directory since “by tracking at a granularity of a region rather than at a finer granularity of a cache line, the size of each cache directory is reduced (¶[0036]). Therefore, it would have been obvious to combine CUMMINGS, BLAKE, and KALYANDASUNDHARAM to obtain the invention as specified in the instant claims.
With respect to Claims 5, 12, and 19, the combination of CUMMINGS, BLAKE, and KALYANDASUNDHARAM disclose the device/system/method of each respective parent claim.
KALYANDASUNDHARAM further discloses reclaiming, in response to the detection of the reclamation, the recently invalidated entry of the partial line-based probe filter (¶[0040] – “when a coherent master receives a region invalidation probe, the coherent master invalidates each cache line of the region that is caches by the local CPU”).
With respect to Claims 6, 13, and 20, the combination of CUMMINGS, BLAKE, and KALYANDASUNDHARAM disclose the device/system/method of each respective parent claim.
KALYANDASUNDHARAM further discloses reclaiming, in response to the detection of the reclamation, entries of the partial line-based probe filter that support the region-based probe filter and that are marked as recently invalidated by setting of the spare state encoding (¶[0040] – “when a coherent master receives a region invalidation probe, the coherent master invalidates each cache line of the region that is caches by the local CPU”).
Claim(s) 7 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over CUMMINGS in further view of BLAKE and CHACON et al (US PGPub 2019/0050333).
With respect to Claims 7 and 14, the combination of CUMMINGS and BLAKE disclose the device/system of each respective parent claim.
CUMMINGS or BLAKE may not explicitly disclose detecting that a set of entries of the partial line-based probe filter has run out of empty entries for allocation; and reclaiming, at least partly in response to detecting that the set of entries of the partial line-based probe filter has run out of empty entries for allocation, the recently invalidated entry of the partial line-based probe filter of the set.
However, CHACON discloses detecting that a set of entries of the partial line-based probe filter has run out of empty entries for allocation; and reclaiming, at least partly in response to detecting that the set of entries of the partial line-based probe filter has run out of empty entries for allocation, the recently invalidated entry of the partial line-based probe filter of the set (¶[0003] - “Maintaining global cache directories is often accomplished by tracking the data in the DRAM caches and replacing or removing outdated cache entries from the global cache directory as needed using a process referred to as “invalidation.””).
CUMMINGS, BLAKE, and CHACON are analogous art because they are from the same field of endeavor of cache coherency systems. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of CUMMINGS, BLAKE, and CHACON before him or her, to modify management of the cache directory of the combination of CUMMINGS and BLAKE to include entry reclaiming as taught by CHACON. A motivation for doing so would have been to reduce the size of the cache directory so that memory otherwise allocated to the directory may be freed to store other data. Therefore, it would have been obvious to combine CUMMINGS, BLAKE, and CHACON to obtain the invention as specified in the instant claims.
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over CUMMINGS in further view of BLAKE and PHAM et al (US PGPub 2024/0020027).
With respect to Claim 21, the combination of CUMMINGS and BLAKE disclose the computing device of claim 1.
CUMMINGS or BLAKE may not explicitly disclose wherein the recently invalidated entry persists until the partial line-based probe filter runs out of empty entries for allocation.
However, PHAM discloses wherein the recently invalidated entry persists until the partial line-based probe filter runs out of empty entries for allocation (¶[0080] – “if all entries in snoop filter are currently in use … snoop filter cache controller may evict some data from snoop filter. As part of evicting data from snoop filter, snoop filter may send a device-to-host invalidate request to device coherency engine, requesting that host invalidate a particular data from its cache”).
CUMMINGS, BLAKE, and PHAM are analogous art because they are from the same field of endeavor of cache coherency systems. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of CUMMINGS, BLAKE, and PHAM before him or her, to modify management of the cache directory of the combination of CUMMINGS and BLAKE to include entry eviction as taught by PHAM. A motivation for doing so would have been to allow for the snoop filter to be a different size than the size of cache in a host while further providing support to manage a host access request for data for which there is no entry in the snoop filter (¶[0080]). Therefore, it would have been obvious to combine CUMMINGS, BLAKE, and PHAM to obtain the invention as specified in the instant claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ERIC T LOONAN/Examiner, Art Unit 2137