Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is in response to application filed 03/17/2026.
Claims 1-12, 14-21 are pending in this application.
Response to Arguments
Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4, 8, 11-12, 14, 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Ueta et al. (US 2023/0308931 A1) in view of LV et al. (US 2021/0328696 A1).
Regarding claim 1, Ueta discloses 1a apparatus comprising:
a network interface device comprising a host interface; a network interface ([0029]: [0029] The edge server 110, in some aspects, includes a set of ‘L’ physical network interfaces 111 including a first physical network interface 111-1 to an L-th physical network interface 111-L, a network switching module 112, a set of ‘M’ network interfaces for applications 113 for applications including a first network interface for application 113-1 to an M-th network interface for application 113-M, a multi networking module 114, a set of ‘N’ applications 115 including a first application 115-1 to an N-th application 115-N); and circuitry to:
receive time information of a device that executes a service (fig. 10: time information t0, td, t1. [0052]: The system, e.g., a field server 103 of the communication system 100 of FIG. 1, may monitor a jitter associated with App #2 (e.g. service) as illustrated in diagram 1010. In diagram 1010, the vertical axis indicates the measured jitter and the horizontal axis indicates the time at which the jitter is measured) and based on the time information indicating that a jitter level for the device is outside of a permitted jitter range for the service, perform one or more actions to cause execution of the service on a device that operates based on a clock signal jitter that is within the permitted jitter range ([0052]: App #2 may also be associated with a threshold of 40 ms for jitter to ensure that the requirement for jitter to be less than 50 ms will be met by switching traffic control patterns before the network fails to meet the requirement that the jitter be less than 50 ms. From a time t0 to a time t1 the system may use traffic control pattern #3. The traffic control pattern #3 may be selected from the traffic control patterns #2 and #3 in traffic control pattern table 1030 that each meet the requirements of App #2. At time td the system may measure a jitter that is above the jitter threshold (e.g., above 40 ms) associated with App #2 and determine to switch to traffic control pattern #2 at time t1 (e.g. action).
However, Ueta does not disclose wherein the clock signal jitter is based on a jitter level of the clock signal relative to a reference clock signal.
In an analogous art, LV discloses wherein the clock signal jitter is based on a jitter level of the clock signal relative to a reference clock signal ([0102]: The PTP message includes a Sync message, a delay_req message, and a delay_resp message. The time information is carried in the PTP message. The time information may be a timestamp 1, a timestamp 2, a timestamp 3, and a timestamp 4. The network device may calculate a time deviation between the network device and the master clock node by using the time information. [0113]: A clock deviation described in the foregoing embodiment may be a jump amplitude deviation, a jitter deviation, and a static deviation of a clock node).
Therefore, it would have been obvious before the effective filed date of the claimed invention to a person having ordinary skill in the art to modify Ueta to comprise “wherein the clock signal jitter is based on a jitter level of the clock signal relative to a reference clock signal” taught by LV.
One of ordinary skilled in the art would have been motivated because it would have enabled a master clock node for performing clock synchronization; and the network device calibrates a clock of the network device based on time information of the selected master clock node (LV, [0006]).
Regarding claim 2, Ueta-LV discloses the apparatus of claim 1, wherein the service is part of a group of distributed services executing on one or more of: a chiplet, processor, server, warehouse computer, data center, or multiple data centers (Ueta, [0063]: the edge server may identify an application in the plurality of applications to be executed by the edge server (e.g., a communication node).
Regarding claim 3, Ueta-LV discloses the apparatus of claim 1, wherein the one or more actions comprise one or more of: reduce offset of the clock signal from a reference clock signal, cause the device to be disabled to execute the service, or request another device or server to be added for use to execute the service (LV, [0020]: when the first clock variance value is less than the second clock variance value, it indicates that the precision of performing clock synchronization by using the first master clock node is higher than the precision of performing clock synchronization by using the second master clock node. [0102]: The PTP message includes a Sync message, a delay_req message, and a delay_resp message. The time information is carried in the PTP message. The time information may be a timestamp 1, a timestamp 2, a timestamp 3, and a timestamp 4. The network device may calculate a time deviation between the network device and the master clock node by using the time information). The same rationale applies as in claim 1.
Regarding claim 4, Ueta-LV discloses the apparatus of claim 3, wherein the reference clock signal is synchronized with a main timer based on one or more of: Institute of Electrical and Electronics Engineers (IEEE) 1588 Precision Time Protocol (PTP), IEEE1588-2019, or White Rabbit Project (Ueta, [0032]: The field servers 103 and the edge server 110 may be synchronized via the communication network 104 by time synchronization such as Precision Time Protocol (PTP).
Regarding claim 8, Ueta-LV discloses the apparatus of claim 1, wherein the network interface device comprises one or more of: an infrastructure processing unit (IPU), data processing unit (DPU), smart NIC, forwarding element, switch, router, network interface controller, or network-attached appliance (Ueta, [0029]: The edge server 110, in some aspects, includes a set of ‘L’ physical network interfaces 111 including a first physical network interface 111-1 to an L-th physical network interface 111-L, a network switching module 112).
Regarding claims 11 and 16; the claims are interpreted and rejected for the same reason as set forth in claim 1.
Regarding claims 12 and 17; the claims are interpreted and rejected for the same reason as set forth in claim 2.
Regarding claim 14, Ueta-LV discloses the computer-readable medium of claim 11, wherein the reference clock signal is synchronized with a main timer based on one or more of: IEEE 1588 Precision Time Protocol (PTP), IEEE1588-2019, or White Rabbit Project (Ueta, [0032]: The field servers 103 and the edge server 110 may be synchronized via the communication network 104 by time synchronization such as Precision Time Protocol (PTP).
Regarding claim 18; the claim is interpreted and rejected for the same reason as set forth in claim 3.
Regarding claim 19; the claim is interpreted and rejected for the same reason as set forth in claim 14.
Claims 5 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ueta in view of LV, as applied to claim 1, in further view of Barry et al. (US 2010/0278055 A1).
Regarding claim 5, Ueta-LV discloses the apparatus of claim 1.
However, Ueta-LV does not disclose wherein the time information is received from a connection consistent with general-purpose input/output (GPIO).
In an analogous art, Barry discloses wherein the time information is received from a connection consistent with general-purpose input/output (GPIO). ([0062]: The apparatus 600 includes a field programmable gate array (FPGA) and/or an application specific integrated circuit (ASIC) 602 that implements the operations of module 300 for clock adjustment based on processing of timing packet delay values. The FPGA/ASIC 602 may be configured by and may provide output to input/output devices 604).
Therefore, it would have been obvious before the effective filed date of the claimed invention to a person having ordinary skill in the art to modify Ueta-LV to comprise “wherein the time information is received from a connection consistent with general-purpose input/output (GPIO)” taught by Barry.
One of ordinary skilled in the art would have been motivated because it would have enabled enhancing the accuracy of timing distribution in packet networks to minimize the jitter affecting timing packets sent between the clock server and the client nodes (Barry, [0006]).
Regarding claim 20; the claim is interpreted and rejected for the same reason as set forth in claim 5.
Claims 6 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Ueta in view of LV, as applied to claim 1, in further view of Polehn et al. (US 2022/0014455 A1).
Regarding claim 6, Ueta-LV discloses the apparatus of claim 1.
However, Ueta-LV does not disclose wherein the permitted jitter range for the service is based on a service level agreement (SLA) for the service.
In an analogous art, Polehn discloses wherein the permitted jitter range for the service is based on a service level agreement (SLA) for the service. ([0056]: The SLA information may indicate threshold performance values, such as latency, jitter, packet loss, and/or other values for other performance metrics)
Therefore, it would have been obvious before the effective filed date of the claimed invention to a person having ordinary skill in the art to modify Ueta-LV to comprise “wherein the permitted jitter range for the service is based on a service level agreement (SLA) for the service” taught by Polehn.
One of ordinary skilled in the art would have been motivated because it would have enabled to evaluate a SLA to verify whether the SLA is being met or not (Polehn, [0057]).
Regarding claim 15; the claim is interpreted and rejected for the same reason as set forth in claim 6.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Ueta in view of LV, as applied to claim 1, in further view of Wen et al. (US 2021/0243712 A1).
Regarding claim 7, Ueta-LV discloses the apparatus of claim 1.
However, Ueta-LV does not disclose wherein the clock signal comprises a 1 pulse per second (PPS) indicator signal.
In an analogous art, Wen discloses wherein the clock signal comprises a 1 pulse per second (PPS) indicator signal ([0075]: The timing chip processes the received physical layer data and outputs a local absolute time information and a frequency reference signal 1pps of the terminal, and the terminal adjusts a terminal reference time according to the absolute time information and the frequency reference signal 1pps outputted by the timing chip).
Therefore, it would have been obvious before the effective filed date of the claimed invention to a person having ordinary skill in the art to modify Ueta-LV to comprise “wherein the clock signal comprises a 1 pulse per second (PPS) indicator signal.” taught by Wen.
One of ordinary skilled in the art would have been motivated because it would have enabled to adjust the terminal reference time according to absolute time information and the frequency reference signal (Wen, [0075]).
Claims 9 are rejected under 35 U.S.C. 103 as being unpatentable over Ueta in view of LV, as applied to claim 1, in further view of Uemura et al. (US 2018/0174209 A1).
Regarding claim 9, Ueta-LV discloses the apparatus of claim 1.
However, Ueta-LV does not disclose a server communicatively coupled to the network interface device, wherein the server is to execute the service and utilize the clock signal to time operations of the service.
In an analogous art, Uemura discloses wherein the second device comprises a host system that is communicatively coupled to the network interface device and wherein the host system is to utilize the clock signal to time operations of the service ([0070]: The protective control device A according to this embodiment includes the clock unit 3 that clocks a date and time, the time information creating unit 4 which associates the operation status of the application with the time information obtained from the clock unit 3 and which creates the application time information. [0072]: The operation status is the status indicating the installation completion of the application, the status indicating the start of operation)
Therefore, it would have been obvious before the effective filed date of the claimed invention to a person having ordinary skill in the art to modify Ueta-LV to comprise “a server communicatively coupled to the network interface device, wherein the server is to execute the service and utilize the clock signal to time operations of the service” taught by Uemura.
One of ordinary skilled in the art would have been motivated because it would have enabled to associate time information with a plurality of operation status for a respective application (Uemura, [0070]).
Claims 10 are rejected under 35 U.S.C. 103 as being unpatentable over Ueta in view of LV in view of Uemura, as applied to claim 9, in view of Connolly et al. (US 2023/0345304 A1).
Regarding claim 10, Ueta-LV-Uemura discloses the apparatus of claim 9.
However, Ueta-LV-Uemura does not disclose comprising a data center, wherein the data center comprises device and second device.
In an analogous art, Connolly discloses comprising a data center, wherein the data center comprises device and second device (fig. 3, [0041]: system 300 can include gaming provider data center 330A-B, network routing equipment 310A-C, edge equipment 320A-B, controller equipment 150, and network node equipment 157).
Therefore, it would have been obvious before the effective filed date of the claimed invention to a person having ordinary skill in the art to modify Ueta-LV-Uemura to comprise “a data center, wherein the data center comprises the server and a second server and wherein the perform one or more actions to cause execution of the service on a device that operates based on a clock signal within a permitted jitter range comprises select the second server to execute the service based on a second time information for the second server being inside of the permitted jitter range for the service” taught by Connolly.
One of ordinary skilled in the art would have been motivated because it would have enabled to addressing consistency of delays in online applications (Connolly, [0001]).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Ueta in view of LV, as applied to claim 9, in view of Pitigoi et al. (US 2019/0020433 A1).
Regarding claim 21, Ueta-LV discloses the apparatus of claim 1.
However, Ueta-LV does not disclose wherein the clock signal jitter is based on comparisons of edges of the clock signal with edges of the reference clock signal.
In an analogous art, Pitigoi discloses wherein the clock signal jitter is based on comparisons of edges of the clock signal with edges of the reference clock signal ([0062]: The predetermined T_Fq may be the same as described above. Here, the sensor 310 may be configured a priori with the predetermined T_Fq. Once the sensor 310 receives the timer correction messages, it may compare the duration of the time interval bookended by the two identifiable significant edges included with the timer correction messages, as measured by the timer 315 in the sensor 310, with the predetermined T_Fq, also as measured by the sensor timer, derive a timer correction factor accordingly, and apply the timer correction factor to correct the internal sensor timer).
Therefore, it would have been obvious before the effective filed date of the claimed invention to a person having ordinary skill in the art to modify Ueta-LV to comprise “wherein the clock signal jitter is based on comparisons of edges of the clock signal with edges of the reference clock signal” taught by Pitigoi.
One of ordinary skilled in the art would have been motivated because it would have enabled adjusting the time interval between samples based on the hardware synchronization event and the offset (Pitigoi, [0006]).
Additional References
The prior art made of record and not relied upon is considered pertinent to applicants disclosure.
Zaidman et al., US 2019/0155327 A1: System and Method for Time Stamp Synchronization.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUAN C TURRIATE GASTULO whose telephone number is (571)272-6707. The examiner can normally be reached Monday - Friday 8 am-4 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brian J Gillis can be reached at 571-272-7952. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.C.T/Examiner, Art Unit 2446
/BRIAN J. GILLIS/Supervisory Patent Examiner, Art Unit 2446
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