Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is in response to application filed 08/05/2026.
Claims 1-12, 14-21 are pending in this application.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/05/2026 has been entered.
Response to Arguments
Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 11, 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the clock signal jitter based on a jitter level of the clock signal utilized by the second device relative to a reference clock signal…" in lines 11-12, and then further recites “…performance of the service on a processor of the second device timed according to the clock signal” in lines 13-14. There is insufficient antecedent basis for this limitation in the claim. The claim introduces “a clock signal jitter” that describes a jitter characteristic rather than introducing a specific “clock signal.” The claim further introduces “a reference clock signal.” Therefore, it is unclear the clarity of “the clock signal” in the claim and how the processor of the second device is timed according to “the clock signal.” Appropriate correction and clarification is required.
Claim 11 recites “determine a difference between a clock signal of a device…” in lines 5-6, and then further recites “…the device operates based on a second clock signal…” in line 9. It is unclear the relationship between “a clock signal of a device” and “a second clock signal” of the device. More specifically, it is unclear whether the “second clock signal” refers to a clock signal different from the recited “clock signal of a device,” or whether “second clock signal” refers to the clock signal after its offset has been corrected. Appropriate correction and clarification is required.
Regarding claim 16; the claim is interpreted and rejected for the same reason as set forth in claim 11.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4, 8-12, 14, 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Johnson et al. (US 11,481,258 B1) in view of Hubbe et al. (US 2023/0006807 A1) in further view of Deji (“Ensuring Accurate Time-Keeping in Virtualized Active Directory Infrastructure”).
Regarding claim 1, Johnson discloses an apparatus comprising: a network interface device comprising a network interface; and circuitry to (column 19, 1-4: the resource stack 602 includes a number of hardware resources 604, such as one or more central processing units (CPUs) 612; solid state drives (SSDs) or other storage devices 610; a network interface card (NIC) 606):
receive time information of a device that executes a service (column 14, 21-24: an application run 402 on a computing resource, such as a personal computer or remote server, this include a number of virtual machines executing on that computing resource. Column 14, 30-37: The clock monitor request a current time value from a clock of the computing resource, such as a system clock or CPU clock, the current time value can be received as indicated by the clock) and based on the time information indicating that a jitter level for the device is outside of a permitted jitter range for the service (column 5, 55-57: the time values should agree to within an allowable jitter or variance value or range, or other acceptable variation amount, such as +/−1 ms), perform one or more actions to cause execution of the service on a second device (column 14, 43-45: The application (or clock monitor) can then compare 410 the received current time value to the time value expected by the application. Column 14, 65-column 15,3: it is determined that the reported current time and expected time values do not agree, at least within a specified amount of variance or jitter, the application can be caused 414 to execute in a time loss management mode. Column 15,43-44: action can be taken, such as to move the workload to another server).
However, Johnson does not disclose a network interface device comprising a host interface; a direct memory access (DMA) circuitry, wherein the clock signal jitter is based on a jitter level of the clock signal utilized by the second device relative to a reference clock signal and wherein the execution of the service on the second device comprises performance of the service on a processor of the second device timed according to the clock signal.
In an analogous art, Hubbe discloses a network interface device (fig. 4) comprising a host interface ([0045]: a NIC can have a peripheral component interconnect express (PCIe) connection 431 for communicating with the host computer); a direct memory access (DMA) circuitry ([0055]: The NOC may provide cache coherent interconnect between the NOC masters, including the packet processing pipeline circuits 408, CPU cores 403, memory interface 415, and PCIe interface 427. The interconnect may distribute memory transactions across a plurality of memory interfaces (i.e. DMA circuitry), wherein the clock signal jitter is based on a jitter level of the clock signal utilized by the second device relative to a reference clock signal ([0043]-[0044]: The HW clock synchronization executable code 301 use the network clock domain packets 102 (e.g. PTP or NTP) to synchronize HW clock I 302 within the CD (synchronizes HW clock I 302 to the reference clock 101). The HW clock synchronization executable code 301 can also produce local HW clock quality metrics 310 for local clocks such as HW clock I 302, the quality metrics (e.g. jitter) include a time correction variance value 313 and a rate correction variance value 316. The HW clock synchronization executable code 301 can detect that the HW clock is ahead of or behind the reference clock) and wherein the execution of the service on the second device comprises performance of the service on a processor of the second device timed according to the clock signal (fig. 12-13, [0077]: a VM in a vCD that has migrated between host computers. VM 2 is running on host computer 2 (e.g. second device). VM 2 can read time values from HW clock B via a vCD access point provided by NIC 2. HW clock B is synchronized with vCD 1 which has reference clock 1 as the reference clock (e.g. second device timed according to clock signal).
Therefore, it would have been obvious before the effective filed date of the claimed invention to a person having ordinary skill in the art to modify Johnson to comprise “a network interface device comprising a host interface; a direct memory access (DMA) circuitry, wherein the clock signal jitter is based on a jitter level of the clock signal utilized by the second device relative to a reference clock signal and wherein the execution of the service on the second device comprises performance of the service on a processor of the second device timed according to the clock signal” taught by Hubbe.
One of ordinary skilled in the art would have been motivated because it would have enabled to synchronize hardware clocks within a the virtual clock domain, thereby allowing virtual machine migration between servers without losing synchronization with the virtual clock domain (Hubber, [0035], [0036]).
However, Johnson-Hubbe does not disclose based on the time information indicating that a jitter level outside of a permitted jitter range for the service, perform one or more actions to cause execution of the service on a second device that operates based on a clock signal jitter that is within the permitted jitter range.
In an analogous art, Deji discloses based on the time information indicating that a jitter level outside of a permitted jitter range for the service (pg. 1, [0003]: Clients, Servers, and domain Controllers in a given Forest be synchronized, or (in a worst-case scenario) never be allowed to deviate by more than 5 minutes (e.g. permitted clock variance), perform one or more actions to cause execution of the service on a second device that operates based on a clock signal jitter that is within the permitted jitter range (pg. 3, [0015]: In the event that a virtualized Domain Controller’s clock becomes skewed (e.g. outside permitted clock variance) as a result of incorrect time on its Host, the quickest remedy is to migrate the VM to (and restart the VM on) another Host which has a known good clock (i.e. within permitted clock variance).
Therefore, it would have been obvious before the effective filed date of the claimed invention to a person having ordinary skill in the art to modify Johnson-Hubbe to comprise “based on the time information indicating that a jitter level outside of a permitted jitter range for the service, perform one or more actions to cause execution of the service on a second device that operates based on a clock signal jitter that is within the permitted jitter range” taught by Deji.
One of ordinary skilled in the art would have been motivated because it would have enabled to migrate the virtual machine from a host having an inaccurate clock to another host having a synchronize clock, in order to remedy the clock skew and maintain accurate timing of the virtual machine (Deji, pg. 1, [0001]; pg. 3, [0015]).
Regarding claim 2, Johnson-Hubbe-Deji discloses the apparatus of claim 1, wherein the service is part of a group of distributed services executing on one or more of: a chiplet, processor, server (Johnson, column 14, 21-24: an application run 402 on a computing resource, such as or remote server, this include a number of virtual machines executing on that computing resource), warehouse computer, data center, or multiple data centers
Regarding claim 3, Johnson-Hubbe-Deji discloses the apparatus of claim 1, wherein the one or more actions comprise one or more of: reduce offset of the clock signal from a reference clock signal, cause the device to be disabled to execute the service, or request another device or server to be added for use to execute the service (Hubbe, [0044]: The HW clock synchronization executable code 301 can detect that the HW clock is advancing too quickly or too slowly with respect to the reference clock. As such, a rate correction can adjust the rate at which the HW clock advances). The same rationale applies as in claim 1.
Regarding claim 4, Johnson-Hubbe-Deji discloses the apparatus of claim 3, wherein the reference clock signal is synchronized with a main timer based on one or more of: Institute of Electrical and Electronics Engineers (IEEE) 1588 Precision Time Protocol (PTP), IEEE1588-2019, or White Rabbit Project (Hubbe, [0040]: A reference clock 101 can send network clock domain packets 102 (e.g., PTP or network time protocol (NTP) packets) to a network interface card 103 (NIC) installed in a host computer 114). The same rationale applies as in claim 1.
Regarding claim 8, Johnson-Hubbe-Deji discloses the apparatus of claim 1, wherein the network interface device comprises one or more of: an infrastructure processing unit (IPU), data processing unit (DPU), smart NIC (Hubbe, [0040]: The NIC can be a distributed service card or a smartNIC), forwarding element, switch, router, network interface controller, or network-attached appliance. The same rationale applies as in claim 1.
Regarding claim 9, Johnson-Hubbe-Deji discloses the apparatus of claim 1, wherein the second device comprises a host system that is communicatively coupled to the network interface device and wherein the host system is to utilize the clock signal to time operations of the service (Hubbe, [0036]: Another advantage is that a virtual machine can be migrated between servers without losing synchronization with the other VMs in a workload. [0074]: . VM 1 and VM 2 can read time values from HW clock A via vCD access points provided by NIC 1). The same rationale applies as in claim 1.
Regarding claim 10, Johnson-Hubbe-Deji discloses the apparatus of claim 9, comprising a data center, wherein the data center comprises device and second device (Hubbe, [0034]: Data center with servers virtual machines. Furthermore, a tenant's workloads may be in different areas of the data center. The tenant's workloads can include numerous VMs that may migrate from one server to a different server). The same rationale applies as in claim 1.
Regarding claim 11, Johnson discloses at least one non-transitory computer-readable medium comprising instructions stored thereon, that if executed by one or more processors (column 19, 1-4: the resource stack 602 includes a number of hardware resources 604, such as one or more central processing units (CPUs) 612; solid state drives (SSDs) or other storage devices 610; a network interface card (NIC) 606), cause the one or more processors to: execute a driver to configure a network interface device (column 19, 51-53: backend driver 626 of the host kernel 624 which can obtain access to the data and communicate it directly to the hardware device, such as the NIC 606) to perform: determine a difference between a clock signal of a device and a reference clock signal (column 5, 55-57: the time values should agree to within an allowable jitter or variance value or range, or other acceptable variation amount, such as +/−1 ms. Column 14, 43-49: The application (or clock monitor) can then compare 410 the received current time value to the time value expected by the application. If it is determined 412 that the reported current time and expected time values agree, at least within a matching threshold, criterion, or range allowing for some slight amount of normal jitter or variation) and
based on the difference being outside of a permitted jitter range for a service, perform one or more actions to cause execution of the service on the device or a second device (Column 14, 65-column 15,3: it is determined that the reported current time and expected time values do not agree, at least within a specified amount of variance or jitter, the application can be caused 414 to execute in a time loss management mode. Column 15,43-44: action can be taken, such as to move the workload to another server), wherein the one or more actions comprise one or more of: cause the service to execute on the second device (Column 15,43-44: action can be taken, such as to move the workload to another server).
However, Johnson does not disclose wherein the device operates based on a second clock signal that is within the permitted jitter range, the second device operates based on a third clock signal that is within the permitted jitter range.
In an analogous art, Hubbe discloses wherein the device operates based on a second clock signal that is within the permitted jitter range, the second device operates based on a third clock signal that is within the permitted jitter range ([0008]: the NIC associates a virtual clock domain identifier with the clock domain identifier, a second NIC is installed in a second host computer and includes a second hardware clock, the hardware clock and the second hardware clock are synchronized within a virtual clock domain).
Therefore, it would have been obvious before the effective filed date of the claimed invention to a person having ordinary skill in the art to modify Johnson to comprise “wherein the device operates based on a second clock signal that is within the permitted jitter range, the second device operates based on a third clock signal that is within the permitted jitter range” taught by Hubbe.
One of ordinary skilled in the art would have been motivated because it would have enabled to synchronize hardware clocks within the virtual clock domain, thereby allowing virtual machine migration between servers without losing synchronization with the virtual clock domain (Hubber, [0035], [0036]).
However, Johnson-Hubbe discloses wherein the one or more actions comprise one or more of: cause the service to execute on the second device that operates within the permitted jitter range, reduce offset of the clock signal from the reference clock signal to be within the permitted jitter range and permit execution of the service on the device, or cause the device to be disabled and not execute the service.
In an analogous art, Deji discloses wherein the one or more actions comprise one or more of: cause the service to execute on the second device that operates within the permitted jitter range (pg. 1, [0003]: Clients, Servers, and domain Controllers in a given Forest be synchronized, or (in a worst-case scenario) never be allowed to deviate by more than 5 minutes (e.g. permitted clock variance. pg. 3, [0015]: In the event that a virtualized Domain Controller’s clock becomes skewed (e.g. outside permitted clock variance) as a result of incorrect time on its Host, the quickest remedy is to migrate the VM to (and restart the VM on) another Host which has a known good clock (i.e. within permitted clock variance), reduce offset of the clock signal from the reference clock signal to be within the permitted jitter range and permit execution of the service on the device, or cause the device to be disabled and not execute the service
Therefore, it would have been obvious before the effective filed date of the claimed invention to a person having ordinary skill in the art to modify Johnson-Hubbe to comprise “wherein the one or more actions comprise one or more of: cause the service to execute on the second device that operates within the permitted jitter range, reduce offset of the clock signal from the reference clock signal to be within the permitted jitter range and permit execution of the service on the device, or cause the device to be disabled and not execute the service” taught by Deji.
One of ordinary skilled in the art would have been motivated because it would have enabled to migrate the virtual machine from a host having an inaccurate clock to another host having a synchronize clock, in order to remedy the clock skew and maintain accurate timing of the virtual machine (Deji, pg. 1, [0001]; pg. 3, [0015]).
Regarding claims 12 and 17; the claims are interpreted and rejected for the same reason as set forth in claim 2.
Regarding claim 14; the claim is interpreted and rejected for the same reason as set forth in claim 4.
Regarding claim 16; the claim is interpreted and rejected for the same reason as set forth in claim 11.
Regarding claim 18; the claim is interpreted and rejected for the same reason as set forth in claim 3.
Regarding claim 19; the claim is interpreted and rejected for the same reason as set forth in claim 14.
Claims 5 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Johnson in view of Hubbe in view of Deji, as applied to claim 1, in further view of Banerjea et al. (US 2013/0173950 A1).
Regarding claim 5, Johnson-Hubbe-Deji discloses the apparatus of claim 1.
However, Johnson-Hubbe-Deji does not disclose wherein the time information is received from a connection consistent with general-purpose input/output (GPIO).
In an analogous art, Banerjea discloses wherein the time information is received from a connection consistent with general-purpose input/output (GPIO) ([0011], [0051]: the wireless communication unit 204 includes an available generic interface contact, such as a GPIO pin, in an embodiment. The communications units 202 and 204 can use these generic interface contact to transmit or receive synchronization signal).
Therefore, it would have been obvious before the effective filed date of the claimed invention to a person having ordinary skill in the art to modify Johnson-Hubbe-Deji to comprise “wherein the time information is received from a connection consistent with general-purpose input/output (GPIO)” taught by Banerjea.
One of ordinary skilled in the art would have been motivated because it would have enabled for efficiently synchronizes processing units using a simple interface (Banerjea, [0019]).
Regarding claim 20; the claim is interpreted and rejected for the same reason as set forth in claim 5.
Claims 6 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Johnson in view of Hubbe in view of Deji, as applied to claim 1, in further view of Polehn et al. (US 2022/0014455 A1).
Regarding claim 6, Johnson-Hubbe-Deji discloses the apparatus of claim 1.
However, Johnson-Hubbe-Deji does not disclose wherein the permitted jitter range for the service is based on a service level agreement (SLA) for the service.
In an analogous art, Polehn discloses wherein the permitted jitter range for the service is based on a service level agreement (SLA) for the service. ([0056]: The SLA information may indicate threshold performance values, such as latency, jitter, packet loss, and/or other values for other performance metrics)
Therefore, it would have been obvious before the effective filed date of the claimed invention to a person having ordinary skill in the art to modify Johnson-Hubbe-Deji to comprise “wherein the permitted jitter range for the service is based on a service level agreement (SLA) for the service” taught by Polehn.
One of ordinary skilled in the art would have been motivated because it would have enabled to evaluate a SLA to verify whether the SLA is being met or not (Polehn, [0057]).
Regarding claim 15; the claim is interpreted and rejected for the same reason as set forth in claim 6.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Johnson in view of Hubbe in view of Deji, as applied to claim 1, in further view of Wen et al. (US 2021/0243712 A1).
Regarding claim 7, Johnson-Hubbe-Deji discloses the apparatus of claim 1.
However, Johnson-Hubbe-Deji does not disclose wherein the clock signal comprises a 1 pulse per second (PPS) indicator signal.
In an analogous art, Wen discloses wherein the clock signal comprises a 1 pulse per second (PPS) indicator signal ([0075]: The timing chip processes the received physical layer data and outputs a local absolute time information and a frequency reference signal 1pps of the terminal, and the terminal adjusts a terminal reference time according to the absolute time information and the frequency reference signal 1pps outputted by the timing chip).
Therefore, it would have been obvious before the effective filed date of the claimed invention to a person having ordinary skill in the art to modify Johnson-Hubbe-Deji to comprise “wherein the clock signal comprises a 1 pulse per second (PPS) indicator signal.” taught by Wen.
One of ordinary skilled in the art would have been motivated because it would have enabled to adjust the terminal reference time according to absolute time information and the frequency reference signal (Wen, [0075]).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Johnson in view of Hubbe in view of Deji, as applied to claim 1, in view of Pitigoi et al. (US 2019/0020433 A1).
Regarding claim 21, Johnson-Hubbe-Deji discloses the apparatus of claim 1.
However, Johnson-Hubbe-Deji does not disclose wherein the clock signal jitter is based on comparisons of edges of the clock signal with edges of the reference clock signal.
In an analogous art, Pitigoi discloses wherein the clock signal jitter is based on comparisons of edges of the clock signal with edges of the reference clock signal ([0062]: The predetermined T_Fq may be the same as described above. Here, the sensor 310 may be configured a priori with the predetermined T_Fq. Once the sensor 310 receives the timer correction messages, it may compare the duration of the time interval bookended by the two identifiable significant edges included with the timer correction messages, as measured by the timer 315 in the sensor 310, with the predetermined T_Fq, also as measured by the sensor timer, derive a timer correction factor accordingly, and apply the timer correction factor to correct the internal sensor timer).
Therefore, it would have been obvious before the effective filed date of the claimed invention to a person having ordinary skill in the art to modify Johnson-Hubbe-Deji to comprise “wherein the clock signal jitter is based on comparisons of edges of the clock signal with edges of the reference clock signal” taught by Pitigoi.
One of ordinary skilled in the art would have been motivated because it would have enabled adjusting the time interval between samples based on the hardware synchronization event and the offset (Pitigoi, [0006]).
Additional References
The prior art made of record and not relied upon is considered pertinent to applicants disclosure.
Zaidman et al., US 2019/0155327 A1: System and Method for Time Stamp Synchronization.
Conclusion
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/J.C.T/Examiner, Art Unit 2454
/KAMAL B DIVECHA/Supervisory Patent Examiner, Art Unit 2453
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