DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Information disclosure statement filed 6 March 2024 has been fully considered.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 162 shown in FIG. 1C and 368 shown in FIG. 3B. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-30 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 3, 5, 6, 29, and 30 recite the limitations, “a first pin,” and, “a second pin.” Claims 14, 16, 18-21, 26, and 27 further recite at least third, fourth, fifth, and sixth pins. It is unclear as to what type of element (e.g. a metal line, a via, etc.) the claimed pins represent.
Claims 1, 29, and 30 recite the limitation, “a source region, common to the first and second logic gates.” It is unclear how the source region common to the first and second logic gates functions as a source region. A source region is typically a doped region of a field effect transistor. However, the claimed source region common to the first and second logic gates comprises a plurality of diffusion regions, and does not function as a source of a field effect transistor.
Claims 1, 29, and 30 recite the limitation, “wherein the first and second pins are on a first metal track directly over the common source region.” It is unclear whether the first and second pins are directly over the common source region, the metal track is directly over the common source region, or both.
Claims 2, 4, 7-13, 15, 17, 22-25, and 28 are rejected for merely containing the flaws of the parent claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-17, 19, 20, and 29 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Peng et al. (US Patent Application Publication 2021/0375851, hereinafter Peng ‘851) of record.
With respect to claim 1, Peng ‘851 teaches (FIGs. 3B, 5A, and 5G) an integrated circuit (IC) cell as claimed, comprising:
a first logic gate (A1) comprising a first polysilicon structure (204a) and a first pin (input to 226a1(A1) characterized in FIG. 3B) ([0067-0068]);
a second logic gate (A2) comprising a second polysilicon structure (204b) and a second pin (input to 226b1(A2) characterized in FIG. 3B), wherein the second polysilicon structure is spaced apart and adjacent to the first polysilicon structure (204a) in a cell row direction ([0067-0068]); and
a source region (within TK3, comprising SD2 and SD9), common to the first (A1) and second (A2) logic gates, situated between the first (204a) and second (204b) polysilicon structures, wherein the first (input to 226a1(A1)) and second (input to 226b1(A2)) pins are on a first metal track (226a1 and 226b1) directly over the common source region ([0067-0068]).
With respect to claim 2, Peng ‘851 teaches wherein the first metal track (226a1 and 226b1) is on an M1 metal layer ([0067-0068]).
With respect to claim 3, Peng ‘851 teaches wherein the first (input to 226a1(A1)) and second (input to 226b1(A2)) pins comprise input pins, respectively ([0067-0068]).
With respect to claim 4, Peng ‘851 teaches further comprising: a first power rail (222a); a first diffusion region (SD2) electrically connected to the first power rail at the common source region (within TK3, comprising SD2 and SD9); a second power rail (222b); and a second diffusion region (SD9) electrically connected to the second power rail at the common source region ([0067-0068]).
With respect to claim 5, Peng ‘851 teaches wherein the first pin (input to 226a1(A1)) is situated directly over the first diffusion region (SD2), and the second pin (input to 226b1(A2)) is situated directly over the second diffusion region (SD9) ([0067-0068]).
With respect to claim 6, Peng ‘851 teaches further comprising first (226a1) and second (226b1) intracell interconnects electrically coupling the first (input to 226a1(A1)) and second (input to 226b1(A2)) pins to the first (204a) and second (204b) polysilicon structures, respectively ([0067-0068]).
With respect to claim 7, Peng ‘851 teaches wherein the first (226a1) and second (226b1) intracell interconnects are situated directly over the first (SD2) and second (SD9) diffusion regions, respectively ([0067-0068]).
With respect to claim 8, Peng ‘851 teaches wherein the first (226a1) and second (226b1) intracell interconnects are on an M0 metal layer (this layer may be defined as an M0 layer) ([0067-0068]).
With respect to claim 9, Peng ‘851 teaches further comprising a set of intracell interconnects (226) including the first (226a1) and second (226b1) intracell interconnects, wherein each intracell interconnect is elongated in the cell row direction and spaced apart from each other in a cell column direction, and wherein the first and second intracell interconnects among the set of intracell interconnects are situated closest to the first (222a) and second (222b) power rails, respectively ([0067-0068]).
With respect to claim 10, Peng ‘851 teaches wherein the first logic gate (A1) comprises: a first p-channel metal oxide semiconductor field effect transistor (PMOS FET) (defined by gate 204a, SD1, and SD2, wherein SD1 and SD2 are n-type), wherein the first polysilicon structure (204a) serves as a first gate for the first PMOS FET, and wherein the first PMOS FET includes a first source (SD2) situated over an n+ diffusion region within the common source region (within TK3, comprising SD2 and SD9); and a first n-channel metal oxide semiconductor field effect transistor (NMOS FET) (defined by gate 204a, SD9, and SD10, wherein SD9 and SD10 are p-type), wherein the first polysilicon structure serves as a first gate for the first NMOS FET, and wherein the first NMOS FET includes a first source (SD9) situated over a p+ diffusion region within the common source region ([0067-0068]).
With respect to claim 11, Peng ‘851 teaches wherein the second logic gate (A2) comprises: a second PMOS FET (defined by gate 204b, SD2, and SD3, wherein SD2 and SD3 are n-type), wherein the second polysilicon structure (204b) serves as a second gate for the second PMOS FET, and wherein the second PMOS FET shares the first source (SD2) with the first PMOS FET; and a second NMOS FET (defined by gate 204b, SD8, and SD9, wherein SD8 and SD9 are p-type), wherein the second polysilicon structure serves as a second gate for the second NMOS FET, and wherein the second NMOS FET shares the first source (SD9) with the first NMOS FET ([0067-0068]).
With respect to claim 12, Peng ‘851 teaches further comprising: a third polysilicon structure (206a) spaced apart and adjacent to the first polysilicon structure (204a) in the cell row direction; and a fourth polysilicon structure (204c) spaced apart and adjacent to the second polysilicon structure (204b) in the cell row direction ([0067-0068]).
With respect to claim 13, Peng ‘851 teaches wherein: the first PMOS FET (defined by gate 204a, SD1, and SD2, wherein SD1 and SD2 are n-type) includes a first drain (SD1) situated over the n+ diffusion region between the first (204a) and third (206a) polysilicon structures; the first NMOS FET (defined by gate 204a, SD9, and SD10, wherein SD9 and SD10 are p-type) includes a first drain (SD10) situated over the p+ diffusion region between the first and third polysilicon structures; the second PMOS FET (defined by gate 204b, SD2, and SD3, wherein SD2 and SD3 are n-type) includes a second drain (SD3) situated over the n+ diffusion region between the second (204b) and fourth (204c) polysilicon structures; and the second NMOS FET (defined by gate 204b, SD8, and SD9, wherein SD8 and SD9 are p-type) includes a second drain (SD8) situated over the p+ diffusion region between the second and fourth polysilicon structures ([0067-0068]).
With respect to claim 14, Peng ‘851 teaches wherein: the first logic gate (A1) includes a third pin (input to 224a) on a second metal track (224a) situated between the first (204a) and third (206a) polysilicon structures; and the second logic gate (A2) includes a fourth pin (input to 224b2) on a third metal track (224b2) situated between the second (204b) and fourth (204c) polysilicon structures ([0067-0068]).
With respect to claim 15, Peng ‘851 teaches wherein each adjacent pair of the first (204a), second (204b), third (206a), and fourth (204c) polysilicon structures is separated by a first pitch, wherein each adjacent pair of the first (226a1 and 226b1), second (224a), and third (224b2) metal tracks is separated by a second pitch, and wherein a ratio of the first pitch to the second pitch is one (1) ([0035]).
With respect to claim 16, Peng ‘851 teaches wherein the third (input to 224a) and fourth (input to 224b2) pins comprise output pins, respectively ([0067-0068]).
With respect to claim 17, Peng ‘851 teaches wherein the first (204a) and second (204b) polysilicon gate structures comprise cell terminating polysilicon gate structures ([0067-0068]).
With respect to claim 19, Peng ‘851 teaches wherein the third (input to 224a) and fourth (input to 224b2) pins are situated between the n+ and p+ diffusion regions ([0067-0068]).
With respect to claim 20, Peng ‘851 teaches wherein the third (input to 224a) and fourth (input to 224b2) pins comprise input pins, respectively ([0067-0068]).
With respect to claim 29, Peng ‘851 teaches (FIGs. 3B, 5A, and 5G) a method as claimed, comprising:
generating a first input logic signal (signal to first logic gate A1) ([0067-0068]);
generating a second input logic signal (signal to second logic gate A2) ([0067-0068]);
applying the first (signal to first logic gate A1) and second (signal to second logic gate A2) logic signals to first (input to 226a1(A1) characterized in FIG. 3B) and second (input to 226b1(A2) characterized in FIG. 3B) pins of an integrated circuit (IC) cell ([0067-0068]), wherein the IC cell includes:
a first logic gate (A1) comprising a first polysilicon structure (204a) and the first pin (input to 226a1(A1) characterized in FIG. 3B) ([0067-0068]);
a second logic gate (A2) comprising a second polysilicon structure (204b) and the second pin (input to 226b1(A2) characterized in FIG. 3B), wherein the second polysilicon structure is spaced apart and adjacent to the first polysilicon structure (204a) in a cell row direction ([0067-0068]); and
a source region (within TK3, comprising SD2 and SD9), common to the first (A1) and second (A2) logic gates, situated between the first (204a) and second (204b) polysilicon structures, wherein the first (input to 226a1(A1)) and second (input to 226b1(A2)) pins are on a first metal track (226a1 and 226b1) directly over the common source region ([0067-0068]);
receiving a first output logic signal (signal from first logic gate A1) from the IC cell, wherein the first output logic signal is based on the first input logic signal (signal to first logic gate A1) ([0067-0068]); and
receiving a second output logic signal (signal from first logic gate A2) from the IC cell, wherein the second output logic signal is based on the second input logic signal (signal to first logic gate A2) ([0067-0068]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 30 is rejected under 35 U.S.C. 103 as being unpatentable over Peng ‘851 in view of Morrow et al. (US Patent Application Publication 2022/0028779, hereinafter Morrow ‘779) of record.
With respect to claim 30, Peng ‘851 teaches (FIGs. 3B, 5A, and 5G) a wireless communication device substantially as claimed, comprising:
an integrated circuit (IC), wherein the IC includes a set of one or more signal processing cores (500G) including an IC cell, comprising:
a first logic gate (A1) comprising a first polysilicon structure (204a) and a first pin (input to 226a1(A1) characterized in FIG. 3B) ([0067-0068]);
a second logic gate (A2) comprising a second polysilicon structure (204b) and a second pin (input to 226b1(A2) characterized in FIG. 3B), wherein the second polysilicon structure is spaced apart and adjacent to the first polysilicon structure (204a) in a cell row direction ([0067-0068]); and
a source region (within TK3, comprising SD2 and SD9), common to the first (A1) and second (A2) logic gates, situated between the first (204a) and second (204b) polysilicon structures, wherein the first (input to 226a1(A1)) and second (input to 226b1(A2)) pins are on a first metal track (226a1 and 226b1) directly over the common source region ([0067-0068]).
Thus, Peng ‘851 is shown to teach all the features of the claim with the exception of:
at least one antenna; and
a transceiver coupled to the at least one antenna;
wherein the integrated circuit (IC) is coupled to the transceiver.
However, Morrow ‘779 teaches (FIG. 12) a wireless communication device comprising at least one antenna (“antenna”) and a transceiver (1225) coupled to the at least one antenna, wherein an integrated circuit (IC) (1235 and 1250) is coupled to the transceiver to provide mobile computing ([0054-0056]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the wireless communication device of Peng ‘851 further comprising at least one antenna; and a transceiver coupled to the at least one antenna; wherein the integrated circuit (IC) is coupled to the transceiver as taught by Morrow ‘779 to provide mobile computing.
Allowable Subject Matter
Claims 18 and 21-28 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record fails to teach the integrated circuit (IC) cell of claim 18 in the combination of limitations as claimed, noting particularly the limitation, “wherein: the third pin is electrically coupled to the respective first drains of the first PMOS and NMOS FETs; and the fourth pin is electrically coupled to the respective second drains of the second PMOS and NMOS FETs.” The third (input to 224a) and fourth (input to 224b2) pins of Peng ‘851 are not electrically coupled to both the respective first drains (SD1 and SD10) of the first PMOS and NMOS FETs and the respective second drains (SD3 and SD8) of the second PMOS and NMOS FETs respectively.
The prior art of record fails to teach the integrated circuit (IC) cell of claim 21 in the combination of limitations as claimed, noting particularly the limitation, “further comprising: a first intracell interconnect electrically coupling the third pin to the third polysilicon structure; and a second intracell interconnect electrically coupling the fourth pin to the fourth polysilicon structure.” First and second intracell interconnects do not electrically couple the third pin (input to 224a) to the third polysilicon structure (206a) and the fourth pin (input to 224b2) to the fourth polysilicon (204c) structure of Peng ‘851 respectively.
The prior art of record fails to teach the integrated circuit (IC) cell of claim 23 in the combination of limitations as claimed, noting particularly the limitation, “wherein the first logic gate comprises: a third PMOS FET, wherein the third polysilicon structure serves as a third gate for the third PMOS FET, and wherein the third PMOS FET includes a third drain coupled to the first drain of the first PMOS FET; and a third NMOS FET, wherein the third polysilicon structure serves as a third gate for the third NMOS FET, and wherein the third NMOS FET includes a third source coupled to the first drain of the first NMOS FET.” Peng ‘851 is silent to at least a third PMOS FET, wherein the third polysilicon structure serves as a third gate for the third PMOS FET, and wherein the third PMOS FET includes a third drain coupled to the first drain of the first PMOS FET.
The prior art of record fails to teach the integrated circuit (IC) cell of claim 25 in the combination of limitations as claimed, noting particularly the limitation, “further comprising: a fifth polysilicon structure spaced apart and adjacent to the third polysilicon structure in the cell row direction; and a sixth polysilicon structure spaced apart and adjacent to the fourth polysilicon structure in the cell row direction.” Peng ‘851 is silent to at least a fifth polysilicon structure spaced apart and adjacent to the third polysilicon structure in the cell row direction.
Claims 22 and 24-28 are indicated as containing allowable subject matter based merely upon their dependencies from claims 21, 23, and 25 indicated as containing allowable subject matter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Do et al (US Patent Application Publication 2019/0355749) and Lee et al. (US Patent Application Publication 2020/0395354) teach integrated circuit (IC) cell layouts.
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/C.M.R./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893