Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION This action is responsive to the Application filed on 11/23/2022 . Claims 1- 8 are pending in the case. Claims 1 and 5 are independent claims. Priority Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. IN202131054346, filed on 11/24/2021. Information Disclosure Statement The information disclosure statement (IDS) submitted on 9/25/2023 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Double Patenting Claims 1-8 of this application is patentably indistinct from claims 1 , 3-5, 7- 8 of Application No. 17993697. Pursuant to 37 CFR 1.78(f), when two or more applications filed by the same applicant or assignee contain patentably indistinct claims, elimination of such claims from all but one application may be required in the absence of good and sufficient reason for their retention during pendency in more than one application. Applicant is required to either cancel the patentably indistinct claims from all but one application or maintain a clear line of demarcation between the applications. See MPEP § 822. Please see the comparison using citation format: Claim 1 of current application: 1. A method comprising: obtaining a gate teleportation circuit for a predetermined number of qubits, wherein the gate teleportation circuit is to transfer an unknown quantum state of a qubit to another qubit in a quantum computing model; segmenting the gate teleportation circuit into a plurality of sub-circuits based on the predetermined number of qubits, wherein each of the plurality of sub-circuits comprises at least one qubit; performing a gate teleportation operation on each of the plurality of sub-circuits sequentially, wherein the gate teleportation operation on each of the plurality of sub-circuits is performed based on the at least one qubit of a given sub-circuit and an output of a gate teleportation operation performed on a sub-circuit which is previous to the given sub-circuit; and measuring an output of the gate teleportation operation on a last sub- circuit from the plurality of sub-circuits. And Claim 2 of current application , t he method as claimed in claim 1, wherein the gate teleportation circuit is prepared based on Measurement Based Quantum Computing (MBQC) model. ( claim 1 of 17/993697, “ A method comprising: obtaining a gate teleportation circuit for a predetermined number of qubits, wherein the gate teleportation circuit is to transfer an unknown quantum state of a qubit to another qubit in a quantum computing model, and wherein the gate teleportation circuit is compliant with Measurement Based Quantum Computing (MBQC) model of quantum computing; simulating segmentation of the gate teleportation circuit into a plurality of sub-circuits based on the predetermined number of qubits, wherein each of the plurality of sub-circuits comprises at least one qubit; simulating a gate teleportation operation on each of the plurality of sub-circuits sequentially, wherein the gate teleportation operation on each of the plurality of sub-circuits is simulated based on the at least one qubit of a given sub-circuit and an output of a gate teleportation operation simulated on a sub-circuit which is previous to the given sub-circuit; and measuring an output of simulation on gate teleportation operation on a last sub-circuit from the plurality of sub-circuits . ”) Claim 3 of current application . The method as claimed in claim 1, wherein each of the plurality of sub-circuits comprises 'n' qubits when the predetermined number of qubits is 2 n . ( claim 3 of 17/993697, “The method as claimed in claim 1, wherein each of the plurality of sub-circuits comprises 'n' qubits when the predetermined number of qubits is 2 n . ”) Claim 4 of current application . The method as claimed in claim 1, wherein each of the plurality of sub-circuits comprises 'n+1' qubits when the predetermined number of qubits is more than 2 n and less than 2 n+1 . ( claim 4 of 17/993697, “The method as claimed in claim 1, wherein each of the plurality of sub-circuits comprises 'n+1' qubits when the predetermined number of qubits is more than 2 n and less than 2 n+1 .. ”) Claim 5 of current application . A quantum computing system comprising: a circuit reception engine to obtain a gate teleportation circuit for a predetermined number of qubits, wherein the gate teleportation circuit is utilized for transferring an unknown quantum state of a qubit to another qubit in a quantum computing model; a circuit segmentation engine coupled to the circuit reception engine to segment the gate teleportation circuit into a plurality of sub-circuits based on the predetermined number of qubits, wherein each of the plurality of sub- circuits comprises at least one qubit; and a gate teleportation engine coupled to the circuit segmentation engine to: perform a gate teleportation operation on each of the plurality of sub-circuits sequentially, wherein the gate teleportation operation on each of the plurality of sub-circuits is performed based on an at least one qubit of a given sub-circuit and an output of a gate teleportation operation performed on a sub-circuit which is previous to the given sub-circuit; and measure an output of the gate teleportation operation on a last sub-circuit from the plurality of sub-circuits. Claim 6 of current application , t he quantum computing system as claimed in claim 5, wherein the gate teleportation circuit is prepared based on Measurement Based Quantum Computing (MBQC) model. ( claim 5 of 17/993697, “A simulator for a quantum computing system comprising: a circuit reception engine to obtain a gate teleportation circuit for a predetermined number of qubits, wherein the gate teleportation circuit is utilized for transferring an unknown quantum state of a qubit to another qubit in a quantum computing model, and wherein the gate teleportation circuit is complaint with Measurement Based Quantum Computing (MBQC) model of quantum computing; a circuit segmentation engine coupled to the circuit reception engine to simulate segmentation of the gate teleportation circuit into a plurality of sub-circuits based on the predetermined number of qubits, wherein each of the plurality of sub-circuits comprises at least one qubit; and a gate teleportation engine coupled to the circuit segmentation engine to: simulate a gate teleportation operation on each of the plurality of sub-circuits sequentially, wherein the gate teleportation operation on each of the plurality of sub-circuits is simulated based on an at least one qubit of a given sub-circuit and an output of a gate teleportation operation simulated on a sub-circuit which is previous to the given sub-circuit; and measure an output of the gate teleportation operation on a last sub-circuit from the plurality of sub-circuits . ”) Claim 7 of current application . The quantum computing system as claimed in claim 5, wherein each of the plurality of sub-circuits comprises 'n' qubits when the predetermined number of qubits is 2 n . ( claim 7 of 17/993697, “The method as claimed in claim 5 , wherein each of the plurality of sub-circuits comprises 'n' qubits when the predetermined number of qubits is 2 n . ”) Claim 8 of current application . The quantum computing system as claimed in claim 5, wherein each of the plurality of sub-circuits comprises 'n+1' qubits when the predetermined number of qubits is more than 2 n and less than 2 n+1 . ( claim 8 of 17/993697, “The method as claimed in claim 5 , wherein each of the plurality of sub-circuits comprises 'n+1' qubits when the predetermined number of qubits is more than 2 n and less than 2 n+1 .. ”) The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure: “64-qubit quantum circuit simulation”, Chen et al, 2018: Chen discloses c lassical simulations of quantum circuits are limited in both space and time when the qubit count is above 50, the realm where quantum supremacy reigns. However, recently, for the low depth circuit with more than 50 qubits, there are several methods of simulation proposed by teams at Google and IBM. Here, we present a scheme of simulation which can extract a large amount of measurement outcomes within a short time, achieving a 64-qubit simulation of a universal random circuit of depth 22 using a 128-node cluster, and 56- and 42-qubit circuits on a single PC. We also estimate that a 72-qubit circuit of depth 23 can be simulated in about 16 h on a supercomputer identical to that used by the IBM team. Moreover, the simulation processes are exceedingly separable, hence parallelizable, involving just a few inter-process communications. Our work enables simulating more qubits with less hardware burden and provides a new perspective for classical simulations . However, Chen does not disclose the claimed invention as a whole. Gonthier et al ( US 20220121979 A1 ): A system and method for initializing and optimizing a variational quantum circuit on a hybrid quantum-classical computer, comprising a set of gates and a set of initial parameters representing a model of a physical system. A quantum circuit is generated comprising a set of smaller contiguous subcomponents which can be independently optimized to minimize a property of the physical system, such as ground state energy or the absorption spectrum of a molecule. At least one entangling gate is introduced between at least two circuit subcomponents. The initial parameters of the circuit components may be set according to values obtained from a parameter library. Once the initial parameters are set, the circuit components of the quantum computer proceed to optimization, which is independent for each subcomponent of the system. The optimization method may also include the use of a variational quantum eigensolver (VQE). However, Gonthier does not disclose the claimed invention as a whole. Applicant is required under 37 C.F.R. § 1.111(c) to consider these references fully when responding to this action. It is noted that any citation to specific pages, columns, lines, or figures in the prior art references and any interpretation of the references should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. In re Heck , 699 F.2d 1331, 1332-33, 216 U.S.P.Q. 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson , 397 F.2d 1006, 1009, 158 U.S.P.Q. 275, 277 (C.C.P.A. 1968)). In the interests of compact prosecution, Applicant is invited to contact the examiner via electronic media pursuant to USPTO policy outlined MPEP § 502.03. All electronic communication must be authorized in writing. Applicant may wish to file an Internet Communications Authorization Form PTO/SB/439. Applicant may wish to request an interview using the Interview Practice website: http://;www.uspto.gov/patent/laws-and-regulations/interview-practice. Applicant is reminded Internet e-mail may not be used for communication for matters under 35 U.S.C. § 132 or which otherwise require a signature. A reply to an Office action may NOT be communicated by Applicant to the USPTO via Internet e- mail. If such a reply is submitted by Applicant via Internet e-mail, a paper copy will be placed in the appropriate patent application file with an indication that the reply is NOT ENTERED. See MPEP § 502.03(II). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT HAIMEI JIANG whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-1590 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-F 9-5pm . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Mariela D Reyes can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT 571-270-1006 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HAIMEI JIANG/ Primary Examiner, Art Unit 2142