DETAIL ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This Office Action is in response to Applicant’s filing on 11/24/2022.
Priority
3. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
4. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
5. Claims 12-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding independent claim 12, Applicant claims, in L7 “the first control signal to conduct the input winding”, is indefinite. Applicant fails to point out if the first control signal is directed for the first switch unit, the second switching unit or entirely different/isolated control.
Going forward, under Broadest Reasonable Interpretation(s) (BRI), when rejecting claim 12, Examiner is interpreting ‘the first control signal’ is a drive signal to control the first switch unit.
There is a lack of antecedent basis for “the first control signal” – claim 12.
Claims 13-18 are depending from claim 12, inheriting same deficiencies, and thus rejected.
6. The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
7. Claim 19 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Regarding claim 19. Applicant claims, “a voltage converter, comprising the novel zero-voltage switching control circuit according to claim 1”, wherein both feature(s) “a voltage converter (see, claim 1 L1)” and “novel zero-voltage switching control circuit (see claim 1 L1)” are already claimed in claim 1. Therefore, claim 19 fails to further limit the subject matters of claim 1, which it depends from.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 102
8. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
9. Claims 1, 7, 12, 14, 16-17, 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jay M. Gordon (“Jay”, US Pub 2008/0225558).
Regarding independent claim 1, Jay teaches (Fig. 1, 4-5; Para 18-29. Additionally, note that Jay’s Fig. 1’s circuit design is similar to Applicant’s Fig. 7.) a novel zero-voltage switching control circuit, applied to a voltage converter (flyback converter),
the novel zero-voltage switching control circuit comprising a controller (74, 30, 60), a first switch unit (48), and a second switch unit (clamp circuit: 50, 52, 40, 72, 76, 56, 54),
the controller (74, 30, 60) being in a signal connection with the first switch unit (48) and the second switch unit (switch 50 of clamp circuit) respectively;
wherein the controller (74, 30, 60) is configured
to generate a first control signal (i.e., pwm1 for 48) to control the first switch unit (48) to switch on-off of an input winding (34’s primary winding “Pri. W”) of the voltage converter, and
to generate a second control signal (i.e., pwm2 for 50) to control the second switch unit (50) to switch on-off between an auxiliary winding (34’s auxiliary winding “Aux. W”) of the voltage converter and a negative voltage level (primary-side ground),
the input winding (Pri W) being coupled with the auxiliary winding (Aux W);
wherein before the first control signal (pwm1) conducts the input winding (Pri W),
the auxiliary winding (Aux W) of the voltage converter is conducted with the negative voltage level in advance, and
the input winding (Pri W) be forced to generate a negative current (I52 is representation of a negative voltage for Aux W. generated from a series connected node of ’56, 54’, and is a “zero potential” for the Vds of Pri W. In other words, when the 50 is conducted, the Pri W is forced to generate I52 so that the direction of the current I52 is flowing different direction first, to release the energy of a parasitic capacitance of 48 towards 72; thus, this energy is recovered through the 72, and will be released again for use in the next working cycle) based on the coupling between the input winding (Pri W) and the auxiliary winding (Aux. W), to release the energy of a parasitic capacitance in the first switch unit (parasitic capacitance of 48; Para 26), so as to further forcing the input winding (Pri W) polarity to reverse until the first switch unit cross voltage (drain-source voltage “Vds” of 48) decays to an expected low switching potential voltages, then to conduct the described input winding (Pri W).
Regarding claim 7, Jay teaches
wherein the second switch unit (clamp circuit: 50, 52, 40, 72, 76, 56, 54) comprises a second electronic switch (50) and a second capacitor (52, 54), and
the auxiliary winding is a single winding (Aux W);
one end of the second capacitor (i.e., 54’s one end) is electrically connected with one end of the auxiliary winding (Aux W), the other end of the auxiliary winding is connected to primary-side ground (Aux W’s other end connected to ground), and
the other end of the second capacitor is connected to primary-side ground (54’s other end connected to ground, via 44) via the second electronic switch (i.e., 50=on).
Regarding independent claim 12, Jay teaches (Fig. 1, 4-5; Para 18-29. Additionally, note that Jay’s Fig. 1’s circuit design is similar to Applicant’s Fig. 7) a novel zero-voltage switching control method, applied to a voltage converter (flyback converter),
the voltage converter (flyback converter) at least comprising a first switch unit (48) and a second switch unit (clamp circuit: 50, 52, 40, 72, 76, 56, 54),
wherein the first switch unit (48) is configured to switch on-off (using controller “CTRL”, which is combination of ‘74, 30, 60’ includes a 1st control signal pwm1 for driving 48) of an input winding (34’s primary winding “Pri. W”) of the voltage converter, and
the second switch unit (clamp circuit: 50, 52, 40, 72, 76, 56, 54) is configured to switch on-off (CTRL includes 2nd control signal pwm2 for driving clamp circuit’s switch 50) between an auxiliary winding (34’s auxiliary winding “Aux. W”) of the voltage converter and a negative voltage level (primary-side ground),
the input winding (Pri W) being coupled with the auxiliary winding (Aux W),
the method comprising steps of
before controlling the first control signal (CTRL’s output pwm1 for driving 48) to conduct the input winding (Pri W),
controlling the second switch unit (CTRL’s output pwm2 for driving clamp circuit’s switch 50) to connect the auxiliary winding (Aux W) of the voltage converter with the negative voltage level in advance (a negative voltage for Aux W. generated from a series connected node of ’56, 54’, and is a “zero potential” for the drain-source voltage of 48 is “Vds” of Pri W), and
input winding (Pri W) be forced to generate a negative current (I52 is representation of a negative voltage; wherein, when the 50 is conducted, the Pri W is forced to generate I52 so that the direction of the current I52 is flowing different direction first, to release the energy of a parasitic capacitance of 48 towards 72; thus, this energy is recovered through the 72, and will be released again for use in the next working cycle) based on the coupling between the input winding (Pri W) and auxiliary winding (Aux W) to release the energy of parasitic capacitance in the first switch unit (parasitic capacitance of 48; Para 26), so as to further enable polarity inversion of the input winding (Pri W) until the first switch unit cross voltage (drain-source voltage “Vds” of 48) decays to an expected low switching potential then conducts the described input winding (Pri W), for achieving the zero-voltage switching.
Regarding claim 14, Jay teaches
wherein the releasing an energy of a parasitic capacitance in the first switch unit (parasitic capacitance of 48; Para 26) and conducts the input winding (Pri W) until the first switch unit cross voltage (drain-source voltage “Vds” of 48) decays (Fig. 5) to an expected low switching potential further comprises:
setting a first delay time (Fig. 5; i.e., one delay t1-3 vs. another delay t4-6) after the second switch unit conducts the auxiliary winding (Aux W) with the negative voltage level (the negative voltage for Aux W. generated from a series connected node of ’56, 54’, and is a “zero potential” for the drain-source voltage of 48 is “Vds” of Pri W) and before the first switch unit (CTRL’s output pwm1 for driving 48) conducts the input winding (Pri W),
wherein the first delay time is set (Fig. 5; i.e., one delay t1-3 vs. another delay t4-6)
according to a volume of the parasitic capacitance in the first electronic switch (parasitic capacitance of 48; Para 26), and
is controlled programmable
by a PWM controller (Fig. 1, 4; detail of CTRL) of the voltage converter.
Regarding claim 16, Jay teaches
wherein after the first switch unit conducts (CTRL’s output pwm1 for driving 48) the input winding (Pri W) and before the second switch unit is turned-off (CTRL’s output pwm2 for driving clamp circuit’s switch 50),
a second delay time is set (Fig. 5; i.e., one delay t1-3 vs. another delay t4-6)
for delaying a conduction time of the second switch unit (50 is delayed to be on)
to ensure that the first switch unit is completely conducted (48 is on/conducting)
before the second switch unit is turned-off (50=off).
Regarding claim 17, Jay teaches
wherein the releasing energy of parasitic capacitance in the first switch unit (parasitic capacitance of 48; Para 26) and conducting the input winding (Pri W) until the first switch unit-cross-voltage decays (drain-source voltage “Vds” of 48) to an expected low switching potential further comprises:
sensing the waveform signal on the auxiliary winding (sensed signal of Aux W is received at one input of 74) and controlling turn-on timing of the first switch unit (CTRL’s output pwm1 for driving 48)
according to the described waveform signal after the second switch unit conducts (Fig. 5; 50 is conducting) the auxiliary winding with the negative voltage level (a negative voltage for Aux W. generated from a series connected node of ’56, 54’, and is a “zero potential” for the drain-source voltage of 48 is “Vds” of Pri W).
Regarding claim 19. Jay teaches A voltage converter (flyback converter), comprising the novel zero-voltage switching control circuit according to claim 1.
10. Claims 1-2, 12, 17, 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yau et al. (“Yau”, US Pat 11018593).
Regarding independent claim 1, Yau teaches (Fig. 1-13; col. 4 L50-col. 8 L36) a novel zero-voltage switching control circuit, applied to a voltage converter,
the novel zero-voltage switching control circuit comprising a controller (anticipated, although not shown “ctrl”), a first switch unit (30), and a second switch unit (clamp circuit: 20, Dreg, C clamp),
the controller (ctrl) being in a signal connection with the first switch unit (30) and the second switch unit (clamp circuit) respectively;
wherein the controller (ctrl) is configured
to generate a first control signal (i.e., pwm1) to control the first switch unit (30) to switch on-off of an input winding (primary winding Np) of the voltage converter, and
to generate a second control signal (pwm2) to control the second switch unit (clamp circuit’s Saux) to switch on-off between an auxiliary winding (N1) of the voltage converter and a negative voltage level (primary-side ground),
the input winding (Np) being coupled with the auxiliary winding (N1);
wherein before the first control signal (pwm1) conducts the input winding (Np),
the auxiliary winding (N1) of the voltage converter is conducted with the negative voltage level in advance (i.e., negative voltage, corresponding to N1 is provided from a node between Dreg & Cclamp), and
the input winding (Np)be forced to generate a negative current (See, Fig. 3-13; current flow direction, based on Smain vs. Saux switching operation) based on the coupling between the input winding (Np) and the auxiliary winding (N1), to release the energy of a parasitic capacitance in the first switch unit (Cmain of the Smain in 30), so as to further forcing the input winding (Np) polarity to reverse until the first switch unit cross voltage (Vds of Smain in 30) decays to an expected low switching potential voltages, then to conduct the described input winding (Np).
Regarding claim 2, Yau teaches
wherein the second switch unit (clamp circuit) comprises a second electronic switch (Saux), a second diode (Dreg), and a second capacitor (Cclamp), and
the auxiliary winding (Na) is a single winding;
one end of the second electronic switch (Saux source/one end) and a negative electrode of the second diode (Dreg’s cathode) are electrically connected with one end of the auxiliary winding (N1’s one end coupled to Saux’s source/one end and Dreg’s cathode) respectively,
the other end of the auxiliary winding is connected to primary-side ground (N1’s other end connected to ground);
the other end of the second electronic switch (Saux’s drain/another end) is electrically connected with a positive electrode of the second diode (Dreg’s anode, vias Smain & N1) and one end of the second capacitor (Cclamp’s one end), and
the other end of the second capacitor is connected to primary-side ground (Cclamp’s other end connected to ground, via Smain),
wherein a node between the second diode (Dreg) and the second capacitor (Cclamp) is configured to generate the negative voltage level.
Regarding independent claim 12, Yau teaches (Fig. 1-13; col. 4 L50-col. 8 L36) a novel zero-voltage switching control method, applied to a voltage converter,
the voltage converter at least comprising a first switch unit (30) and a second switch unit (clamp circuit: 20, Dreg, C clamp),
wherein the first switch unit (30) is configured to switch on-off of an input winding (primary winding Np) of the voltage converter, and
the second switch unit (clamp circuit: 20, Dreg, C clamp) is configured to switch on-off (i.e., Saux) between an auxiliary winding (N1) of the voltage converter and a negative voltage level (primary-side ground),
the input winding (Np) being coupled with the auxiliary winding (N1),
the method comprising steps of
before controlling the first control signal to conduct (controlling 30) the input winding (Np),
controlling the second switch unit (clamp circuit: 20, Dreg, C clamp) to connect the auxiliary winding (N1) of the voltage converter with the negative voltage level in advance (i.e., negative voltage, corresponding to N1 is provided from a node between Dreg & Cclamp), and
input winding (Np) be forced to generate a negative current (See, Fig. 3-13; current flow direction, based on Smain vs. Saux switching operation) based on the coupling between the input winding (Np) and auxiliary winding (N1) to release the energy of parasitic capacitance in the first switch unit (Cmain of the Smain in 30), so as to further enable polarity inversion of the input winding (Np) until the first switch unit cross voltage (Vds of Smain in 30) decays to an expected low switching potential then conducts the described input winding (Np), for achieving the zero-voltage switching.
Regarding claim 17, Yau teaches
wherein the releasing energy of parasitic capacitance in the first switch unit (Cmain of the Smain in 30 and conducting the input winding (Np) until the first switch unit-cross-voltage (Vds of Smain in 30) decays to an expected low switching potential further comprises:
sensing the waveform signal on the auxiliary winding (See, Fig. 3-13; current flow direction, based on Smain vs. Saux switching operation, thus sensing & manipulation of N1 is being performed) and controlling turn-on timing of the first switch unit (controlling 30)
according to the described waveform signal (See, Fig. 3-13; current flow direction, based on Smain vs. Saux switching operation, thus sensing & manipulation of N1 is being performed)
after the second switch unit conducts (clamp circuit: 20, Dreg, C clamp) the auxiliary winding (N1)
with the negative voltage level (i.e., negative voltage, corresponding to N1 is provided from a node between Dreg & Cclamp).
Regarding claim 19. A voltage converter (flyback converter), comprising the novel zero-voltage switching control circuit according to claim 1.
Claim Rejections - 35 USC § 103
11. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
12. Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jay (US Pub 2008/0225558), in view of Gong et al. (“Gong” US Pub 2019/0149052).
Regarding claim 13, Jay teaches
wherein the controlling (CTRL’s output pwm2) the second switch unit (clamp circuit: 50, 52, 40, 72, 76, 56, 54) to conduct the auxiliary winding (Aux W) with the negative voltage level in advance (the negative voltage for Aux W. generated from a series connected node of ’56, 54’, and is a “zero potential” for the drain-source voltage of 48 is “Vds” of Pri W) further comprises:
controlling a timing when the second switch unit (CTRL’s output pwm2 for driving clamp circuit’s switch 50) conducts the auxiliary winding (Aux W) with the negative voltage level (the negative voltage for Aux W. generated from a series connected node of ’56, 54’, and is a “zero potential” for the drain-source voltage of 48 is “Vds” of Pri W)
using
a clock signal (i.e., pulsated drive signal) of the voltage converter (i.e., Fig. 4), and
an output signal (i.e., using 60’s output) provided by the output winding (34’s secondary side “Sec W” is output winding) of the voltage converter.
However, Jay fails to teach controlling a timing of the second switch is performed explicitly using a feedback signal.
However, Gong teaches (Fig. 3-7) controlling a timing of the second switch is performed explicitly using or according to a clock signal (for the drive signal, see Fig. 5) and a feedback signal (i.e., pin FB, which is based on the output winding’s provided output signal).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jay’s zero-voltage switching control circuit to control a timing of the second switch by explicitly using or according to a clock signal (for the drive signal) and a feedback signal (based on the output winding’s provided output signal), as disclosed by Gong, as doing so would have provided a steady load output, regardless of input variations, while preventing energy losses, thus providing a faster and overall improved efficient performance of the converter, as taught by Gong (abstract and Para 1-4).
13. Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jay (US Pub 2008/0225558), in view of Yan et al. (“Yan”, US Pat 10985665).
Regarding claim 18, Jay teaches
wherein the controlling turn-on timing of the first switch unit (CTRL’s output pwm1 for driving 48) according to the described waveform signal (Fig. 5) further comprises:
controlling the first switch unit (CTRL’s output pwm1 for driving 48) to conduct the input winding (Pri W) when the voltage of the described waveform level (sensed signal of Aux W is received at one input of 74) reaches the pre-set voltage threshold (Vref),
wherein the waveform signal is obtained by the auxiliary winding (sensed signal of Aux W is received at one input of 74) through the … with capacitor filtering, and
the timing of the first switch unit conducts the input winding (Pri W) is controlled by adjusting the corresponding RC time constant (i.e., 44, 54 connection).
However, Jay fails to teach the auxiliary winding’s waveform signal is obtained through the resistor divider.
However, Yan teaches (Fig. 2-3; col. 2 L46-col. 6 L36) the auxiliary winding’s waveform signal (Vx sense) is obtained through the resistor divider (R1-2; col. 3 L34- col. 4 L6).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jay’s zero-voltage switching control circuit to include the auxiliary winding’s waveform signal be obtained through the resistor divider (thus, operating as RC time constant when connected with the Jay’s capacitor filter), as disclosed by Yan, as doing so would have provided a much more scaled version of auxiliary winding waveform with reduced noise, and thus improving overall efficient performance of the control circuit operation while maintaining a steady output, as taught by Yan (abstract).
Allowable Subject Matter
14. Claims 3-6, 8-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 3, Jay teaches
wherein the second switch unit (clamp circuit: 50, 52, 40, 72, 76, 56, 54) comprises a second electronic switch (50), a second diode (56), and a second capacitor (54), and
the auxiliary winding (Aux. W) is a single winding;
one end of the second electronic switch (50’s one end) and the second diode (56’s cathode) are coupled with the auxiliary winding (Aux W’s one end coupled to 50’s one end and D2’s cathode; wherein Q2 & D2’s cathode is connected via a series connection of ‘L1, D3’) respectively, the other end of the auxiliary winding is connected to primary-side ground (Aux W’s other end connected to ground);
the other end of the second electronic switch (50’s other end) is coupled with the second diode (56’s anode) and one end of the second capacitor (54’s one end), and the other end of the second capacitor is connected to primary-side ground (54’s other end connected to ground), wherein a node between the second diode (56) and the second capacitor (54) is configured to generate the negative voltage level.
However, Jay fails to teach specific direct connection, “the auxiliary winding is a double winding comprising a coupled winding and a negative voltage winding; one end of the second electronic switch is electrically connected with one end of the coupled winding, the other end of the coupled winding is connected to primary-side ground; the other end of the second electronic switch is electrically connected with a positive electrode of the second diode (anode) and one end of the second capacitor, and the negative electrode of the second diode (cathode) is electrically connected with one end of the negative voltage winding, and the other end of the negative voltage winding is connected to primary-side ground, wherein a node between the second diode and the second capacitor is configured to generate the negative voltage level”, as claimed in claim 3.
Claims 4-6 are depending from claim 3.
Regarding claim 8, Jay fails to teach, “the second switch unit further comprises a current limiting inductor disposed between the second capacitor and the auxiliary winding, a second diode, and a third diode; a positive electrode of the second diode and a negative electrode of the third diode are electrically connected with the second capacitor, a negative electrode of the second diode is electrically connected with the auxiliary winding, and a positive electrode of the third diode is electrically connected with the auxiliary winding via the current limiting inductor, wherein the current limiting inductor is configured to limit an inrush current level passing through the second electronic switch”.
Regarding claim 9, Jay fails to teach, “the second switch unit comprises a second electronic switch, a second diode, a third diode, and a second capacitor, and the auxiliary winding is a double-winding comprising a coupled winding and a negative voltage winding; the negative electrode of the second diode is electrically connected with one end of the negative voltage winding, and the other end of the negative voltage winding is connected to primary-side ground; the positive electrode of the second diode and the negative electrode of the third diode are electrically connected with one end of the second capacitor, and the positive electrode of the third diode is electrically connected with one end of the coupled winding; the other end of the coupled winding is connected to primary-side ground, and the other end of the second capacitor is connected to primary-side ground via the second electronic switch, wherein the node between the second diode and the second capacitor is configured to generate the negative voltage level”.
Claims 10-11 are depending from claim 9.
15. Claims 15, 20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Regarding claim 15, cited prior art(s) fail to teach the controlling programmable by a PWM controller of the voltage converter “performing compensation adjustment for the first delay time according to the output load current level feedback”.
Regarding claim 20, cited prior art(s) fail to teach wherein the second switch unit further comprises “a drive resistor, a drive capacitor, and a current limiting resistor; a control end of the second electronic switch is electrically connected with one end of the drive resistor and the drive capacitor respectively, the other end of the drive resistor is electrically connected to the positive electrode of the second diode, and the other end of the drive capacitor is electrically connected with the controller via the current limiting resistor”.
Conclusion
16. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Regarding independent claims 1, 12, Hsiao et al. (“Hsiao”, US Pat 10135348) teaches a novel zero-voltage switching control circuit (“ZVS” control circuit), applied to a voltage converter (Fig. 3; 300 includes elements of Fig. 1-2; col. 7 L33-col. 10 L40. Additionally, 300 is used to achieve zero voltage switching for primary side switches, and zero current switching for secondary side rectifiers under a wide input voltage range under different load conditions; col. 4 L65-col. 5 L3, col. 6 L38-col. 7 L23),
the novel zero-voltage switching control circuit comprising a controller (205), a first switch unit (Q1-2), and a second switch unit (clamp: Q3, D3-4, Cf, Aux a-b),
the controller (205) being in a signal connection with the first switch unit (Q1-2) and the second switch unit (clamp: Q3, D3-4, Cf, Aux a-b) respectively;
wherein the controller (205) is configured
to generate a first control signal (215, 213) to control the first switch unit (Q1-2) to switch on-off of an input winding (primary winding P) of the voltage converter, and
to generate a second control signal (211) to control the second switch unit (clamp: Q3, D3-4, Cf, Aux a-b) to switch on-off between an auxiliary winding (Aux a-b) of the voltage converter and a negative voltage level (primary-side ground),
the input winding (P) being coupled with the auxiliary winding (Aux a-b);
wherein before the first control signal (215, 213) conducts the input winding (P),
the auxiliary winding (Aux a-b) of the voltage converter is conducted with the negative voltage level in advance, and
the input winding (P) be forced to generate a negative current (a negative voltage for Aux a-b, generated from a series connected node of ‘D3, CF’, and is a “zero potential” for cross voltage of P. In other words, when the Q3 is conducted, the P is forced to generate the negative current so that the direction of the current is flowing upward first (i.e., see Fig. 2a vs. Fig. 2b current direction), to release the energy, such as corresponding drain-to source voltages of Q1-2, using feedback loop-controlled operation; thus, this energy is recovered, and will be released again for use in the next working cycle. See, col. 4 L37-col. 5 L52 and col. 7 L63-col. 8 L46) based on the coupling between the input winding (P) and the auxiliary winding (Aux a-b), to release the energy of … the first switch unit (Q1-2), so as to further forcing the input winding (P) polarity to reverse until the first switch unit cross voltage (drain-to source voltages of Q1-2) decays to an expected low switching potential voltage, then to conduct the described input winding (P).
However, Hsiao fails to teach use of a parasitic capacitance in the first switch, when releasing the energy of the same switch.
However, Liu et al. (“Liu”, CN 209805680) teaches use of a parasitic capacitance in the first switch (Q1-2 includes respective parasitic capacitance(s) Cds1-2), when releasing the energy of the same switch.
However, it would not have been obvious to have modified Hsiao’s ZVS control circuit for the resonant forward voltage converter to include use of a parasitic capacitance in the first switch, when releasing the energy of the same switch, as disclosed by Liu, as two prior arts are concentrated in two different types of converters, such as forward vs. flyback converter.
17. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NUSRAT QUDDUS whose telephone number is (571)270-7921. The examiner can normally be reached M-Th 9am-4pm ET
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/NUSRAT QUDDUS/Examiner, Art Unit 2838
/SEAN KAYES/Supervisory Patent Examiner, Art Unit 2838