DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, and 8, are rejected under 35 U.S.C. 103 as being unpatentable over by WIPO Application Publication to Avrahami WO2006/028477A1 in view of the US Patent Wessels 6,605,151US
In terms of Claim 1, Avrahami teaches a method comprising: depositing a magnesium oxide (MgO) seed layer (Figure 4c: layer 180 functions as a seed layer to grow layer 140 above of it; wherein 180 is made of MgO materials [Page 10, lines 5-10]) directly on an amorphous insulating cladding layer (Figure 4c: the insulator layer 120 is amorphous material (Page 12, lines 5-10).
In this example MgO layer 180 is “directly on 120” as shown in Figure 4c-d). This specification indicates this intervening layer 130 between 180 and 120 can be removed via a thinning process as indicated below:
In an embodiment, prior to the formation of the electro-optical layer 140, crystalline semiconductor layer 130 may be thinned to the desired thickness t.sub.2 (generally less than 100 nm) if, for example, a conventional SOI wafer is employed. The thickness of the crystalline semiconductor layer may be controlled to be no greater than 100 nm. For example, if the starting SOI wafer has a semiconductor top layer (e.g., crystalline semiconductor layer 130) with an initial thickness of greater than ~100 nm, the crystalline semiconductor layer 130 may be thinned by, e.g., oxidation, before or after the deposition of overlying layers, or by, e.g., polishing or etching before the deposition of overlying layers. Furthermore, thinning may involve a multi- step process beginning, for example, with oxidation followed by a chemical etch and, optionally, a dry etch, as is well-known in the art. Oxidation may be partial, i.e., so that a residual thin crystalline semiconductor layer 130 exists at the end of the fabrication process, or complete, i.e. so that the crystalline semiconductor layer 130 is essentially gone at the end of the process. In any event, complete oxidation may not take place before the deposition of the overlaying layer has started. Oxidation may be initiated by diffusion of oxygen from the atmosphere through the layers deposited over the SOI structure, either after the buffer layer growth or after the electro- optical layer growth. The oxidation step
may be performed even if the semiconductor top layer is less than 100 nm thick (Page 11, lines 1-40).
Referring to Figure 4C, the crystalline semiconductor layer 130 may be completely oxidized, resulting in a thicker insulator layer in direct contact with first buffer layer 180. Referring to Figure 4D, ridge 150 may be defined either from or over the electro-optical layer 140 (Page 12; lines 1-10).
In the disclosure above the thinning process of 130 can be done before the “deposition step of the overlying layer”. In Figure 4a: the layer 180 is overlying layer 130 which qualifies it to be an overlying layer; therefore, layer 130 can be removed before deposition 180 onto 130. Further, the statement of “In any event, complete oxidation may not take place before the deposition of the overlaying layer has started” does not preclude the possibility of some location of 130 has been thinned out to 120 and exposing 120, before the deposition of 180. In this example 180 will be directly on 120. Alternatively, another thinning out process can be executed before the deposition of 180 onto 130 via “polishing or etching before the deposition of overlying layers”. This means the oxidation step can be avoided altogether to produce an MgO layer that is in direct contact with 120 as indicated Figure 4c and (Page 12; lines 1-10). A second example is also disclosed wherein the layer 180 maybe be made of two layers 180 and 190 both made of MgO materials (Page 9, lines 20-35 and Page 11, lines 1-40), formed via PVD (Page 9, lines 20-35). In this example the topmost layer of MgO is the seed layer while the second MgO layer functions as an insulating (oxide material) cladding layer to waveguide layer 140.
The combined layers of 130/120 form a SOI layer which may function to limit loss or decouple light which is the functionality of a cladding layer [Page 6, lines 25-35 and Page 7, lines 30-34]). Further, Avrahami discloses materials that layer 120 can be used as cladding materials include SiO2 [Page 9, lines 20-25] hence the SOI can function has a bottom cladding layer via the layer 120 wherein layer 120 may also be amorphous [Page 16: see claim 22]) by a physical vapor deposition (PVD or physical vapor deposition [Page 5, lines 1-10]) process; and depositing a crystalline electro-optic layer (Figure 6c: 140 and Page 7, lines 20-25) directly on the crystalline MgO seed layer (Figure 6c: 140 and 180).
Avrahami does not teach wherein the MgO layer has a crystalline structure.
Wessels does teach wherein a MgO layer used in electro-optic modulator has a single crystalline structure (Column 3, lines 25-40). It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify the device of Avrahami to have crystalline MgO layer in order to provide thermos stability in semiconductor devices such as optical modulators (Column 3, lines 25-40).
As for claim 2, Avrahami / Wessels teaches the method of claim 1, wherein Avrahami teaches the crystalline electro-optic layer (Figure 6c: 140 is crystalline [Page 7, lines 20-3]) is between 50 nanometers nm and 500 nm in thickness (Page 7, lines 10-15), the crystalline MgO (Figure 6c: 180 is MgO and MgO is a crystalline material) seed layer is between 1 nm and 20 nm in thickness (Page 9, lines 31-34), and the amorphous insulating cladding layer (120/130) is between 1um and 10 um (Figure 6c: 120 and 130 is 3.05 Um in thickness).
As for claim 3, Avrahami / Wessels teaches the method of claim 1, wherein Avrahami teaches the amorphous insulating cladding layer (layer 120 is amorphous and insulating [see claim 22]) comprises silicon oxide, silicon nitride, silicon oxynitride or tantalum oxide (Page 6, lines 10-20).
As for claim 4, Avrahami / Wessels teaches the method of claim 1, wherein Avrahami teaches the crystalline electro-optic layer comprises a ferroelectric waveguide layer (Figure 6c: 140 is the electro-optic layer; wherein the electro-optic layer is made of BaTiO3 which is well known ferroelectric material). The examiner would also like to note that BaTiO3 is also the same material used as the electro-optic material (applicant’s specification [0039-0040]).
As for claim 6, Avrahami / Wessels teaches the method of claim 1, wherein Avrahami teaches the crystalline electro-optic layer comprises one of: strontium titanate (STO); barium strontium titanate (BST);hafnium oxide; lithium niobate (LiNbo3); zirconium oxide; titanium oxide; graphene oxide; tantalum oxide; lead zirconium titanate (PZT or PbZrTiO3); lead lanthanum zirconium titanate (PLZT or PbLaZrTiO3 );strontium barium niobate (SBN); or aluminum oxide (Page 7, lines 5-15 wherein the bolded materials and formula are disclosed by Avrahami of EO layer 140).
As for claim 8, Avrahami / Wessels teaches the method of claim 1, wherein Avrahami teaches comprising: etching the electro-optic layer (Figure 6c: 140) to produce a ridge structure (Figure 6c: 150); and depositing an additional insulating cladding layer on the etched electro- optic layer (Figure 1H: 170).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Avrahami WO2006/028477A1 / Wessels 6,605,151US as applied to claim 4 above, and further in view of US Patent Application Publication to Weiss 2004/0232406US.
In regard to Claim 5, Avrahami teaches the method of claim 4, wherein the electro-optic layer comprises of BTO (Page 7, lines 5-15 which teaches layer 140 maybe BaTiO3) wherein the layer 140 contains a portion 150 that may be formed through electron beam deposition (Page 8, lines 15-25).
Avrahami does not teach wherein the MgO layer is formed using electron beam or ion beam deposition.
Weiss does teach a method of making optical components wherein layers of MgO can be made through the use of electron beam deposition ([0082]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of deposition of the MgO layer to use electron beam deposition because electron beam deposition is a well-known process that has high precision accuracy for manufacturing of oxides layers.
Claims 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Avrahami WO2006/028477A1 / Wessels 6,605,151US as applied to claim 1 above, and further in view of US Patent to Teng 10,197,731US.
In regard to claims 7 and 9, Avrahami teaches the method of claim 1, wherein the device has a top and bottom cladding layers (120 and 170).
Avrahami / Wessels do not teach wherein the method further comprising forming a first waveguide embedded within the cladding layer; and a second waveguide embedded within the additional cladding layer.
Teng does teach wherein a method further comprising forming a first waveguide embedded within the cladding layer; and a second waveguide embedded within the additional cladding layer (See Figure 2a and 2b wherein a plurality of cores are embedded into vertical layers to allow the device to have multiple transmission channels (Column 5, lines 30-67). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Avrahami to include core layers within the cladding layers of 120 and 170. This allows the device to have multiple waveguide channels within one semiconductor package. The device can be used for input and output scaling purposes wherein more input/outputs are required on one package.
Claim 10-16, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Avrahami WO2006/028477A1 / Wessels 6,605,151US as applied to claim 4 above, and further in view of Japanese Patent to 中村 善貞 (JP4958331B2).
In terms of Claims 10-11 and 20, Avrahami teaches a method and device, comprising a magnesium oxide (MgO) seed layer (Figure 4c: layer 180 functions as a seed layer to grow layer 140 above of it; wherein 180 is made of MgO materials [Page 10, lines 5-10]) located directly on an amorphous insulating cladding layer (Figure 4c: the insulator layer 120 is amorphous material (Page 12, lines 5-10).
In this example MgO layer 180 is “directly on 120” as shown in Figure 4c-d). This specification indicates this intervening layer 130 between 180 and 120 can be removed via a thinning process as indicated below:
In an embodiment, prior to the formation of the electro-optical layer 140, crystalline semiconductor layer 130 may be thinned to the desired thickness t.sub.2 (generally less than 100 nm) if, for example, a conventional SOI wafer is employed. The thickness of the crystalline semiconductor layer may be controlled to be no greater than 100 nm. For example, if the starting SOI wafer has a semiconductor top layer (e.g., crystalline semiconductor layer 130) with an initial thickness of greater than ~100 nm, the crystalline semiconductor layer 130 may be thinned by, e.g., oxidation, before or after the deposition of overlying layers, or by, e.g., polishing or etching before the deposition of overlying layers. Furthermore, thinning may involve a multi- step process beginning, for example, with oxidation followed by a chemical etch and, optionally, a dry etch, as is well-known in the art. Oxidation may be partial, i.e., so that a residual thin crystalline semiconductor layer 130 exists at the end of the fabrication process, or complete, i.e. so that the crystalline semiconductor layer 130 is essentially gone at the end of the process. In any event, complete oxidation may not take place before the deposition of the overlaying layer has started. Oxidation may be initiated by diffusion of oxygen from the atmosphere through the layers deposited over the SOI structure, either after the buffer layer growth or after the electro- optical layer growth. The oxidation step
may be performed even if the semiconductor top layer is less than 100 nm thick (Page 11, lines 1-40).
Referring to Figure 4C, the crystalline semiconductor layer 130 may be completely oxidized, resulting in a thicker insulator layer in direct contact with first buffer layer 180. Referring to Figure 4D, ridge 150 may be defined either from or over the electro-optical layer 140 (Page 12; lines 1-10).
In the disclosure above the thinning process of 130 can be done before the “deposition step of the overlying layer”. In Figure 4a: the layer 180 is overlying layer 130 which qualifies it to be an overlying layer; therefore, layer 130 can be removed before deposition 180 onto 130. Further, the statement of “In any event, complete oxidation may not take place before the deposition of the overlaying layer has started” does not preclude the possibility of some location of 130 has been thinned out to 120 and exposing 120, before the deposition of 180. In this example 180 will be directly on 120. Alternatively, another thinning out process can be executed before the deposition of 180 onto 130 via “polishing or etching before the deposition of overlying layers”. This means the oxidation step can be avoided altogether to produce an MgO layer that is in direct contact with 120 as indicated Figure 4c and (Page 12; lines 1-10). A second example is also disclosed wherein the layer 180 maybe be made of two layers 180 and 190 both made of MgO materials (Page 9, lines 20-35 and Page 11, lines 1-40), formed via PVD (Page 9, lines 20-35). In this example the topmost layer of MgO is the seed layer while the second MgO layer functions as an insulating (oxide material) cladding layer to waveguide layer 140.
The combined layers of 130/120 form a SOI layer which may function to limit loss or decouple light which is the functionality of a cladding layer [Page 6, lines 25-35 and Page 7, lines 30-34]). Further, Avrahami discloses materials that layer 120 can be used as cladding materials include SiO2 [Page 9, lines 20-25] hence the SOI can function has a bottom cladding layer via the layer 120 wherein layer 120 may also be amorphous [Page 16: see claim 22]) by a physical vapor deposition (PVD or physical vapor deposition [Page 5, lines 1-10]) process; and depositing a crystalline electro-optic layer (Figure 6c: 140 and Page 7, lines 20-25) directly on the crystalline MgO seed layer (Figure 6c: 140 and 180).
Insulator layer may be made of silicon dioxide (Page 6, lines 20 of which is the same material used as the upper cladding layer 170 [Page 9, line 20]. Hence the examiner considers layer 120 capable of function as a cladding layer) by a physical vapor deposition (PVD or physical vapor deposition [Page 5, lines 1-10]) process; and a crystalline electro-optic layer (Figure 6c: 140 of which also performs modulating functions Page 1, lines 1-10) located directly on the MgO seed layer (Figure 6c: 140 and 180) via a second PVD process (the second PVD process is identified by the examiner has a product by process, wherein the process does not impart any additional structure from what is disclosed in the prior art, hence structurally speaking the disclosed structure still reads onto the device as claimed).
Avrahami does not teach wherein the MgO layer has a crystalline structure.
Wessels does teach wherein an MgO layer used in electro-optic modulator has a crystalline structure (Column 3, lines 25-40). It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify the device of Avrahami to have crystalline MgO layer in order to provide thermos stability in semiconductor devices such as optical modulators (Column 3, lines 25-40) wherein the electrode is in contact with the electro optic layer (Figure 1h: 160a-b and 140, conductive leads must be couple to the electrodes 160a-b in order to supply electrical current or voltage to the device).
Avrahami / Wessels do not teach wherein a doped or vacancy containing strontium titanium oxide (STO) forms the electrodes.
中村 善貞 does teach wherein a doped or vacancy containing strontium titanium oxide (STO – [0014]) forms the electrodes ([0015]) for the purpose increase electrical conductivity in semiconductor devices ([0015]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the materials of the electrodes of Avrahami to be made from doped STO in order to increase the electrical conductivity of the semiconductor device ([0015]) which allows the device to be more efficient.
As for Claim 12, Avrahami / Wessels / 中村 善貞 teaches the device of claim 11, wherein Avrahami teaches the crystalline electro-optic layer (Figure 6c: 140 is crystalline [Page 7, lines 20-3]) is between 50 nanometers nm and 500 nm in thickness (Page 7, lines 10-15), the MgO (Figure 6c: 180 is MgO and MgO) seed layer is between 1 nm and 20 nm in thickness (Page 9, lines 31-34), and the amorphous insulating cladding layer (120) is between 1um and 10 um (Figure 6c: 120 and 130 is 3.05 Um in thickness).
As for Claim 13, Avrahami / Wessels / 中村 善貞 teaches the device of claim 11, wherein Avrahami teaches the amorphous insulating cladding layer (layer 120 is amorphous and insulating [see claim 22]) comprises silicon oxide, silicon nitride, silicon oxynitride or tantalum oxide (Page 6, lines 10-20).
As for Claim 14, Avrahami / Wessels / 中村 善貞 teaches the device of claim 11, wherein Avrahami teaches the crystalline electro-optic layer comprises a ferroelectric waveguide layer (Figure 6c: 140 is the electro-optic layer; wherein the electro-optic layer is made of BaTiO3 which is well known ferroelectric material). The examiner would also like to note that BaTiO3 is also the same material used as the electro-optic material (applicant’s specification [0039-0040]).
As for Claim 15, Avrahami / Wessels / 中村 善貞 teaches the device of claim 14, wherein Avrahami teaches the crystalline EO layer comprises barium titanate (BTO, Page 7, lines 5-15: which teaches the material BaTiO3 which is BTO).
As for Claim 16, Avrahami / Wessels / 中村 善貞 teaches the device of claim 11, wherein Avrahami teaches the crystalline electro-optic layer comprises one of: strontium titanate (STO); barium strontium titanate (BST);hafnium oxide; lithium niobate (LiNbo3); zirconium oxide; titanium oxide; graphene oxide; tantalum oxide; lead zirconium titanate (PZT or PbZrTiO3); lead lanthanum zirconium titanate (PLZT or PbLaZrTiO3 );strontium barium niobate (SBN); or aluminum oxide (Page 7, lines 5-15 wherein the bolded materials and formula are disclosed by Avrahami of EO layer 140).
As for Claim 18, Avrahami / Wessels / 中村 善貞 teaches the device of claim 11, wherein Avrahami teaches: a ridge structure (Figure 6c: 150) located in the electro optic layer (Figure 1H: 150 and 140); and an additional insulating cladding layer on the etched electro- optic layer (Figure 1H: 170).
Claims 17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Avrahami WO2006/028477A1 / Wessels 6,605,151US / 中村 善貞 JP4958331B2 as applied to claim 11 above, and further in view of US Patent to Teng 10,197,731US.
In regard to claims 17, and 19, Avrahami / Wessels / 中村 善貞 teaches the device of claim 11, wherein the device has a top and bottom cladding layers (120 and 170).
Avrahami / Wessels do not teach wherein the method further comprising forming a first waveguide embedded within the cladding layer; and a second waveguide embedded within the additional cladding layer.
Teng does teach wherein a method further comprising forming a first waveguide embedded within the cladding layer; and a second waveguide embedded within the additional cladding layer (See Figure 2a and 2b wherein a plurality of cores are embedded into vertical layers to allow the device to have multiple transmission channels (Column 5, lines 30-67). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Avrahami to include core layers within the cladding layers of 120 and 170. This allows the device to have multiple waveguide channels within one semiconductor package. The device can be used for input and output scaling purposes wherein more input/outputs are required on one package.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Avrahami WO2006/028477A1 / Wessels 6,605,151US as applied to claim 1 above, and further in view of US Patent to Abe 7,262,485US.
In regard to Claim 21, Avrahami / Wessels teaches the method of Claim 1.
Avrahami / Wessels do not teach wherein the MgO layer has a single crystalline structure.
Abe does teach wherein an optical device having electro-optical functions wherein buffered MgO layer is made from a single crystalline structure (Column 1, lines 55-60) to improve the quality (Abe’s Column 1, lines 30-37) of the device by alleviating lattice mismatch between BTO layer and Si layers (Abe’s Column 1, lines 35-45). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the MgO layer to have single crystalline structure in order to improve the quality of the device by reducing the effects of lattice mismatch between the BTO layer and the Si base layer.
Response to Arguments
Applicant's arguments filed 6/24/2026 have been fully considered but they are not persuasive. In this instant the applicant argues Figure 4c does not teach the method steps of “depositing a crystalline MgO seed layer directly on an amorphous insulating cladding layer” because the cited MgO layer (Figure 4c: 180 is shown to be deposited on top of intervening layer 130 which is not an insulating or a cladding layer). An additional step is used thin out layer 130 to remove it so the resulting structure in Figure 4c: wherein MgO layer 180 is shown to be on top of cladding and insulating layer 120. Since the depositing steps requires “MgO seed layer directly on an amorphous insulating cladding layer”, thus having layer 130 in-between 180 and 120 during the depositing step does not meet the limitation as claimed (Remarks Page 7). The applicant further stated in the disclosure of Avrahami, wherein the thinning out step via oxidation requires so residual amounts of 130 to be present thus not meeting “directly” orientation between the MgO layer and the cladding insulating layer as claimed.
The examiner respectfully disagreed because of the following reasons:
In this example MgO layer 180 is “directly on 120” as shown in Figure 4c-d). This specification indicates the intervening layer 130 between 180 and 120 can be removed via two thinning processes as indicated below:
In an embodiment, prior to the formation of the electro-optical layer 140, crystalline semiconductor layer 130 may be thinned to the desired thickness t.sub.2 (generally less than 100 nm) if, for example, a conventional SOI wafer is employed. The thickness of the crystalline semiconductor layer may be controlled to be no greater than 100 nm. For example, if the starting SOI wafer has a semiconductor top layer (e.g., crystalline semiconductor layer 130) with an initial thickness of greater than ~100 nm, the crystalline semiconductor layer 130 may be thinned by, e.g., oxidation, before or after the deposition of overlying layers, or by, e.g., polishing or etching before the deposition of overlying layers. Furthermore, thinning may involve a multi- step process beginning, for example, with oxidation followed by a chemical etch and, optionally, a dry etch, as is well-known in the art. Oxidation may be partial, i.e., so that a residual thin crystalline semiconductor layer 130 exists at the end of the fabrication process, or complete, i.e. so that the crystalline semiconductor layer 130 is essentially gone at the end of the process. In any event, complete oxidation may not take place before the deposition of the overlaying layer has started. Oxidation may be initiated by diffusion of oxygen from the atmosphere through the layers deposited over the SOI structure, either after the buffer layer growth or after the electro- optical layer growth. The oxidation step
may be performed even if the semiconductor top layer is less than 100 nm thick (Page 11, lines 1-40).
Referring to Figure 4C, the crystalline semiconductor layer 130 may be completely oxidized, resulting in a thicker insulator layer in direct contact with first buffer layer 180. Referring to Figure 4D, ridge 150 may be defined either from or over the electro-optical layer 140 (Page 12; lines 1-10).
In the disclosure above the thinning process of oxidation can be performed on layer 130 before the “deposition step of the overlying layer”. In Figure 4a: the layer 180 is an overlying layer relative to 130. Layer 130 can be removed before deposition 180 onto 130. The applicant has relied on this statement from above “In any event, complete oxidation may not take place before the deposition of the overlaying layer has started” to provide support to the applicant’s position, that layer 180 can’t be “directly on” 120 because oxidation can’t be completed as stated by Avrahami. However, the examiner doesn’t find this position persuasive because Avrahami only mentions about the relationship of “complete oxidation” relative to deposition of overlying layers. It is entirely possible for layer 130 to have uncompleted oxidation (i.e. a residual portion 130 be left on 120 in some location) while other location may have deposition 180 “directly on” because the area layer 130 has been removed to the surface of 120 as shown in Figure 4c. The applicant appears to imply that the oxidation process must be applied in a uniformed manner across the entire surface of 130 at the same time, hence 130 will always be present until the oxidation is fully completed. However, this meaning is not explicitly mentioned in the disclosure above.
The applicant cited indicated Avrahami teaches that some portion of 130 will always be present and located in between the MgO layer and the insulating cladding layer due to un-completed oxidation removal thinning process, thus not meeting the limitation of Claim 1. However, another thinning out process can be executed before the deposition of 180 onto 130 via “polishing or etching before the deposition of overlying layers”. This means the oxidation step can be avoided altogether to produce an MgO layer that is in direct contact with 120 as indicated Figure 4c and (Page 12; lines 1-10). Since oxidation thinning out process can be avoided altogether renders the applicant’s position relating to the oxidation process mot.
Lastly, A second example is also disclosed wherein the layer 180 maybe be made of two layers 180 and 190 both made of MgO materials (Page 9, lines 20-35 and Page 11, lines 1-40), formed via PVD (Page 9, lines 20-35).
Base on the 3 reason(s) detailed above, the examiner still considers the prior of Avrahami to read on to the limitations of “MgO seed layer directly on an amorphous insulating cladding layer” as recited in claim 1.
In regards to Claim 11, the applicant argued the prior art of Japanese Patent to 中村 善貞 / Nakamura (JP4958331B2) does not teach electrodes having doped or vacancy containing sto as claimed.
The examiner respectfully disagrees, because 中村 善貞 / Nakamura teaches:
In the photosensitive layer, the semiconductor acts as a photoconductor, absorbs light, separates charges, and generates electrons and holes. In a dye-sensitized semiconductor, light absorption and the generation of electrons and holes thereby occur mainly in the dye, and the semiconductor particles play a role of receiving and transmitting these electrons (or holes). The semiconductor used in the present invention is preferably an n-type semiconductor in which conductor electrons become carriers under photoexcitation and give an anode current.
[0014] Preferred metal chalcogenides include titanium, tin, zinc, iron, tungsten, zirconium, hafnium, strontium, indium, cerium, yttrium, lanthanum, vanadium, niobium, or tantalum oxide, cadmium, zinc, lead, silver, antimony or Bismuth sulfide, cadmium or lead selenide, cadmium telluride and the like. Examples of other compound semiconductors include phosphides such as zinc, gallium, indium, and cadmium, gallium-arsenic or copper-indium selenides, and copper-indium sulfides. Furthermore, MxOySz or M.sub.1xM.sub.2yOz (M, M.sub.1And M.sub.2A composite element such as each of which is a metal element, O is oxygen, and x, y, and z are combinations of which the valence is neutral) can also be preferably used.
[0015] Preferred specific examples of the semiconductor used in the present invention include Si and TiO..sub.2, SnO.sub.2, Fe.sub.2O.sub.Three, WO.sub.Three, ZnO, Nb.sub.2O.sub.Five, CdS, ZnS, PbS, Bi.sub.2S.sub.Three, CdSe, CdTe, SrTiO.sub.Three, GaP, InP, GaAs, CuInS.sub.2, CuInSe.sub.2And more preferably TiO.sub.2, ZnO, SnO.sub.2, Fe.sub.2O.sub.Three, WO.sub.Three, Nb.sub.2O.sub.Five, CdS, PbS, CdSe, SrTiO.sub.Three (STO material), InP, GaAs, CuInS.sub.2Or CuInSe.sub.2And particularly preferably TiO.sub.2Or Nb.sub.2O.sub.FiveAnd most preferably TiO.sub.2It is. TiO.sub.2TiO containing 70% or more of anatase type crystals.sub.2And particularly preferably 100% anatase type TiO.sub.2It is. It is also effective to dope metals for the purpose of increasing the electronic conductivity in these semiconductors. As the metal to be doped, divalent and trivalent metals are preferable. In order to prevent reverse current from flowing from the semiconductor to the charge transport layer, it is also effective to dope the semiconductor with a monovalent metal.
The material STO material above is a metal, having electrically conductive properties, is able to carry current and be used as an anode. The examiner considers the material above to qualify because it is metal having conductive properties and can transport current. Lastly, the material strontium SrTiO3 disclosed by 中村 善貞 / Nakamura (JP4958331B2) is also the same electrode material as indicated by the applicant to correspond to the claimed electrode (claim 10 of the current application).
Newly added claim 21 was rejected in view of newly cited prior art as detailed above.
This action is therefore made FINAL for the reason(s) detailed above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOANG Q TRAN whose telephone number is (571)272-5049. The examiner can normally be reached 9:30 am - 5:30pm Monday - Friday.
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/HOANG Q TRAN/ Examiner, Art Unit 2874
/UYEN CHAU N LE/ Supervisory Patent Examiner, Art Unit 2874
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