DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
Response filed on 22 August 2025 has been entered. Applicant has canceled claim 16, amended claims 1, 5, and 10, and added claims 20-21. Claims 1-15 and 17-21 are pending.
Response to Arguments
Applicant’s arguments with respect to the rejection(s) of claim(s) 1 under 35 USC § 103 have been fully considered and are persuasive. Applicant asserts that element 112 is not formed in the region corresponding to the floating diffusion region. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of an alternative interpretation of the Masagaki reference.
Applicant asserts that element 111 could not provide a pixel separation region in an area excluding a region corresponding to the floating diffusion region and that a portion of the penetrating pixel separation region is not in contact with the non-penetrating pixel region. However, element 111 shown (fig. 3-4) along the C-C’ presents 111 as non-penetrating above floating diffusion area 72 in the center of the four-pixel group while another section of 111, as seen along A-A’ or B-B’, is penetrating pixel separation layer by connecting 111B to 111A between two adjacent pixels, which therefore discloses a penetrating pixel separation region except for in the floating diffusion region where 111A is absent. Further, a portion of 111 that is penetrating away from region 72 is contacting the non-penetrating portion (Masagaki ¶97).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-15, 17, and 20-21 rejected under 35 U.S.C. 103 as being unpatentable over Masagaki et al. US PGPUB 20180350856 (hereinafter Masagaki) in view of Nakajiki et al. US PGPUB 20190206917 (hereinafter Nakajiki).
It would have been obvious to one of ordinary skill in the art at the time of filing to
Regarding claim 1, Masagaki discloses (figs. 1-6) a solid-state imaging element comprising:
a semiconductor layer in which pixels (71 ¶70-80) that receive light and perform photoelectric conversion (PD 91 ¶74) are two-dimensionally arranged (¶73, where "Each pixel group 70 includes 2×2 pixels 71-1 to 71-4, an FD 72, a reset transistor 73, an amplification transistor 74, a selection transistor 75, a power supply electrode 76, and a well electrode 77");
a floating diffusion (FD 72, ¶73) region provided in the semiconductor layer and shared by the visible-light pixel and the infrared-light pixel adjacent to each other;
a penetrating pixel separation region (111, fig. 3-4 ¶90-91, where 111b connects to 111a) provided in a region excluding a region corresponding to the floating diffusion region in an inter-pixel region, the penetrating pixel separation region penetrating the semiconductor layer in a depth direction (fig. 4, where pixel separation from the backside, 111b contacts 111a except for in the center of the C-C’ section corresponding to the floating diffusion region 72); and
a non-penetrating pixel separation (111, fig. 3-4 ¶90-91, where 111 is not penetrating in the center of the C-C’ section corresponding to the floating diffusion region 72) region provided in the region corresponding to the floating diffusion region in the inter-pixel region, the non-penetrating pixel separation region reaching a midway part in the depth direction from a light receiving surface of the semiconductor layer (fig. 4, where 111b does not contact 111a in the center of the C-C’ section, resulting in 111 stopping midway in the depth direction),
wherein a portion of the penetrating pixel separation region is in contact with the non-penetrating pixel separation region (fig. 6A-B, where 111b is shown to be connecting the penetrating portion shown as 111a in fig. 6A to the non-penetrating portion in the floating diffusion region 72).
Masagaki discloses the CMOS device can be configured for visible and infrared light (¶330), but does not disclose the simultaneous arrangement of the pixels for both wavelength ranges. Therefore, Masagaki does not explicitly disclose a visible-light pixel that receives visible light and performs photoelectric conversion and an infrared-light pixel that receives infrared light.
In the same field of endeavor, Nakajiki discloses (Nakajiki fig. 4-5) a visible (51) and infrared (52) pixel (Nakajiki ¶112) two-dimensionally arranged (fig. 5). It would have been obvious to one of ordinary skill in the art at the time of filing to arrange both visible and infrared pixels as disclosed by Nakajiki, improving device performance by increasing the range of wavelengths detected.
Regarding claim 3, Masagaki and Nakajiki disclose the solid-state imaging element according to claim 1,
wherein the floating diffusion region (FD 72, Masagaki ¶73) is shared by four pixels adjacent in a matrix direction (Masagaki fig. 5).
Regarding claim 4, Masagaki and Nakajiki disclose the solid-state imaging element according to claim 1,
wherein the floating diffusion region (FD 72, Masagaki ¶73) is shared by two pixels adjacent to each other (path W1, Masagaki fig. 5 ¶105).
Regarding claim 5, Masagaki discloses (figs. 1-6) a solid-state imaging element comprising:
a semiconductor layer in which a pixels (71 ¶70-80) that receive light and perform photoelectric conversion (PD 91 ¶74) are two-dimensionally arranged (¶73, where "Each pixel group 70 includes 2×2 pixels 71-1 to 71-4, an FD 72, a reset transistor 73, an amplification transistor 74, a selection transistor 75, a power supply electrode 76, and a well electrode 77");
a pixel transistor (73, 74, or 75, ¶73, 81-86) provided in the semiconductor layer and shared by pixels adjacent to each other;
a penetrating pixel separation region (111, fig. 3-4 ¶90-91, where 111b connects to 111a) provided in a region excluding a region corresponding to the pixel transistor in an inter-pixel region of the visible-light pixel and the infrared-light pixel, the penetrating pixel separation region penetrating the semiconductor layer in a depth direction (fig. 4, where pixel separation from the backside, 111b contacts 111a except for in the center of the C-C’ section corresponding to the floating diffusion region 72); and
a non-penetrating pixel separation region (111, fig. 3-4 ¶90-91, where 111 is not penetrating in the center of the C-C’ section corresponding to the floating diffusion region 72) provided in the region corresponding to the pixel transistor in the inter-pixel region, the non-penetrating pixel separation region reaching a midway part in the depth direction from a light receiving surface of the semiconductor layer (fig. 4, where 111b does not contact 111a in the center of the C-C’ section, resulting in 111 stopping midway in the depth direction).
Masagaki discloses the CMOS device can be configured for visible and infrared light (¶330), but does not disclose the simultaneous arrangement of the pixels for both wavelength ranges. Therefore, Masagaki does not explicitly disclose a visible-light pixel that receives visible light and performs photoelectric conversion and an infrared-light pixel that receives infrared light.
In the same field of endeavor, Nakajiki discloses (Nakajiki fig. 4-5) a visible (51) and infrared (52) pixel (Nakajiki ¶112) two-dimensionally arranged (fig. 5). It would have been obvious to one of ordinary skill in the art at the time of filing to arrange both visible and infrared pixels as disclosed by Nakajiki, improving device performance by increasing the range of wavelengths detected.
Regarding claim 6, Masagaki and Nakajiki disclose the solid-state imaging element according to claim 5,
wherein the penetrating pixel separation region (111, fig. 3-4 ¶90-91, where 111b connects to 111a) is extended between the pixel transistor (73, 74, or 75, Masagaki ¶73, 81-86) shared by the visible-light pixel and the infrared-light pixel and a pixel transistor shared by the visible-light pixel and the infrared-light pixel adjacent to the visible-light pixel and the infrared-light pixel (Masagaki fig. 5, where pixels can be paired as 71-1/71-2 and 71-3/71-4 with each pair having a visible-light pixel and an infrared-light pixel as modified by Nakajiki).
Regarding claim 7, Masagaki and Nakajiki disclose the solid-state imaging element according to claim 5,
wherein the non-penetrating pixel separation region (111, fig. 3-4 ¶90-91, where 111 is not penetrating in the center of the C-C’ section corresponding to the floating diffusion region 72) extends between the pixel transistor (73, 74, or 75, Masagaki ¶73, 81-86) shared by the visible-light pixel and the infrared-light pixel and a pixel transistor shared by the visible-light pixel and the infrared-light pixel adjacent to the visible-light pixel and the infrared-light pixel (Masagaki fig 6).
Regarding claim 8, Masagaki and Nakajiki disclose the solid-state imaging element according to claim 5,
wherein the pixel transistor (73, 74, or 75, Masagaki ¶73, 81-86) is shared by four pixels adjacent in a matrix direction (Masagaki fig 6).
Regarding claim 9, Masagaki and Nakajiki disclose the solid-state imaging element according to claim 5,
wherein the pixel transistor (73, 74, or 75, Masagaki ¶73, 81-86) is shared by two pixels adjacent to each other (Masagaki fig. 5).
Regarding claim 10. Masagaki discloses (figs. 1-6) a solid-state imaging element comprising:
a semiconductor layer in which pixels (71 ¶70-80) that receive light and perform photoelectric conversion (PD 91 ¶74) are two-dimensionally arranged (¶73, where "Each pixel group 70 includes 2×2 pixels 71-1 to 71-4, an FD 72, a reset transistor 73, an amplification transistor 74, a selection transistor 75, a power supply electrode 76, and a well electrode 77");
a well contact (118, ¶93-94) provided in the semiconductor layer and shared by pixels adjacent to each other (fig. 6);
a penetrating pixel separation region (111, fig. 3-4 ¶90-91, where 111b connects to 111a) provided in a region excluding a region corresponding to the well contact (118) in an inter-pixel region, the penetrating pixel separation region penetrating the semiconductor layer in a depth direction (fig. 4, where pixel separation from the backside, 111b contacts 111a except for in the center of the C-C’ section corresponding to the floating diffusion region 72); and
a non-penetrating pixel separation region (111, fig. 3-4 ¶90-91, where 111 is not penetrating in the center of the C-C’ section corresponding to the floating diffusion region 72) provided in the region corresponding to the well contact in the inter-pixel region, the non-penetrating pixel separation region reaching a midway part in the depth direction from a light receiving surface of the semiconductor layer (fig. 4, where 111b does not contact 111a in the center of the C-C’ section, resulting in 111 stopping midway in the depth direction),
wherein a portion of the penetrating pixel separation region is in contact with the non-penetrating pixel separation region(fig. 6A-B, where 111b is shown to be connecting the penetrating portion shown as 111a in fig. 6A to the non-penetrating portion in the floating diffusion region 72).
Masagaki discloses the CMOS device can be configured for visible and infrared light (¶330), but does not disclose the simultaneous arrangement of the pixels for both wavelength ranges. Therefore, Masagaki does not explicitly disclose a visible-light pixel that receives visible light and performs photoelectric conversion and an infrared-light pixel that receives infrared light.
In the same field of endeavor, Nakajiki discloses (Nakajiki fig. 4-5) a visible (51) and infrared (52) pixel (Nakajiki ¶112) two-dimensionally arranged (fig. 5). It would have been obvious to one of ordinary skill in the art at the time of filing to arrange both visible and infrared pixels as disclosed by Nakajiki, improving device performance by increasing the range of wavelengths detected.
Regarding claim 11, Masagaki and Nakajiki disclose the solid-state imaging element according to claim 10,
wherein the non-penetrating pixel separation region (111, fig. 3-4 ¶90-91, where 111 is not penetrating in the center of the C-C’ section corresponding to the floating diffusion region 72) reaches, from the light receiving surface of the semiconductor layer, an impurity diffusion region (101, Masagaki ¶89-92) connected to the well contact (118, Masagaki ¶93-94) in the semiconductor layer.
Regarding claim 12, Masagaki and Nakajiki disclose the solid-state imaging element according to claim 10,
wherein the well contact (118, Masagaki ¶93-94) is shared by four pixels adjacent in a matrix direction (Masagaki fig. 6).
Regarding claim 13, Masagaki and Nakajiki disclose the solid-state imaging element according to claim 10,
wherein the well contact (118, Masagaki ¶93-94) is shared by two pixels adjacent to each other (Masagaki fig. 6).
Regarding claim 14, Masagaki and Nakajiki disclose the solid-state imaging element according to claim 1,
wherein the penetrating pixel separation region (113, Masagaki ¶90-92) includes:
a trench part (113B, Masagaki ¶97, 99) that extends from the light receiving surface toward a surface opposed to the light receiving surface of the semiconductor layer, and
an element isolation structure (113A, Masagaki ¶97, 99) that extends from the surface opposed to the light receiving surface toward the light receiving surface, and is in contact with the trench part (Masagaki fig. 5).
Regarding claim 15, Masagaki and Nakajiki disclose the solid-state imaging element according to claim 1.
Masagaki discloses (figs. 30-31) wherein the non-penetrating pixel separation region (311B, Masagaki ¶255, 257) is in contact with the penetrating pixel separation region (311B and 311A not overlapping 192, Masagaki fig. 30A-B ¶255, 257). It would have been obvious to one of ordinary skill in the art at the time of filing to use the alternate embodiment disclosed by Masagaki, improving performance by suppressing “degradation of imaging characteristics due to leakage of charges from the PD 291 to the reset transistor 193, the amplification transistor 194, the selection transistor 195, the power supply electrode 197, or the well electrode 198” (Masagaki ¶263).
Regarding claim 17, Masagaki and Nakajiki disclose the solid-state imaging element according to claim 1.
Masagaki and Nakajiki are silent regarding wherein the visible-light pixel and the infrared-light pixel have a shortest distance of 2.2 microns or less between sides facing each other in a plan view.
MPEP §2144.05-II (A) states, "’[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.’ In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.).”
In the instant case, Masagaki discloses the general conditions of the claimed invention. Therefore, it would not be inventive to set the specific minimum distance between sides facing each other between respective pixels in a plan view to 2.2 microns or less.
It would have been obvious to one of ordinary skill in the art at the time of filing to optimize the lateral separation of adjacent pixels, reducing charge leakage between the adjacent pixels.
Regarding claim 20, Masagaki and Nakajiki disclose the solid-state imaging element according to claim 1,
wherein the portion of the penetrating pixel separation region in contact with the non-penetrating pixel separation region is in the inter-pixel region of the visible-light pixel and the infrared-light pixel (fig. 6A-B, where 111b is shown to be connecting the penetrating portion shown as 111a in fig. 6A to the non-penetrating portion in the floating diffusion region 72 and 112b is located in the inter-pixel regions).
Regarding claim 21, Masagaki and Nakajiki disclose the solid-state imaging element according to claim 5,
wherein the portion of the penetrating pixel separation region in contact with the non-penetrating pixel separation region is in the inter-pixel region of the visible-light pixel and the infrared-light pixel (fig. 6A-B, where 111b is shown to be connecting the penetrating portion shown as 111a in fig. 6A to the non-penetrating portion in the floating diffusion region 72 and 112b is located in the inter-pixel regions).
Claim 2 rejected under 35 U.S.C. 103 as being unpatentable over Masagaki and Nakajiki in view of Ikeda et al. US PGPUB 20170025455 (hereinafter Ikeda).
Regarding claim 2, Masagaki and Nakajiki disclose the solid-state imaging element according to claim 1.
Masagaki and Nakajiki do not disclose wherein the non-penetrating pixel separation region reaches the floating diffusion region from the light receiving surface of the semiconductor layer.
In the same field of endeavor, Ikeda discloses wherein the non-penetrating pixel separation region (insulting section 20, Ikeda fig. 4 ¶96-97) reaches the floating diffusion region (FD, Ikeda ¶96) from the light receiving surface of the semiconductor layer (Ikeda fig. 4). It would have been obvious to one of ordinary skill in the art at the time of filing for the non-penetrating pixel separation region to reach the floating diffusion region as disclosed by Ikeda, improving device performance by reducing noise and preventing unwanted signal coupling.
Claim 18 rejected under 35 U.S.C. 103 as being unpatentable over Masagaki and Nakajiki in view of Yanagita et al. US PGPUB 20140054662 (hereinafter Yanagita).
Regarding claim 18, Masagaki and Nakajiki disclose the solid-state imaging element according to claim 1.
Masagaki and Nakajiki do not disclose wherein a negative voltage is applied to the penetrating pixel separation region and the non-penetrating pixel separation region.
In the same field of endeavor, Yanagita discloses (fig. 2) wherein a negative voltage (Yanagita ¶68-70) is applied to the pixel separation region (19 and 20, Yanagita ¶67-70). It would have been obvious to one of ordinary skill in the art at the time of filing to apply the fixed charge of Yanagita to the solid-state imaging element disclosed by Masagaki and Nakajiki, improving efficiency of transfer of accumulated charges from the pixel.
Claim 19 rejected under 35 U.S.C. 103 as being unpatentable over Masagaki and Nakajiki in view of Lee et al. US PGPUB 20160043119 (hereinafter Lee).
Regarding claim 19, Masagaki and Nakajiki disclose the solid-state imaging element according to claim 1.
Masagaki and Nakajiki do not disclose wherein the non-penetrating pixel separation region is provided at a position dividing each of the visible-light pixel and the infrared-light pixel having a square planar shape into two regions having an equal light receiving area and a rectangular planar shape.
In the same field of endeavor, Lee discloses (figs. 2, 11) wherein the non-penetrating pixel separation region (D1, Lee ¶128) is provided at a position dividing each of the visible-light pixel and the infrared-light pixel (pixel 120-1A, 120-1B, 120-1C, or 120-D, Lee ¶52-53, equivalent to the cross-section view of pixel 400-5, Lee ¶127-129) having a square planar shape (fig. 2) into two regions having an equal light receiving area and a rectangular planar shape (fig. 11).
It would have been obvious to one of ordinary skill in the art at the time of filing to divide each pixel into two rectangular pixels as disclosed by Lee, improving timing resolution of the solid-state imaging element.
Conclusion
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/Seth D Lawson/ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893