DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Response to Amendments
Applicant's response of 08/13/2025 has been acknowledged. Claim 15 has been amended. No new matter has been added.
This office action considers claims 1-20 pending for prosecution and are examined on their merits.
Response to Arguments
Applicant’s arguments filed 08/13/2025 with respect to the rejection of claims 1-20 have been fully considered but are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all
obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 1-13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou et al. (US 20170220148 A1 – hereinafter Zhou) in view of Cho et al. (US 20210043134 A1 – hereinafter Cho).
Regarding independent claim 1, Zhou teaches
(Original) An array substrate ([0008] – “array substrate”), comprising a
first adjacent data line (34A – Fig. 7 – [0035] – “One of the two data lines having the projections in the same pixel gap K in the direction perpendicular to the pixel electrode layer is referred to as a first data line 34A and the other one is referred to as a second data line 34B”) and a second adjacent data line (34B – Fig. 7 – [0035] – “One of the two data lines having the projections in the same pixel gap K in the direction perpendicular to the pixel electrode layer is referred to as a first data line 34A and the other one is referred to as a second data line 34B”) extending along a first direction (Y – Fig. 7 – [0031] – “The array substrate further includes multiple data lines extending in a column direction Y of the array”);
wherein the first adjacent data line (34A) and the second adjacent data line (34B) extend from a same inter-column region (K – Fig. 7 – [0033] – “pixel gap K exists between adjacent columns of the pixel electrodes 31” – Fig. 7 shows this) between a first column of pixel driving circuit (Fig. 7 annotated, see below – hereinafter ‘C1’ – [0029] – “pixel electrode layer includes multiple pixel electrodes 31 arranged in an array” – these correspond to driving circuits) and a second column of pixel driving circuit (Fig. 7 annotated, see below – hereinafter ‘C2’ – these correspond to driving circuits) in a display area into a boundary area between the first column of pixel driving circuit and a peripheral area;
wherein, in the boundary area, the first adjacent data line and the second adjacent data line are in a same layer.
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Zhou does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Cho teaches
a display area (Fig. 3 annotated, see below – [0063] – “The pixel area PXA is a planar area where pixels PXL for displaying images are disposed (e.g., a display area)” – hereinafter ‘Display Area’) into a boundary area (Fig. 3 annotated, see below – [0007] – “a display device includes a substrate including a pixel area including a pixel; a peripheral area adjacent to the pixel area; and a boundary between the pixel area and the peripheral area” – hereinafter ‘Boundary Area’) between the first column of pixel driving circuit (Fig. 3 annotated, see below – [0072] – “The pixels PXL may be arranged in a matrix along rows extended along the first direction DR1 and columns extended along the second direction DR2” – hereinafter ‘C1’) and a peripheral area (Fig. 3 annotated, see below – [0007] – “a display device includes a substrate including a pixel area including a pixel; a peripheral area adjacent to the pixel area; and a boundary between the pixel area and the peripheral area” – hereinafter ‘Peripheral Area’);
wherein, in the boundary area (Boundary Area), the first adjacent data line ([0220] – “the plurality of first data lines Da” – this is interpreted as first data line Da-1) and the second adjacent data line ([0220] – “the plurality of first data lines Da” – this is interpreted as first data line Da-2) are in a same layer (Fig. 10 shows all Da data lines (Da-1 and Da-2 are in the same layer).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the display and boundary structure as taught by Cho into Zhou.
An ordinary artisan would have been motivated to use the known technique of Cho in the manner set forth above to produce the predictable result of [0005] – “a display device in which a dead space is reduced at corners in a peripheral area of the display device, by disposing initialization voltage sources over signal lines arranged in a fan-out structure.”
Regarding claim 2, Zhou, as modified by Cho, teaches claim 1 from which claim 2 depends. Zhou further teaches
(Original) The array substrate of claim 1, wherein the first column of
pixel driving circuit (C1) is on a side of the first adjacent data line (34A) away from the second adjacent data line (34B) in the boundary area; and
the second column of pixel driving circuit (C1) is absent on a side of the second adjacent data line (C2) away from the first adjacent data line (C1) in the boundary area.
Zhou does not expressly disclose the other limitations of claim 2.
However, in an analogous art, Cho teaches
the boundary area (Boundary Area).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the boundary structure as taught by Cho into Zhou.
An ordinary artisan would have been motivated to use the known technique of Cho in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 3, Zhou, as modified by Cho, teaches claim 1 from which claim 3 depends. Zhou further teaches
the first adjacent data line (34A) and the second adjacent data line
(34B) are in a same layer.
Zhou does not expressly disclose the other limitations of claim 3.
However, in an analogous art, Cho teaches
(Original) The array substrate of claim 1, further comprising a plurality of
signal lines (V1a – Fig. 12 – {[0056] – “signal lines extended from a scan driver, an emission driver and/or initialization voltage sources”}, {[0203] – “first initialization voltage lines V1 may include in the peripheral area PPA a first portion V1a”) extending along a second direction (DR1 – Fig. 9 – [0203] – “the first direction DR1”) from the boundary area (Boundary Area) into the peripheral area (Peripheral Area – Fig. 9 annotated, see below, shows this);
wherein the first adjacent data line and the second adjacent data line are in a same layer where they cross over the plurality of signal lines (V1a – Fig. 12 shows this – Cho shows the data lines, Da, in the same layer as signal lines, V1a, when they cross over as shown in Fig. 9).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the signal line structure as taught by Cho into Zhou.
An ordinary artisan would have been motivated to use the known technique of Cho in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 4, Zhou, as modified by Cho, teaches claim 3 from which claim 4 depends. Zhou does not expressly disclose the limitations of claim 4.
However, in an analogous art, Cho teaches
(Original) The array substrate of claim 3, further comprising:
a plurality of first layer switching structure (CH13a, CH14a – Fig. 9 – [0198] –
“contact hole CH13a” – these correspond to a plurality of switching structures) in the boundary area (Boundary Area); and
a plurality of signal supply lines (Fig. 9 annotated, see above – [0056] –
“signal lines extended from a scan driver, an emission driver and/or initialization voltage sources” – hereinafter ‘SL’’) in the peripheral area (Peripheral Area) respectively
electrically connected to the plurality of signal lines (Fig. 9 annotated, see above – [0056] – “signal lines extended from a scan driver, an emission driver and/or initialization voltage sources” – hereinafter ‘SL’) in the boundary area (Boundary Area – Fig. 9 annotated, see above, shows this) ;
wherein a respective first layer switching structure (CH14b) connects a pair of signal line (Sb – Fig. 11 – {[0056] – “signal lines extended from a scan driver, an emission driver and/or initialization voltage sources”}, {[0201] – “the first portion Sa of the scan line S with the second portion Sb of the scan line S”}) and signal supply line (Sa – Fig. 11 – [0056] – “signal lines extended from a scan driver, an emission driver and/or initialization voltage sources”, {[0201] – “the first portion Sa of the scan line S with the second portion Sb of the scan line S”}) in different layers.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the switching structure as taught by Cho into Zhou.
An ordinary artisan would have been motivated to use the known technique of Cho in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 5, Zhou, as modified by Cho, teaches claim 1 from which claim 5 depends. Zhou does not expressly disclose the limitations of claim 5.
However, in an analogous art, Cho teaches
(Previously Presented) The array substrate of claim 1, further comprising a
column of layer switching structures (Ch13a, CH14a, CH15a – Fig. 9 – this is interpreted as a column of switching structures) in the boundary area (Boundary Area – Fig. 9 annotated, see above);
wherein, in the boundary area (Boundary Area), the first adjacent data line (Fig. 9 annotated, see above – [0091] – “data lines D” – hereinafter ‘DL1’) and the second adjacent data line (Fig. 9 annotated, see above – [0091] – “data lines D” – hereinafter ‘DL2’) are between the first column of pixel driving circuit (C1) and the column of layer switching structures (Fig. 3 annotated, see below, shows DL1 and DL2 as ‘D’, the switching structures are not shown in Fig. 3 but are shown in Fig. 9 which is an enlarged portion of Fig. 3 – [0193] – “FIG. 9 is an enlarged plan view showing an exemplary embodiment of portion P2 of FIG. 3”).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the switching structure as taught by Cho into Zhou.
An ordinary artisan would have been motivated to use the known technique of Cho in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 6, Zhou, as modified by Cho, teaches claim 1 from which claim 6 depends. Zhou does not expressly disclose the limitations of claim 6.
However, in an analogous art, Cho teaches
(Previously Presented) The array substrate of claim 1, further comprising a
first data signal supply line (Fig. 9 annotated, see above – [0208] – “data line Db may be provided in plural” – hereinafter ‘Db-1’) and a second data signal supply line (Fig. 9 annotated, see above – [0208] – “data line Db may be provided in plural” – hereinafter ‘Db-2’) outside the boundary area (Boundary Area) and in the peripheral area (Peripheral Area);
wherein the first data signal supply line (Db-1) and the second data signal supply line (Db-2) are respectively connected to the first adjacent data line (DL1) and the second adjacent data line (DL1) respectively through a plurality of second layer switching structures (CH17 and CH18 – [0209] – “contact hole CH17 … contact hole CH18”); and
the first data signal supply line (Db-1) and the second data signal supply line (Db-2) are in different layers from each other (Fig. 14 and Fig. 15 show this), and are in layers different from the first adjacent data line (DL1) and the second adjacent data line (DL2 – Fig.14 and Fig 15 show this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the signal line structure as taught by Cho into Zhou.
An ordinary artisan would have been motivated to use the known technique of Cho in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 7, Zhou, as modified by Cho, teaches claim 1 from which claim 7 depends. Zhou does not expressly disclose the limitations of claim 7.
However, in an analogous art, Cho teaches
(Previously Presented) The array substrate of claim 1, wherein the first
adjacent data line (D1 – Fig. 2 – [0091] – “data lines D1 to Dm and the power line PL”) and the second adjacent data line (D2 – Fig. 2 – [0091] – “data lines D1 to Dm and the power line PL”) are between a first voltage supply line (PL1 – Fig. 2 – [0126] – “first power lines PL1”) and a second voltage supply line (Fig. 2 shows second branch of PL1);
the first adjacent data line (D1) and the second adjacent data line (D2) are configured to provide data signals to the first column (Fig. 2 annotated, see below, shows this – hereinafter ‘C1’) of pixel driving circuits and the second column of pixel driving circuits column (Fig. 2 annotated, see below, shows this – hereinafter ‘C2’), respectively (Fig. 2 shows this); and
the first voltage supply line column (Fig. 2 annotated, see below, shows this – hereinafter ‘PL1-1’) and the second voltage supply line column (Fig. 2 annotated, see below, shows this – hereinafter ‘PL1-2’) are configured to provide power supply voltages to the first column of pixel driving circuits (C1) and the second column of pixel driving circuits (C2), respectively.
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the line structure as taught by Cho into Zhou.
An ordinary artisan would have been motivated to use the known technique of Cho in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 8, Zhou, as modified by Cho, teaches claim 1 from which claim 8 depends. Zhou does not expressly disclose the limitations of claim 8.
However, in an analogous art, Cho teaches
(Previously Presented) The array substrate of claim 1, wherein a respective
pixel driving circuit (Fig. 5 shows the pixel driving circuit) comprises:
a second capacitor electrode (Fig 5 – capacitor Cst has a top and bottom electrode) connected to a respective voltage supply line (Fig. 5 shows the top capacitor electrode connected to the voltage supply ELVDD); and
a first semiconductor material layer ([0174] – “The first active pattern ACT1 to seventh active pattern ACT7 include or are made of a semiconductor material” – hereinafter ‘SML1’) comprising a second node portion (Fig. 5 annotated, see below, hereinafter ‘N2P’), a boundary of which being defined by an active layer of a driving transistor (ACT1 – Fig. 5 – [0152] – “first transistor T1 includes a first gate electrode GE1, a first active pattern ACT1” – T1 corresponds to the driving transistor), an active layer of a first transistor (ACT2 – Fig. 5 – [0157] – “second transistor T2 includes a second gate electrode GE2, a second active pattern ACT2” – this corresponds to the second transistor), and an active layer of a third transistor (ACT5 – Fig. 5 – [0163] – “fifth transistor T5 includes a fifth gate electrode GE5, a fifth active pattern ACT5” – this corresponds to the first transistor);
wherein an orthographic projection of the second node portion (N2P) on a base substrate (SUB – Fig. 8 – [0174] – “substrate SUB”) is at least partially non-overlapping with an orthographic projection of the second capacitor electrode (UE – Fig. 8 – [0169] – “The storage capacitor Cst includes a lower electrode LE and an upper electrode UE. The lower electrode LE may be provided or formed as the first gate electrode GE1 of the first transistor T1” – this corresponds to the second capacitor electrode) on the base substrate (SUB – Fig. 8 shows this).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the node structure as taught by Cho into Zhou.
An ordinary artisan would have been motivated to use the known technique of Cho in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 9, Zhou, as modified by Cho, teaches claim 8 from which claim 9 depends. Zhou does not expressly disclose the limitations of claim 9.
However, in an analogous art, Cho teaches
(Original) The array substrate of claim 8, wherein the orthographic
projection of the second node portion (N2P) on the base substrate (SUB) is at least 50% non-overlapping with an orthographic projection of the second capacitor electrode (UE) on the base substrate (SUB – Fig. 6 annotated, see below, shows this).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the capacitor structure as taught by Cho into Zhou.
An ordinary artisan would have been motivated to use the known technique of Cho in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 10, Zhou, as modified by Cho, teaches claim 8 from which claim 10 depends. Zhou does not expressly disclose the limitations of claim 10.
However, in an analogous art, Cho teaches
(Original) The array substrate of claim 8, wherein the second capacitor
electrode (upper electrode of Cst in Fig. 5 – hereinafter ‘UE’) comprises a first part (Fig. 6 annotated, see below – hereinafter ‘UE-1’) and a second part (Fig. 6 annotated, – hereinafter ‘UE-2’);
an orthographic projection of the first part on the base substrate (SUB) is at least 90% non-overlapping with the orthographic projection of the second node portion (N2P) on the base substrate (SUB); and
an orthographic projection of the second part (UE-2) on the base substrate (SUB) is at least partially overlapping with the orthographic projection of the second node portion (N2P) on the base substrate (Fig. 6 annotated, see below, shows this).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the capacitor structure as taught by Cho into Zhou.
An ordinary artisan would have been motivated to use the known technique of Cho in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 11, Zhou, as modified by Cho, teaches claim 10 from which claim 11 depends. Zhou does not expressly disclose the limitations of claim 11.
However, in an analogous art, Cho teaches
(Original) The array substrate of claim 10, wherein the respective pixel
driving circuit further comprises a voltage connecting pad (Fig. 6 annotated, see above – [0182] – “The power line PL is connected to the upper electrode UE of the storage capacitor Cst through third and fourth contact holes CH3 and CH4” – hereinafter ‘VCP’) connected to a first electrode of the third transistor, a respective voltage supply line (PL – Fig. 6 – [0147] – “first supply voltage ELVDD is applied to the power line PL”), and the second capacitor electrode (UE – [0182] – “The power line PL is connected to the upper electrode UE of the storage capacitor Cst through third and fourth contact holes CH3 and CH4”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the power structure as taught by Cho into Zhou.
An ordinary artisan would have been motivated to use the known technique of Cho in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 12, Zhou, as modified by Cho, teaches claim 11 from which claim 12 depends. Zhou does not expressly disclose the limitations of claim 12.
However, in an analogous art, Cho teaches
(Original) The array substrate of claim 11, wherein the orthographic
projection of the second part (UE-2) on the base substrate (SUB) is at least 75% overlapping with an orthographic projection of the voltage connecting pad (VCP – Fig. 6 annotated, see above, shows this) on the base substrate (SUB) ; and
the orthographic projection of the first part (UE-1) on the base substrate (SUB) is non-overlapping with the orthographic projection of the voltage connecting pad (VCP – Fig. 6 annotated, see above, shows this) on the base substrate (SUB).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the capacitor structure as taught by Cho into Zhou.
An ordinary artisan would have been motivated to use the known technique of Cho in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 13, Zhou, as modified by Cho, teaches claim 10 from which claim 13 depends. Zhou does not expressly disclose the limitations of claim 13.
However, in an analogous art, Cho teaches
(Original) The array substrate of claim 10, wherein the second node portion
(N2P) extends along a first direction (DR2 – Fig. 6 – [0187] – “direction DR2”) crossing over a respective gate line (Si – Fig. 6 – [0158] – “gate electrode GE2 is connected to the i.sup.th scan line Si”); and
a first maximum width of the first part (UE-1) along the first direction is greater than a second maximum width of the second part (UE-2) along the first direction by at least 30% (Fig. 6 annotated, see above, shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the capacitor structure as taught by Cho into Zhou.
An ordinary artisan would have been motivated to use the known technique of Cho in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 20, Zhou, as modified by Cho, teaches claim 10 from which claim 13 depends. Zhou further teaches
the array substrate ([0008] – “array substrate”).
Zhou does not expressly disclose the other limitations of claim 20.
However, in an analogous art, Cho teaches
(Previously Presented) A display apparatus, comprising the array substrate
of claim 1, and an integrated circuit (TC – [0058] – “” – this is interpreted as an integrated circuit) connected to the array substrate.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the integrated circuit structure as taught by Cho into Zhou.
An ordinary artisan would have been motivated to use the known technique of Cho in the manner set forth above to produce the predictable result as stated above in claim 1.
Claims 14-15 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou in view of Cho and Chen (US 20220310731 A1).
Regarding claim 14, Zhou, as modified by Cho, teaches claim 1 from which claim 14 depends. Zhou and Cho do not expressly disclose the limitations of claim 14.
However, in an analogous art, Chen teaches
(Previously Presented) The array substrate of claim 1, comprising a first
semiconductor material layer ([0007] – “the switching transistor, the driving transistor, the first light-emitting control transistor, and the second light-emitting control transistor are P-type transistors” – hereinafter ‘P-type’) and a second semiconductor material layer ([0007] – “the compensation transistor, the first initialization transistor, and the second initialization transistor are N-type transistors” – hereinafter ‘N-type’);
wherein the second semiconductor material layer (N-type) comprise at least an active layer of a second transistor (T3 – Fig. 1 – [0043] – “compensation transistor T3”) and at least an active layer of a first reset transistor (T4 – Fig. 1 – [0043] – “first initialization transistor T4”);
the first semiconductor material layer (P-type) comprise at least an active layer of a driving transistor (T1 – Fig. 1 – [0043] – “driving transistor T1”) comprising a first semiconductor material (P-type); and
active layers of the second transistor (T3) and the first reset transistor (T4) comprise a second semiconductor material (N-type) different from the first semiconductor material (P-type).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the semiconductor material structure as taught by Chen into Zhou and Cho.
An ordinary artisan would have been motivated to use the known technique of Chen in the manner set forth above to produce the predictable result of [0028] – “both low leakage current characteristics of oxide transistors and high mobility characteristics of low-temperature polysilicon transistors can be achieved, so that the pixel driving circuit is more stable and the display effect of the display panel is improved.”
Regarding claim 15, Zhou, as modified by Cho and Chen, teaches claim 14 from which claim 15 depends. Zhou and Cho do not expressly disclose the limitations of claim 15.
However, in an analogous art, Chen teaches
(Currently Amended) The array substrate of claim 14, wherein an
orthographic projection of a respective voltage supply line (802 combined with 901 – Figs. 10 and 11 – [0081] – “first blocking member 901 is connected to the power supply high-potential signal line 802” – hereinafter ‘VSL’) on a base substrate (100 – [0088] – “substrate 100”) covers at least 50% of an orthographic projection of the active layer of the second transistor (T3 – [0082] – “first blocking member 901 on the oxide active layer covers a channel region of the compensation transistor T3 and a channel region of the first initialization transistor T4”) on the base substrate (100), and covers at least 50% of an orthographic projection of the active layer of the first reset transistor (T4 – [0082] – “first blocking member 901 on the oxide active layer covers a channel region of the compensation transistor T3 and a channel region of the first initialization transistor T4”) on the base substrate (100).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the semiconductor structure as taught by Chen into Zhou and Cho.
An ordinary artisan would have been motivated to use the known technique of Chen in the manner set forth above to produce the predictable result as stated above in claim 14.
Regarding claim 18, Zhou, as modified by Cho, teaches claim 1 from which claim 18 depends. Zhou and Cho do not expressly disclose the limitations of claim 18.
However, in an analogous art, Chen teaches
(Previously Presented) The array substrate of claim 1, wherein a respective
pixel driving circuit (Fig. 1 – [0088] – “pixel driving circuit” – hereinafter ‘PDC’) comprises a node connecting line (804 – Fig. 10 – [0077] – “connection line 804”), a second transistor (T3), a first reset transistor (T4), and a storage capacitor (C1 – Fig. 1 – [0043] – “storage capacitor C1”);
wherein the node connecting line (804 – [0078] – “connection line 804 is connected to a gate of the driving transistor T1 and a second electrode plate 403 of the storage capacitor C1”) connects a first electrode of the second transistor (T3) and a second electrode of the first reset transistor (T4 – Fig. 8 shows these connected) to a first capacitor electrode (403 = Fig. 6 – [0078] – “electrode plate 403 of the storage capacitor C1”) of the storage capacitor (C1); and
an orthographic projection of a respective voltage supply line (VSL) on a base substrate (100) covers at least 50% of an orthographic projection of the node connecting line (804 – Fig. 10 and Fig. 11 shows this) on the base substrate (100).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the node structure as taught by Chen into Zhou and Cho.
An ordinary artisan would have been motivated to use the known technique of Chen in the manner set forth above to produce the predictable result as stated above in claim 14.
Regarding claim 19, Zhou, as modified by Cho and Chen, teaches claim 18 from which claim 19 depends. Zhou and Cho do not expressly disclose the limitations of claim 19.
However, in an analogous art, Chen teaches
(Original) The array substrate of claim 18, wherein at least a portion of the
respective voltage supply line (VSL) and at least a portion of the node connecting line (VSL) have conforming contours (Fig. 10 and Fig 11 show conforming contours which is interpreted as non-straight portions).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the power structure as taught by Chen into Zhou and Cho.
An ordinary artisan would have been motivated to use the known technique of Chen in the manner set forth above to produce the predictable result as stated above in claim 14.
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou in view of Cho and Cho et al. (US 20220336563 A1 – hereinafter Cho-563).
Regarding claim 16, Zhou, as modified by Cho, teaches claim 1 from which claim 16 depends. Zhou and Cho do not expressly disclose the limitations of claim 16.
However, in an analogous art, Cho-563 teaches
(Previously Presented) The array substrate of claim 1, further comprising a
respective second gate line (SL2 – Fig. 6 – [0109] – “compensation transistor T3 may be turned on according to the second scan signal Sn′ transferred via the second scan line SL2”) connected to a gate electrode of a second transistor (T3 – Fig. 6 – [0109] – “compensation transistor T3 “ – this corresponds to a second transistor);
the respective second gate line (SL2 – [0148] – “the sixth gate wiring 1530 may correspond to the second scan line SL2 of FIG. 6, along with the fourth gate wiring 1320”) comprises a first branch (1320 – [0148] – “the second scan signal Sn′ may be applied to the pixels via the sixth gate wiring 1530 and/or the fourth gate wiring 1320”) in a second conductive layer (Fig. 10 – [0042] – “FIGS. 8 to 15 are schematic layouts illustrating elements such as transistors and capacitors for each of layers in the display apparatus of FIG. 7”) and a second branch (1530 – [0148] – “the second scan signal Sn′ may be applied to the pixels via the sixth gate wiring 1530 and/or the fourth gate wiring 1320”) in a third conductive layer (Fig. 13 – [0042] – “FIGS. 8 to 15 are schematic layouts illustrating elements such as transistors and capacitors for each of layers in the display apparatus of FIG. 7”); and
an orthographic projection of the first branch (1320) on a base substrate ([0148] – “substrate 100) at least partially overlaps ([0148] – “wiring 1530 may extend in the first direction (or x-axis direction). When seen in the direction perpendicular to the substrate 100 (or z-axis direction), the sixth gate wiring 1530 may overlap the fourth gate wiring 1320”) with an orthographic projection of the second branch (1530) on the base substrate (100).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the gate line structure as taught by Cho-563 into Zhou and Cho.
An ordinary artisan would have been motivated to use the known technique of Cho-563 in the manner set forth above to produce the predictable result of [0005] – “a region in which a driver, etc. are located has a large area, or a region from the driver to a display area has a large area. Accordingly, an area of a dead space in which display devices are not arranged is excessively large.”
Regarding claim 17, Zhou, as modified by Cho, teaches claim 1 from which claim 16 depends. Zhou and Cho do not expressly disclose the limitations of claim 17.
However, in an analogous art, Cho-563 teaches
(Previously Presented) The array substrate of claim 1, further comprising a
respective reset control signal line (SLp – Fig. 6 – [0147] – “the previous scan line SLp of FIG. 6, along with the third gate wiring 1310. The previous scan signal Sn−1 may be applied to the pixels via the fifth gate wiring 1520 and/or the third gate wiring 1310”) connected to a gate electrode of a first reset transistor (first initialization transistor T4”);
the respective reset control signal line (SLp) comprises a first branch (1310 – Fig. 6 – [0147] – “the previous scan line SLp of FIG. 6, along with the third gate wiring 1310. The previous scan signal Sn−1 may be applied to the pixels via the fifth gate wiring 1520 and/or the third gate wiring 1310”) in a second conductive layer (Fig. 10) and a second branch (1520 – Fig. 6 – [0147] – “the previous scan line SLp of FIG. 6, along with the third gate wiring 1310. The previous scan signal Sn−1 may be applied to the pixels via the fifth gate wiring 1520 and/or the third gate wiring 1310”) in a third conductive layer (Fig. 13); and
an orthographic projection of the first branch (1310) on a base substrate (1520) at least partially overlaps with an orthographic projection of the second branch on the base substrate ([0147] – “seen in the direction perpendicular to the substrate 100 (or z-axis direction), the fifth gate wiring 1520 may overlap the third gate wiring 1310. In the fifth gate wiring 1520, a portion overlapping the second semiconductor layer 1400 may include a first initialization upper gate electrode of the first initialization transistor T4”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the signal line structure as taught by Cho-563 into Zhou and Cho.
An ordinary artisan would have been motivated to use the known technique of Cho-563 in the manner set forth above to produce the predictable result as stated above in claim 16.
Pertinent Art
For the benefits of the Applicant, US 20220149133 A1 and US 20220013619 A1 are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose the combination of limitations including "boundary and peripheral areas”.
Conclusion
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/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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