DETAILED ACTION
This final action is in response to the amendment and remarks filed on 05/19/2026 for application 17/996,533.
Claims 14-15, 17-19, and 25-26 have been amended. Claim 24 has been canceled.
Claims 14-23 and 25-26 thereby remain pending in the application. Claims 14, 25, and 26 are independent claims.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
The examiner notes that there was an erroneous acknowledgement of foreign priority in the office action mailed 11/20/2025. A corrected Bibliographic Data Sheet has been attached to this office action to reflect that no foreign priority claim was made.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14-19, 23 and 25-26 are rejected under 35 U.S.C. 103 as being unpatentable over Hari et al. (“Making Convolutions Resilient via Algorithm-Based Error Detection Techniques”, published IEEE 2 Mar 2021, cited in IDS dated 10/19/2022), hereinafter Hari, in view of Zhao et al. (“FT-CNN: Algorithm-Based Fault Tolerance for Convolutional Neural Networks”, published IEEE 31 Dec 2020), hereinafter Zhao, and Kuutti et al. (“A Survey of Deep Learning Applications to Autonomous Vehicle Control”, published IEEE 7 Jan 2020), hereinafter Kuutti.
Regarding claim 14, Hari teaches A method for operating a hardware platform for an inference calculation of a convolutional neural network (“this article, we focus on algorithmically verifying convolutions, the most resource-demanding operations in CNNs. We use checksums to verify convolutions. We identify the feasibility and performance related challenges that arise in algorithmically detecting errors in convolutions in optimized CNN inference deployment platforms (e.g., TensorFlow or TensorRT on GPUs) that fuse multiple network layers and use reduced-precision operations, and demonstrate how to overcome them” [Hari Abstract]), the hardware platform having at least one acceleration module that is specialized to calculate a convolution of an input matrix with a convolution kernel by applying the convolution kernel to various positions within the input matrix, and to output a result of the convolving as a two-dimensional output matrix (“Recent advancement in the ability of Convolutional Neural Networks (CNNs) to accurately process real-time telemetry has boosted their use in safety-critical and high-performance computing (HPC) systems…Processors deployed in safety-critical and HPC systems employ ECC and/or parity in major SRAM structures. However, this protection is typically not sufficient to meet the requirements of ISO 26262 for all hardware error sources. For intermittent and permanent faults, non-storage elements contribute significantly towards the total error rates in GPUs and DNN-accelerators that dedicate significant chip area to logic [6]. As CNNs are posed to dominate the runtimes of many safety-critical and HPC systems, the goal of this paper is to develop a low-cost CNN-specific resilience solution that allows the full system to meet the target markets’ resilience requirements without full duplication and is easy to implement…Over 90 percent of the computation during CNN inference is in convolutions [24]” [Hari pages 1-2 Introduction]; “Input fmaps are represented as a 4-D tensor in most CNNs. Each fmap is a 2-D tensor with height (H) and width (W)…Each output fmap value is produced by performing a dot product between a filter and a same-sized portion of the input fmap’s tensor. An example is shown in the highlighted cells in Fig. 1, along with the formula to compute each of the output fmap values” [Hari page 3 The Convolution Operation]; see Fig. 1 including Filters (F), Input feature maps (I), and Output feature maps (O) – “Fig. 1. A typical convolution operation used by most CNNs” [Hari page 3]; GPU and DNN accelerators dedicate processing power to convolution, wherein convolution follows the typical procedure of convolution of applying a filter tensor (i.e., convolution kernel) to portions of an input feature map (i.e., input matrix) to produce output feature maps (i.e., output matrix)) , the method comprising the following steps:
convolving, by the acceleration module, an input matrix having input data of the convolutional neural network with a plurality of convolution kernels, so that a multiplicity of two-dimensional output matrices results ([Hari pages 1-2 Introduction] and [Hari page 3 The Convolution Operation] and Fig. 1 [Hari page 3] as detailed above; The convolution operation is performed at the 2-D tensor (i.e., matrix) level, and fmaps are stacked and batched respectively to form 3-D and 4-D tensors)
summing the convolution kernels elementwise to form a control kernel; (“Verifying every output value of a convolution might require duplicating the entire operation. Instead, the focus of this work is to verify just the reduced output, i.e., sum of all the output elements…Based on this key insight, we explore the following three schemes to verify a convolution, which are summarized in Fig. 2” [Hari page 3 Convolution ABED Approach]; “In this scheme, a 3-D filter checksum tensor is computed by performing an element-wise sum (using sum as a checksum function) across all the 3-D filter tensors (1 in Fig. 2a)” [Hari page 3 Filter Checksum-Based (FC)]; see Fig. 2 - (a) Filter Checksum-based detection (FC) including (1) Filter checksum generation
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[Hari page 4]; The filter tensors (i.e., convolution kernel) are summed elementwise to form a filter checksum tensor
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(i.e., control kernel))
convolving, by the acceleration module, the input matrix with the control kernel, so that a two-dimensional control matrix results; (“This new checksum filter is convolved with the input maps to compute an extra output fmap, which is used to verify the original fmaps’ values” [Hari page 3 Filter Checksum-Based (FC)]; see Fig. 2 - (a) Filter Checksum-based detection (FC) including extra output maps (shown in purple) of dimension P x Q (to which output fmaps (O) are then compared); The convolution of the checksum filter (i.e., control kernel) with input fmaps (i.e., matrices) produces additional output fmaps (i.e., control matrix))
comparing each element at a respective position of the control matrix with a respective sum of elements summed from those elements in each of the output matrices located at the respective position in each of the output matrices (“The original output fmaps’ values are reduced across the channel dimension to generate a reduced fmap, which is compared element-wise for equality with the extra output fmap for verification” [Hari pages 3-4 Filter Checksum-Based (FC)]; see Fig. 2 - (a) Filter Checksum-based detection (FC) including Element-wise compare of extra output maps
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to the channel-wise reduction (i.e., sum) of the original output fmaps
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and 3) Output verification
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[Hari page 4])
However, Hari does not expressly teach responsive to the comparison yielding a deviation for an element of the control matrix, checking with at least one additional control calculation, whether an element of at least one output matrix corresponding to the element of the control matrix was correctly calculated.
In the same field of endeavor, Zhao teaches a means of using checksum techniques to algorithmically detect errors in inference calculations of a CNN executed on accelerator hardware (“Traditional fault tolerance methods are not suitable for CNN inference because error-correcting code is unable to protect computational components, instruction duplication techniques incur high overhead, and existing algorithm-based fault tolerance (ABFT) techniques cannot protect all convolution implementations. In this article, we focus on how to protect the CNN inference process against soft errors as efficiently as possible, with the following three contributions. (1) We propose several systematic ABFT schemes based on checksum techniques and analyze their fault protection ability and runtime thoroughly” [Zhao Abstract]) that responsive to a comparison yielding a deviation for an element of an output checksum matrix (see Table 1 – “Notations and Symbols Used in This Paper” [Zhao page 2]; “At the block level, the convolution operation is similar to matrix-matrix multiplication. The element (i, j) of O is calculated by using the ith element of D and the jth element of W“ [Zhao page 3 Preliminary Analysis-Convolution]; “Soft error protection includes error detection and error correction. Error detection means that the scheme can detect soft errors without knowing the exact location. Error correction means that the scheme can locate the soft error locations and recover the incorrect result” [Zhao page 5 Fault Model]; “Specifically, Co5, Co6, and Co7 are the output checksums we will use in this scheme. Similar to Co1, using the distributive property can get three equations between the output checksums and output as follows
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So5, So6, and So7 are defined as the output summations corresponding to Co5, Co6, and Co7…Using the output checksums, we can get the following.
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The location i, j can be obtained by
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and
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. Then the soft error can be fixed by adding
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to Oij. If only soft error detection is required, we do not need to compute Co6 and Co7, thus reducing the number of computations. Input checksums regarding Cd1, Cd2 and Cw1, Cw2, however, are still required for soft error detection. We denote such a detection scheme by CoC-D” [Zhao pages 4-5 Checksum-of-Checksum Scheme (CoC/Coc-D)]; “To achieve the highest protection ability and lowest overhead, we propose a multischeme workflow by integrating the four schemes, as shown in Fig. 7. The workflow is made up of two modules: error detection and error correction. In our designed workflow, we use CoC-D to detect errors because it has the lowest overhead. For the error correction, we put CoC in the beginning because it is the most lightweight method…The error detection modules will be executed for every execution whether there is a soft error or not…The error correction module will not be executed until some soft errors are detected” [Zhao page 7 Multischeme Workflow for Soft Error Protection]; In the disclosed workflow, to reduce computational overhead, steps required for error correction (including determining exact error location) are only executed in response to error detection, wherein error detection module CoC-D comprises comparing output checksum matrix Co5 to summation of output matrices So5 to determine deviation
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), check[s] with at least one additional control calculation, whether an element of at least one output matrix corresponding to the element of the output checksum matrix was correctly calculated (see [Zhao pages 4-5 Checksum-of-Checksum Scheme (CoC/Coc-D)] and [Zhao page 7 Multischeme Workflow for Soft Error Protection] as detailed above; “Fig. 2 demonstrates the protection ability of the CoC scheme when soft errors strike the input or output data. As shown in Fig. 2a, multiple soft errors can be detected by using only Co5. A single soft error in O can be corrected by CoC using all checksums including Co5, Co6, and Co7, as shown in Fig. 2b” [Zhao page 5 Soft Error Protection Ability of CoC Scheme]; see Fig. 2 – (b) CoC Error Detection [Zhao page 5]; see Fig. 7 including CoC-d – Error is detected –> CoC – “Fig. 7. Multischeme workflow designed to detect/correct soft errors” [Zhao page 7]; Responsive to an error being detected, the CoC module serves as an additional calculation to further check and determine location of the detected error in the output matrix).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated responsive to a comparison yielding a deviation for an element of an output checksum matrix, check[s] with at least one additional control calculation, whether an element of at least one output matrix corresponding to the element of the output checksum matrix was correctly calculated as taught by Zhao into Hari because they are both directed towards using checksum techniques to algorithmically detect errors in inference calculations of a CNN executed on accelerator hardware. Given that Hari already uses a substantially similar checksum comparison technique to Zhao for detecting errors in convolutions, and emphasizes a focus on error detection over error localization and correction due to the added computational overhead (“Lastly, processing the output matrix twice to generate both the row and column checksums for error correction capability can also introduce high overheads. Optimized implementations that process the output just once will reduce this overhead. By focusing on error detection alone, ABED significantly speeds up this step by generating a single checksum” [Hari page 11 Overhead Analysis of a Traditional ABET Technique]), a person of ordinary skill in the art would recognize the value of incorporating the teachings of Zhao to thereby enable error localization and correction, but while also continuing the objective of limiting computational overhead by only introducing additional checksum schemes once errors are actually detected ([Zhao page 7 Multischeme Workflow for Soft Error Protection] as detailed above) via, e.g., the low-cost ABED checksum technique of Hari, and also by starting with the most lightweight error correction checksum schemes first (“For the error correction, we put CoC in the beginning because it is the most lightweight method. By comparison, FC has highest correction ability but also highest time overhead, so we put it at the end of the workflow” [Zhao page 7 Multischeme Workflow for Soft Error Protection]).
However, the combination does not expressly teach processing the output matrices to form a control signal; and controlling, using the control signal, a vehicle and/or a system for quality control of mass-produced products and/or a system for medical imaging and/or an access control system.
In the same field of endeavor, Kuutti teaches a means of applying CNNs via high-performance computing systems for real-life applications (e.g. autonomous vehicular systems) (“Recently, deep learning has gained attention due to the numerous state-of-the-art results it has achieved in fields such as image classification and speech recognition [24]–[26]. This has led to increasing use of deep learning in autonomous vehicle applications, including planning and decision making [27]–[31], perception [32]–[36], as well as mapping and localisation [37]–[39]. The performance of Convolutional Neural Networks (CNNs) with raw camera inputs has the potential to reduce the number of sensors used by autonomous vehicles. This has led to some organisations investigating autonomous vehicles without expensive sensors such as LIDAR, instead employing extensive use of deep learning for scene understanding, object recognition, semantic segmentation, and motion estimation” [Kuutti pages 1-2 Introduction]; “Indeed, while neural networks are hardly new, the research interest and adoption to various applications has exploded in recent years due to increased computing power, especially through parallel graphics processing units (GPUs) which can significantly reduce training time and improve performance” [Kuutti page 4 Lateral Control Systems]) that process[es] the output matrices to form a control signal; (“The strong results of deep learning in these perception problems have also sparked interest in using Deep Neural Networks (DNNs) to produce control actions in autonomous vehicles. Indeed, autonomous vehicle control often has a strong link to perception, as many techniques use CNNs to predict control actions based on images of the scene, without any separate perception module, thereby removing the separation between the perception and control layer” [Kuutti pages 1-2 Introduction]) and
control[s], using the control signal, a vehicle and/or a system for quality control of mass-produced products and/or a system for medical imaging and/or an access control system ([Kuutti pages 1-2 Introduction] as detailed above).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated processing the output matrices to form a control signal; and controlling, using the control signal, a vehicle and/or a system for quality control of mass-produced products and/or a system for medical imaging and/or an access control system as taught by Kuutti into the combination because both Hari and Kuutti are directed towards applying CNNs via high-performance computing systems for real-life applications. Given that Hari already discusses known applications of CNNs to autonomous vehicle systems (“For example, autonomous vehicles (AVs) employ CNNs to perform complex tasks such as vehicle, pedestrian, lane, and road-sign detection [3], [34]” [Hari page 1 Introduction]), a person of ordinary skill in the art would recognize the value of incorporating the teachings of Kuutti to thereby enable training of the combined system for vehicular applications (e.g., outputting control actions).
Regarding claim 15, the combination of Hari, Zhao and Kuutti teaches the limitations of parent claim 14, and Hari further teaches wherein, for at least one convolution kernel of the plurality of convolution kernels, the convolving further comprises a bias value corresponding to the at least one convolution kernel is added to the elements of the output matrix produced with the at least one convolution kernel, and a sum of all bias values is also added to all elements of the control matrix (“Convolution, bias, and activation operations are typically fused together for performance. Such fused operations perform O = activation(conv(x) + bias). For int8 convolutions, I and F use int8, and O uses either int8 or fp32. Fig. 4 explains the logical flow of computation within such fused kernels. For int8 convolutions, the output of the convolution operation is an int32 result (ConvOut in the figure)…Bias is added to ScaledOut” [Hari page 6 Kernel Modifications]; see Fig. 4 including Fused convolution, bias, and activation kernel – “Fig. 4. The logical computation flow in a fused convolution, bias, and activation kernel” [Hari page 6])
Regarding claim 16, the combination of Hari, Zhao and Kuutti teaches the limitations of parent claim 14, and Zhao further teaches wherein in the checking with the additional control calculation, checking whether a line or a column, containing the element to be checked, of the at least one output matrix was correctly calculated (see Fig. 7 including CoC-d – Error is detected –> CoC –Unable to correct error–>RC/CIC Controller [Zhao page 7]; see implementation of Row Checksum Scheme (RC) and Column Checksum Scheme (CIC) [Zhao page 4, sects. 3.4 and 3.5]; If, e.g., the CoC module is unsuccessful, the additional calculations may further comprise additional row (i.e. line) and column checksum schemes RC and CIC, that compare checksums to summations on a row-by-row or column-by-column basis to detect location of errors in the output matrix)
Regarding claim 17, the combination of Hari, Zhao and Kuutti teaches the limitations of parent claim 16, and Zhao further teaches in the additional control calculation:
the input matrix is expanded with verification elements; (“Since the row checksum scheme and column checksum scheme are symmetric with each other, we discuss them together in this section. As shown in Fig. 4a, the row checksum scheme can detect and correct soft errors if they are in the same row” [Zhao page 5 Soft Error Protection Ability of Row Checksum Scheme and Column Checksum Scheme]; see Fig. 4 – (a) Row Checksum Scheme including additional checksum elements Cd1 and Cd2 (shown in yellow) added to D1, D2,…Dn (i.e., input matrix) [Zhao page 6])
the verification elements are convolved, by the acceleration module, with the convolution kernel that corresponds to the at least one output matrix to obtain a control value; (see Fig 4 – (a) Row Checksum Scheme including D1,D2..Dn,Cd1,Cd2 convolved with W1, W2,…,Wn (i.e., convolution kernel) to obtain output O [Zhao page 6])
a sum of the elements in the line or the column is compared with the control value; (see implementation of Row Checksum Scheme (RC) [Zhao page 4]) and
responsive to the comparison of the sum of the elements in the line or the column with the control value yielding a deviation, determining that the line or the column was not correctly calculated, and the element to be checked of the output matrix was also not correctly calculated (see implementation of Row Checksum Scheme (RC) [Zhao page 4]).
Regarding claim 18, the combination of Hari, Zhao and Kuutti teaches the limitations of parent claim 14, and Zhao further teaches wherein in which, in response to the determination that an element of an output matrix was not correctly calculated, the element is corrected by the deviation yielded in the comparison (“Then the soft error can be fixed by adding
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to Oij” [Zhao page 6 Checksum-of-Checksum Scheme (CoC/CoC-D)])
Regarding claim 19, the combination of Hari, Zhao and Kuutti teaches the limitations of parent claim 14, and Zhao further teaches wherein in response to the checking determining that all of the elements of the at least one output matrix were correctly calculated, determining that the element of the control matrix was not correctly calculated (“Fig. 3 illustrates the protection ability of the CoC scheme when soft errors happen inside the checksums. Such soft errors can cause inconsistency among the output checksums of CoC, which can be used for error detection. For example, in Fig. 3a, Cd1 is corrupted, leading to corrupted Co5 and Co6 with correct Co7. We can detect this abnormal pattern when comparing checksums with the summation of O to detect the input checksum corruption. The input D, W, and output O are clean and without soft errors since fault frequency is at most once per convolution. Thus, we can safely discard all the checksums and finish this convolution computation” [Zhao page 5 Soft Error Protection Ability of CoC Scheme]; Besides detecting soft errors within the elements of output matrices, the CoC scheme may detect errors that happen within the calculation of output checksums (including, e.g., control matrix) themselves, and given the assumption that only one fault may occur per convolutional layer (see [Zhao page 5 Fault Model] – note this assumption is synonymous with the assumption set forth in the instant specification [page 6 lines 15-26]), it logically follows that the elements of the output matrix themselves are error-free (i.e., correctly calculated)).
Regarding claim 23, the combination of Hari, Zhao, and Kuutti teaches the limitations of parent claim 14, and Kuutti further teaches wherein the input data includes optical image data and/or thermal image data and/or video data and/or radar data and/or ultrasonic data and/or lidar data, the input data having been obtained through a physical measurement process and/or through a partial or complete simulation of the physical measurement process, and/or through a partial or complete simulation of a technical system observable with the physical measurement process (“The rapid progress in the implementation of deep learning systems on autonomous vehicles has led to the availability of diverse deep learning data sets for autonomous driving and perception. Perhaps the most well known data set for autonomous driving is the KITTI benchmark suite [70], [71], which includes multiple data sets for evaluation of stereo vision, optical flow, scene flow, simultaneous localisation and mapping, object detection and tracking, road detection and semantic segmentation” [Kuutti page 3 Datasets and Tools for Deep Learning]; Comprehensive datasets provide training data, including various types of image data, drawn from real-world benchmarks (i.e., physical measurement processes)).
Regarding claim 25, it is a product claim that substantially corresponds to the method of claim 14, which is already taught by the combination of Hari, Zhao, and Kuutti as detailed above. Hari further teaches A non-transitory machine-readable data carrier on which is stored a computer program for operating a hardware platform that performs the claimed functions (“Runtime Overhead Evaluation. We experimentally evaluate the runtime of convolutions by creating a cuDNN-based workload that sets up, initializes, and runs convolutions in a loop. We compile this workload using CUDA 10 and use cuDNN 7.3 on both a Jetson AGX Xavier system and an x86- based desktop with a V100-based GPU (Titan V) [29], [31]” [Hari page 7 Overhead Evaluation]). Consequently, claim 25 is rejected for the same reasons as claim 14.
Regarding claim 26, it is an apparatus claim that substantially corresponds to the method of claim 14, which is already taught by the combination of Hari, Zhao, and Kuutti as detailed above. Hari further teaches A computer configured to operate a hardware platform that performs the claimed functions ([Hari page 7 Overhead Evaluation] as detailed in claim 25 above). Consequently, claim 26 is rejected for the same reasons as claim 14.
Claims 20-22 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Hari, Zhao, and Kuutti, as applied to claim 14 above, further in view of Xu et al. (“Safety Design of a Convolutional Neural Network Accelerator with Error Localization and Correction”, available IEEE Xplore 17 Feb 2020), hereinafter Xu.
Regarding claim 20, the combination of Hari, Zhao, and Kuutti teaches the limitations of parent claim 14.
However, the combination does not expressly teach wherein when the comparison yields a deviation with regard to at least one hardware component or at least one memory area that can be regarded as the cause of the deviation, an error counter is incremented upward.
In the same field of endeavor, Xu teaches a means of using checksum techniques to algorithmically detect errors in inference calculations of a CNN executed on accelerator hardware (“[10] extended ABFT and proposed Algorithm Based Error Checker (ABEC) for a WS CNN accelerator to identify errors of an Atomic operation for all the PEs during run-time and Algorithm Based Cluster Checker (ABCC) to isolate the errors to a PE cluster….In this paper, we proposed two design techniques for low latency error detection and error correction with enhanced error localization capability and minimal power and area overhead. Specifically, this paper makes four contributions. First, we proposed ABAEC-1 which extends ABEC with an additional low overhead error checker to check PEs against themselves during replay operation and localize an error down to each PE with no performance degradation…Second, we proposed ABAEC-2 which extends ABEC with a weighted checksum to perform on-the-fly instant error localization and error correction with no performance degradation. Third, we applied the proposed techniques to a WS CNN accelerator and compared across coverage, latency, localization and Performance Power Area (PPA) efficiency metric for safety applications. Last, we discussed and generalized ABEC to cover other dataflow architectures” [Xu page 1 Introduction]) wherein when the comparison yields a deviation with regard to at least one hardware component or at least one memory area that can be regarded as the cause of the deviation, an error counter is incremented upward (“The proposed design techniques not only detect the errors on-the-fly but also perform error diagnosis to localize the errors to a Processing Element (PE) for on-line fault management and recovery” [Xu Abstract]; “we proposed ABAEC-1 which extends ABEC with an additional low overhead error checker to check PEs against themselves during replay operation and localize an error down to each PE with no performance degradation” [Xu page 1 Introduction]; “2) Error Replay and Recovery: When the ABEC detects an error, error diagnosis can be performed with replay operation during run-time…. The recovery logic logs the error occurrence for each replay operation by incrementing an error counter” [Xu page 4 ABAEC-1 with Error Replay and Correction])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated wherein when the comparison yields a deviation with regard to at least one hardware component or at least one memory area that can be regarded as the cause of the deviation, an error counter is incremented upward as taught by Xu into the combination because Hari and Xu are both directed towards using checksum techniques to algorithmically detect errors in inference calculations of a CNN executed on accelerator hardware. Incorporating the teachings of Xu would enable the combination to not only detect transient (i.e., soft) errors, but also further determine when repeated errors signal a permanent hardware fault or malfunction (i.e., hard error), and thus a need for reconfiguration (“The replay operations are executed N times till a soft error disappears, or a hard error is determined after the replay error counter exceeds the threshold. If a soft error is determined, the system will resume normal operation with no hardware reconfiguration required. If a hard error is determined, a spare MAC Cell will be swapped in, and the system will resume normal operation” [Xu pages 8-9 Latency Evaluation and Performance Discussions]).
Regarding claim 21, the combination of Hari, Zhao, Kuutti, and Xu teaches the limitations of parent claim 20, and Xu further teaches wherein, in response to a determination that the error counter has exceeded a specified threshold value, the hardware component or the memory area is recognized as defective (“In case the error counter exceeds a predefined threshold, the error is caused by a permanent fault, and the recovery logic signals the need for hardware reconfiguration” [Xu page 4 ABAEC-1 with Error Replay and Correction])
Regarding claim 22, the combination of Hari, Zhao, Kuutti, and Xu teaches the limitations of parent claim 21, and Xu further teaches wherein the hardware platform is reconfigured in such a way that, for further calculations, instead of the hardware component recognized as defective, or the memory area recognized as defective, a reserve hardware component or a reserve memory area is used (“Once a faulty MAC Cell with a permanent fault is identified the recovery logic will notify the safety manager to perform hardware reconfiguration to replace the faulty MAC Cell with a spare one” [Xu page 5 ABAEC-1 with Error Replay and Correction]).
Response to Amendment and Arguments
The amendment filed 05/13/2026 has been entered.
Applicant’s amendment with respect to resolving claim objections and indefiniteness rejections under 35 U.S.C. 112(b) has been considered, and the objections and rejections are consequently withdrawn.
The remarks filed 05/13/2026 have been fully considered.
Applicant’s remarks traversing the non-eligible subject matter rejections under 35 U.S.C. 101 set forth in the office action mailed 05/13/2026, in view of claims 1-23 and 25-26 as amended, have been considered and are persuasive in part (see section Step 2A, Prong Two in Remarks [pages 8-10]).
Consequently, the rejections are withdrawn.
Applicant’s remarks traversing the obviousness rejections under 35 U.S.C. 103 set forth in the office action mailed 05/13/2026, in view of claims 14-23 and 25-26 as amended, have been considered but are not persuasive.
Applicant alleges that Hari does not disclose that the same accelerator module used for the calculation of the control matrix is used for the calculation of the output matrices, because the office action does not expressly map both operations as being performed by one and the same accelerator.
The examiner respectfully disagrees. Applicant’s argument appears to rely on a narrower interpretation of the term “acceleration module” than what is warranted by the claims, e.g., as referring to a specific, isolated accelerator hardware unit (e.g., sub-unit or chip) that is exclusively designed to perform the recited operations. Under a broad interpretation however, the term “acceleration module” merely encompasses any processing block or hardware engine within an overall hardware platform that is configured to execute convolution operations, which Hari expressly suggests via its disclosure [Hari pages 1-2 Introduction].
It is further important to note that Hari implicitly suggests use of inference accelerators for convolution operations, as the intended purpose of the disclosed checksum error detection procedure is entirely to account for accelerator errors, and the procedure is particularly designed around this use case (“Employing an algorithmic resilience technique in such platforms for seamless application across architectures (e.g., CPUs, GPUs, or accelerators) is desirable, but has never been analyzed. Several feasibility-, performance-, and coverage-related challenges remain. (1) The increasing use of reduced-precision data types (e.g., 8- and 4-bit integers) in CNN inference accelerators introduces new challenges for checksum-based error detection techniques” [Hari page 2 Introduction]; “We design precise checksum-based checks for deterministic and strong coverage. We focus on fixed-point arithmetic, as many commercial inference accelerators such as ARM MLC, Cadence C5, Ceva NeuPro NP4000, Google TPUv1, Imagination PowerVR Series2NX, Wave DPU, and Mobileye EQ3 and EQ4 [12] use just fixed-point data types for performance and energy reasons” [Hari page 2 Introduction]; “Using the raw failure rate of 20.49 FIT/Mb for SRAM manufactured using 16nm process and DNN accelerator size parameters (1,344 PEs with a total of 49 Mb SRAM) as listed in a prior study [23], the raw FIT rate of the inference accelerator will be about 1,000 FIT (one failure in one million hours of operation) without considering any high-level masking” [Hari page 12 Overhead Due to Aggressive Detection]). As such, it would be within the scope of what would be suggested to one of ordinary skill in the art by the disclosure to have all convolution operations be performed by the same accelerator unit, such that the designed checksum procedure would then accurately account for potential errors by that accelerator.
Applicant has not presented further arguments with respect to the dependent claims. As such, amended claims 14-23 and 25-26 stand rejected under 35 U.S.C. 103.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VIJAY M BALAKRISHNAN whose telephone number is (571) 272-0455. The examiner can normally be reached 10am-5pm EST Mon-Thurs.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JENNIFER WELCH can be reached on (571) 272-7212. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/V.M.B./
Examiner, Art Unit 2143
/JENNIFER N WELCH/Supervisory Patent Examiner, Art Unit 2143
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