Prosecution Insights
Last updated: July 17, 2026
Application No. 17/997,394

ARRANGEMENT AND METHOD FOR PERFORMING A VECTOR-MATRIX MULTIPLICATION BY MEANS OF CAPACITIVE OR RESISTIVE SYNAPTIC COMPONENTS

Non-Final OA §112
Filed
Oct 28, 2022
Priority
Apr 29, 2020 — EU 20172081.0 +2 more
Examiner
SANDIFER, MATTHEW D
Art Unit
2151
Tech Center
2100 — Computer Architecture & Software
Assignee
Semron GmbH
OA Round
1 (Non-Final)
80%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allowance Rate
519 granted / 646 resolved
+25.3% vs TC avg
Strong +25% interview lift
Without
With
+24.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
10 currently pending
Career history
654
Total Applications
across all art units

Statute-Specific Performance

§101
23.1%
-16.9% vs TC avg
§103
45.3%
+5.3% vs TC avg
§102
9.3%
-30.7% vs TC avg
§112
18.9%
-21.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 646 resolved cases

Office Action

§112
DETAILED ACTION The instant application having Application No. 17/997,394 filed on 10/28/2022 is presented for examination by the examiner. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Claims 14-15, 17, and 19 are objected to for reciting “The method as claimed in one of claims 11”. The claims should instead read “The method as claimed in claim 11”. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 1-19 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. As per Claim 1, it recites “a matrix arrangement of capacitive synaptic components or resistive synaptic components or mixed capacitive-resistive synaptic components in a differential arrangement”. However, as it is worded, it is unclear if the matrix arrangement applies to each of the three types of synaptic components or only the capacitive and/or resistive components. Similarly, it is unclear if the “differential arrangement” applies to each of the three types of synaptic components or only the mixed capacitive-resistive components. The Examiner suggests amending the limitation to recite “a matrix of synaptic components in a differential arrangement, wherein the synaptic components are capacitive synaptic components or resistive synaptic components or mixed capacitive-resistive synaptic components”, which makes clear that the “matrix arrangement” and “differential arrangement” applies to any/all of the three types of components. Additionally, the claim recites “with periodic charging and discharging”. However, it is unclear what the statement is referring to, i.e. it is unclear what components or what part of “the arrangement” is charging and discharging periodically. Additionally, the claim recites the limitations “the bit lines” in line 6, “the word lines” in line 10, and “the voltage of the oscillator” in line 11. There is insufficient antecedent basis for this limitation in the claim. Finally, the claim recites “the oscillator” in lines 12 and 13. However, it is unclear which of the “one or more oscillators” this limitation is antecedently referring. The Examiner suggests amending the limitation to recite “the clock generator is designed to react to a rising or falling edge of the one or more oscillators or to the positive and negative value range of the voltage of the one or more oscillators”. As per Claims 2-4, the claims recite the limitation “the oscillator”. However, as described above, it is unclear which of the “one or more oscillators” this limitation is antecedently referring. As per Claims 3 and 11-13, the claims recite the limitations “the bit line” and “the word line”. However, it is unclear which of the plurality of “bit lines” and “word lines” the limitations are antecedently referring. As per Claims 11-12, the claims recite the limitation “a charge integration amplifier”. It is unclear if this limitation is meant to antecedently refer to the “charge integration amplifier” claimed in Claim 1. As per Claim 15, the claim recites the limitation “the input variable”. There is insufficient antecedent basis for this limitation in the claim. As per Claim 16, the claim recites the limitation “the weights”. There is insufficient antecedent basis for this limitation in the claim. As per Claim 18, the claim recites “the appropriate frequency”. There is insufficient antecedent basis for this limitation in the claim. Moreover, the term “appropriate” is a relative term which renders the claim indefinite. The term “appropriate” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Additionally, the phrase "for example" in the claim renders the claim indefinite because it is unclear whether the limitation(s) following the phrase are part of the claimed invention. See MPEP § 2173.05(d). As per Claim 19, the claim recites the limitations “the supply lines of the matrix arrangement” and “the capacitive energy supply”. There is insufficient antecedent basis for these limitations in the claim. Additionally, the claim recites “the capacitive synaptic component itself”. It is unclear which of the plurality of capacitive synaptic components this limitation is meant to antecedently refer. The remaining dependent Claims 5-10, 14 and 17 are rejected for the reasons presented above, due to being dependent upon a rejected base claim. Allowable Subject Matter Claims 1-19 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) set forth in this Office action. The following is a statement of reasons for the indication of allowable subject matter: The closest found prior art is Asnaashari et al. (US 2019/0103162), Ge et al. (US 2017/0323677), and Applicant’s admitted prior art (Yayla et al., US 5,343,555). Asnaashari discloses a resistive random access memory array comprising multiple sets of bitlines and multiple wordlines for performing arithmetic functions such as multiplication, wherein clock source(s) can facilitate selection of wordlines or bitlines in response to external or internal commands. Ge discloses a memcapacitive crossbar array for performing a matrix-vector multiplication, wherein each bitline is coupled to an evaluation gate, i.e. a transistor, for allowing charge on the bitline to accumulate at the output of the evaluation, the accumulated charge representing a dot product of a matrix column and an input vector. As noted in the instant specification, Yayla discloses switched-capacitor synapses wherein the synaptic capacitances are charged and discharged periodically by means of two clock pulses which do not overlap and the charge is transferred to a charge integration amplifier. However, the closest found references fail to teach a matrix of synaptic components coupled to a clock generator, wherein the clock generator is designed to alternately connect the bit lines to a charge integration amplifier or ground via a changeover switch or is designed to alternately connect the bit lines to a non-inverting input and an inverting input of the charge integration amplifier via a changeover switch, the word lines are electrically connected to one or more oscillators, and the clock generator is designed to react to a rising or falling edge of the voltage of the oscillator or to the positive and negative value range of the voltage of the oscillator. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW SANDIFER whose telephone number is (571)270-5175. The examiner can normally be reached Mon-Fri 9:30am-6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571) 272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MATTHEW D SANDIFER/Primary Examiner, Art Unit 2151
Read full office action

Prosecution Timeline

Oct 28, 2022
Application Filed
Jun 16, 2026
Non-Final Rejection mailed — §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
80%
Grant Probability
99%
With Interview (+24.9%)
3y 0m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 646 resolved cases by this examiner. Grant probability derived from career allowance rate.

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