DETAILED ACTION
The instant application having Application No. 17/998,221 filed on 11/8/2022 is presented for examination by the examiner. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 26-29, 31, 34 and 45 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoda et al. (US 2019/0197656).
As per Claim 26, Yoda discloses an apparatus comprising: matrix processing circuitry to perform a matrix processing operation on first and second input operands to generate a result matrix, where the result matrix is a two-dimensional matrix (Abstract and Figures 4-8, 19-20 and Paragraphs 0031, 0049, 0054, 0066 and 0116, a GPU includes a processor core comprising sum-of-product arithmetic unit(s) for performing two-dimensional convolution operation(s), wherein the inputs and output(s) are two-dimensional matrices);
operand storage circuitry to store information for forming the first and second input operands for the matrix processing circuitry (Figures 2, 8, 19-20 and Paragraphs 0031, 0038-0041, 0045, 0049, 0065-0068, 0107-0108 and 0116, filter coefficients (i.e. weights) and image data are transferred from main memory and stored in SRAM, wherein format-converted image data and filter coefficients are provided from SRAM to a sum-of-product arithmetic unit(s) for convolution processing);
and masking circuitry to perform a masking operation to mask at least part of the matrix processing operation or the information stored to the operand storage circuitry based on masking state data indicative of one or more masked row or column positions to be treated as representing a masking value (Figure 8-11, 13-16, 19-20 and Paragraphs 0046, 0065-0069, 0074-0075, 0077-0079, 0083, and 0085-0086, the format converter includes a compression arithmetic unit 41 and a padding arithmetic unit 43 for generating neighborhood matrix image data, i.e. data2, from the image data stored in SRAM_0, i.e. data0, according to a compression mask and a padding mask, wherein each mask value corresponds to a two-dimensional position/element of a two-dimensional image data matrix (see e.g. Figures 11 and 13), and wherein the convolution/sum-of-product operations are performed on the resulting masked (i.e. compressed and padded) neighborhood matrix image data).
As per Claim 27, Yoda discloses the apparatus according to claim 26, in which the masking value is zero (Figure 13 and Paragraphs 0055 and 0085, a padding value P may be “0” according to a Pmask value of “3”, and a masked value is “0” according to a Pmask value of “0”).
As per Claim 28, Yoda discloses the apparatus according to claim 26, in which the masking value is selected from a plurality of masking values depending on at least one of: a masking value selection parameter specified by an instruction which causes the masking operation to be performed; a control value stored in a control register; and, a masking vector specifying separate masking values for a plurality of elements of a masked row/column (Figures 9-10, 13, 16 and Paragraphs 0068, 0071-0072 and 0092-0094, control data is set in a control register CNT_REG which controls setting of the compression mask, padding data, the padding mask, etc., wherein the padding arithmetic unit selects a masking value of “0” or “P”, for example, by a selector SEL1, in response to the setting of the control data and control by the control circuit CNT).
As per Claim 29, Yoda discloses the apparatus according to claim 26, in which the masking state data has an encoding identifying within a two-dimensional array of elements, elements to be treated as representing the masking value (Figures 11-13 and Paragraphs 0084-0086, Cmask is encoded to selectively extract or mask, i.e. identify, particular matrix elements from e.g. the two-dimensional image data shown in Figure 11).
As per Claim 31, Yoda discloses the apparatus according to claim 26, in which the masking state data has an encoding capable of indicating, as masked row or column positions, at least two non-adjacent row or column positions separated by at least one non-masked row or column position (Figures 11-13 and Paragraphs 0084-0086, Cmask and Pmask are encoded such that non-adjacent matrix elements from data0 are selected and padded, i.e. masked, in order to mask non-adjacent rows or columns, such as by padding column 0 and row 0 and masking out columns 3-14 and rows 3-14 from the padded image data in Figure 11 to generate neighborhood matrix (0) centered on pixel X0 shown in Figure 12).
As per Claim 34, Yoda discloses the apparatus according to claim 26, in which: the matrix processing circuitry comprises the masking circuitry, and is responsive to said masking information to perform said matrix processing operation with a portion of one of said first and second operands corresponding to said one or more masked row or column positions treated as representing the masking value instead of an actual value of said portion of said one of said first and second operands stored in the operand storage circuitry (Figures 1-3, 8, 11-13 and Paragraphs 0045-0046, 0049 and 0064-0065, the GPU executes matrix convolution operations, i.e. two-dimensional convolution, and includes format conversion circuitry FMT_C, wherein FMT_C sets the masks for extracting and padding neighborhood matrix image data, i.e. an operand of the convolution operation, wherein padded elements in the neighborhood matrix are treated as mask values instead of an actual image data values; moreover, the neighborhood matrix data string data2 comprises masked values of “0” instead of actual image data values).
As per Claim 45, Yoda discloses a data processing method comprising: storing, in operand storage circuitry, information for forming first and second input operands for a matrix processing operation (Figures 2, 8, 19-20 and Paragraphs 0031, 0038-0041, 0045, 0049, 0065-0068, 0107-0108 and 0116, filter coefficients (i.e. weights) and image data are transferred from main memory and stored in SRAM, wherein format-converted image data and filter coefficients are provided from SRAM to a sum-of-product arithmetic unit(s) for convolution processing);
and performing a matrix processing operation on the first and second input operands to generate a result matrix, where the result matrix is a two-dimensional matrix (Abstract and Figures 4-8, 19-20 and Paragraphs 0031, 0049, 0054, 0066 and 0116, a GPU includes a processor core comprising sum-of-product arithmetic unit(s) for performing two-dimensional convolution operation(s), wherein the inputs and output(s) are two-dimensional matrices);
and performing a masking operation to mask at least part of the matrix processing operation or the information stored to the operand storage circuitry based on masking state data indicative of one or more masked row or column positions to be treated as representing a masking value (Figure 8-11, 13-16, 19-20 and Paragraphs 0046, 0065-0069, 0074-0075, 0077-0079, 0083, and 0085-0086, the format converter includes a compression arithmetic unit 41 and a padding arithmetic unit 43 for generating neighborhood matrix image data, i.e. data2, from the image data stored in SRAM_0, i.e. data0, according to a compression mask and a padding mask, wherein each mask value corresponds to a two-dimensional position/element of a two-dimensional image data matrix (see e.g. Figures 11 and 13), and wherein the convolution/sum-of-product operations are performed on the resulting masked (i.e. compressed and padded) neighborhood matrix image data).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 44 is rejected under 35 U.S.C. 103 as being unpatentable over Yoda in view of Bainville et al. (US 2020/0034145).
As per Claim 44, Yoda does not explicitly disclose the apparatus according to claim 26, in which the first and second input operands are one-dimensional vector operands.
However, Bainville teaches a computation engine that performs masked vector and matrix multiply-accumulate operations, e.g. for neural networks, wherein the input operands may be one-dimensional vectors or two-dimensional matrices (Abstract and Figures 2-3, 5-6 and Paragraphs 0037, 0057 and 0059, the computation engine performs vector multiplications and/or outer product computations on vector operands or matrix operands from the X and Y memories, wherein the computations may be masked, e.g. restrict computations when the edges/corners of the matrices are reached).
It would have been obvious to one of ordinary skill in the art prior to the effective filing of the claimed invention to combine the masked matrix computation engine taught by Bainville with the masked matrix computation architecture of Yoda because Bainville provides for increased flexibility and increased parallelism, as well as additional computations/modes of operation (Bainville, Paragraphs 0002-0003, numerous parallel computations, offset provides additional flexibility in the location of operands, vector and matrix modes).
Allowable Subject Matter
Claims 30, 32-33, and 35-43 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW SANDIFER whose telephone number is (571)270-5175. The examiner can normally be reached Mon-Fri 9:30am-6pm.
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/MATTHEW D SANDIFER/Primary Examiner, Art Unit 2151
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