Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Notice of Pre-AIA or AIA Status
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7-15, 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zheng (WO 2020/199326).
Regarding claim 1, Zheng (figure 20) discloses a display panel, comprising:
a plurality of pixel repeating units (R+ G- B+; see annotated drawing 1), each of the pixel repeating units comprising a first sub-pixel column, a second sub-pixel column, and a third sub-pixel column that are arranged in a row direction, wherein the first sub-pixel column comprises a plurality of first sub-pixels arranged in a column direction, the second sub-pixel column comprises a plurality of second sub-pixels arranged in the column direction, the third sub-pixel column comprises a plurality of third sub-pixels arranged in the column direction, and wherein the plurality of pixel repeating units comprise a first pixel repeating unit and a second pixel repeating unit disposed adjacent to the first pixel repeating unit (R+ G- B+); and
a plurality of source lines (the lines connected to D1+) wherein one of the source lines is disposed between the first pixel repeating unit and the second pixel repeating unit,
wherein the one of the source lines (the lines connected to D1+) is electrically connected to the first sub-pixel column of the second pixel repeating unit through a plurality of first transistors (T4-1 and T4-2), the one of the source lines is electrically connected to the third sub-pixel column of the second pixel repeating unit through a plurality of third transistors (B+; T6-1 and T6-2; the lines are connected to the first output terminal D1+), and the one of the source lines is electrically connected to the second sub-pixel column of the first pixel repeating unit through a plurality of second transistors (G- and T2-1 and T2-2; the lines are connected to the first output terminal D1+);
the display panel further comprising:
a first auxiliary source line, disposed on one side of the plurality of pixel repeating units and connected by the second transistors to the second sub-pixel column of one of the pixel repeating units adjacent to the first auxiliary source line (the lines are connected to the first output terminal D1+; see annotated drawing 1); and
a plurality of data lines (R+ G- B+), comprising a first data line electrically connected to the first sub-pixel column of the second pixel repeating unit, a third data line electrically connected to the third sub-pixel column of the second pixel repeating unit, and a second data line electrically connected to the second sub-pixel column of the first pixel repeating unit (R+ G- B+);
wherein the first transistors are electrically connected to the first data line, the second transistors are electrically connected to the second data line, and the third transistors are electrically connected to the third data line (R+ G- B+ and the lines connected to D1+).
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Regarding claim 2, Zheng (figure 20) discloses a second auxiliary source line disposed on the other side of the plurality of pixel repeating units, wherein the second auxiliary source line is connected to the first sub-pixel column and the third sub-pixel column of one of the pixel repeating units adjacent to the second auxiliary source line respectively through the plurality of first transistors and the plurality of third transistors (see annotated drawing 1).
Regarding claim 3, Zheng (figure 20) discloses
first demultiplexing lines (Mux 4-1), wherein gates of the plurality of first transistors (T4-1 and T4-2) are electrically connected to the first demultiplexing lines, sources of at least one of the first transistors corresponding to one of the pixel repeating units are electrically connected to one of the source lines, and drains of at least one of the first transistors corresponding to the one of the pixel repeating units are electrically connected to the corresponding first data line;
second demultiplexing lines (Mux 3-1), wherein gates of the plurality of second transistors (T2-1 and T2-2) are electrically connected to the second demultiplexing lines, sources of at least one of the second transistors corresponding to the one of the pixel repeating units are electrically connected to the corresponding one of the source lines, and drains of at least one of the second transistors corresponding to the one of the pixel repeating units are electrically connected to the corresponding second data line; and
third demultiplexing lines (Mux 6-1), wherein gates of the plurality of third transistors (T6-1 and T6-2) are electrically connected to the third demultiplexing lines, sources of at least one of the third transistors corresponding to the one of the pixel repeating units are electrically connected to the corresponding one of the source lines, and drains of at least one of the third transistors corresponding to the one of the pixel repeating units are electrically connected to the corresponding third data line.
Regarding claim 4, Zheng (figure 20) discloses wherein all of the first transistors, the second transistors, and the third transistors are located in a display area (on substrate area).
Regarding claim 5, Zheng (figure 20) discloses wherein the first data line, the second data line, and the third data line are disposed between two adjacent source lines in the row direction (M4-2, Mux 3-2, Mux 6-2), wherein the display panel further comprises: connection lines, each spanning the corresponding third data line to connect the corresponding second data line and one of the second transistors (see annotated drawing 1).
Regarding claim 7, Zheng (figure 20) discloses wherein the plurality of first sub-pixels located in the same row of the plurality of pixel repeating units are connected to one of the first demultiplexing lines, the plurality of second sub-pixels located in the same row of the plurality of pixel repeating units are connected to one of the second demultiplexing lines, and the plurality of third sub-pixels located in the same row of the plurality of pixel repeating units are connected to one of the third demultiplexing lines (Mux 1 to Mux 6).
Regarding claim 8, Zheng (figure 20) discloses wherein in one of the pixel repeating units, polarity of the first sub-pixel column is opposite to polarity of the second sub-pixel column, and the polarity of the first sub-pixel column is the same as polarity of the third sub-pixel column; and in two adjacent pixel repeating units, polarity of the third sub-pixel column in one of the pixel repeating units is opposite to polarity of the first sub-pixel column in the other of the pixel repeating units (R+ G- B+ and R- G+ B-).
Regarding claim 9, Zheng (figure 20) discloses a display panel, comprising:
a plurality of pixel repeating units (R+ G- B+; see annotated drawing 1), each of the pixel repeating units comprising a first sub-pixel column, a second sub-pixel column, and a third sub-pixel column that are arranged in a row direction, wherein the first sub-pixel column comprises a plurality of first sub-pixels arranged in a column direction, the second sub-pixel column comprises a plurality of second sub-pixels arranged in the column direction, the third sub-pixel column comprises a plurality of third sub-pixels arranged in the column direction, and wherein the plurality of pixel repeating units comprise a first pixel repeating unit and a second pixel repeating unit disposed adjacent to the first pixel repeating unit (R+ G- B+); and
a plurality of source lines (the lines connected to D1+) wherein one of the source lines is disposed between the first pixel repeating unit and the second pixel repeating unit,
wherein the one of the source lines (the lines connected to D1+) is electrically connected to the first sub-pixel column of the second pixel repeating unit through a plurality of first transistors (T4-1 and T4-2), the one of the source lines is electrically connected to the third sub-pixel column of the second pixel repeating unit through a plurality of third transistors (B+; T6-1 and T6-2; the lines are connected to the first output terminal D1+), and the one of the source lines is electrically connected to the second sub-pixel column of the first pixel repeating unit through a plurality of second transistors (G- and T2-1 and T2-2; the lines are connected to the first output terminal D1+).
Regarding claim 10, Zheng (figure 20) discloses a first auxiliary source line, disposed on one side of the plurality of pixel repeating units and connected by the second transistors to the second sub-pixel column of one of the pixel repeating units adjacent to the first auxiliary source line (the lines are connected to the first output terminal D1+; see annotated drawing 1).
Regarding claim 11, Zheng (figure 20) discloses a second auxiliary source line disposed on the other side of the plurality of pixel repeating units, wherein the second auxiliary source line is connected to the first sub-pixel column and the third sub-pixel column of one of the pixel repeating units adjacent to the second auxiliary source line respectively through the plurality of first transistors and the plurality of third transistors (see annotated drawing 1).
Regarding claim 12, Zheng (figure 20) discloses
a plurality of data lines (R+ G- B+), comprising a first data line electrically connected to the first sub-pixel column of the second pixel repeating unit, a third data line electrically connected to the third sub-pixel column of the second pixel repeating unit, and a second data line electrically connected to the second sub-pixel column of the first pixel repeating unit (R+ G- B+);
wherein the first transistors are electrically connected to the first data line, the second transistors are electrically connected to the second data line, and the third transistors are electrically connected to the third data line (R+ G- B+ and the lines connected to D1+).
Regarding claim 13, Zheng (figure 20) discloses
first demultiplexing lines (Mux 4-1), wherein gates of the plurality of first transistors (T4-1 and T4-2) are electrically connected to the first demultiplexing lines, sources of at least one of the first transistors corresponding to one of the pixel repeating units are electrically connected to one of the source lines, and drains of at least one of the first transistors corresponding to the one of the pixel repeating units are electrically connected to the corresponding first data line;
second demultiplexing lines (Mux 3-1), wherein gates of the plurality of second transistors (T2-1 and T2-2) are electrically connected to the second demultiplexing lines, sources of at least one of the second transistors corresponding to the one of the pixel repeating units are electrically connected to the corresponding one of the source lines, and drains of at least one of the second transistors corresponding to the one of the pixel repeating units are electrically connected to the corresponding second data line; and
third demultiplexing lines (Mux 6-1), wherein gates of the plurality of third transistors (T6-1 and T6-2) are electrically connected to the third demultiplexing lines, sources of at least one of the third transistors corresponding to the one of the pixel repeating units are electrically connected to the corresponding one of the source lines, and drains of at least one of the third transistors corresponding to the one of the pixel repeating units are electrically connected to the corresponding third data line.
Regarding claim 14, Zheng (figure 20) discloses wherein all of the first transistors, the second transistors, and the third transistors are located in a display area (on substrate area).
Regarding claim 15, Zheng (figure 20) discloses wherein the first data line, the second data line, and the third data line are disposed between two adjacent source lines in the row direction (M4-2, Mux 3-2, Mux 6-2), wherein the display panel further comprises: connection lines, each spanning the corresponding third data line to connect the corresponding second data line and one of the second transistors (see annotated drawing 1).
Regarding claim 17, Zheng (figure 20) discloses wherein the plurality of first sub-pixels located in the same row of the plurality of pixel repeating units are connected to one of the first demultiplexing lines, the plurality of second sub-pixels located in the same row of the plurality of pixel repeating units are connected to one of the second demultiplexing lines, and the plurality of third sub-pixels located in the same row of the plurality of pixel repeating units are connected to one of the third demultiplexing lines (Mux 1 to Mux 6).
Regarding claim 18, Zheng (figure 20) discloses wherein in one of the pixel repeating units, polarity of the first sub-pixel column is opposite to polarity of the second sub-pixel column, and the polarity of the first sub-pixel column is the same as polarity of the third sub-pixel column; and in two adjacent pixel repeating units, polarity of the third sub-pixel column in one of the pixel repeating units is opposite to polarity of the first sub-pixel column in the other of the pixel repeating units (R+ G- B+ and R- G+ B-).
Regarding claim 19, Zheng (figure 20) discloses an electronic terminal comprising the display panel according to claim 9.
Regarding claim 20, Zheng (figure 20) discloses a first auxiliary source line, disposed on one side of the plurality of pixel repeating units and connected by the second transistors to the second sub-pixel column of one of the pixel repeating units adjacent to the first auxiliary source line (the lines are connected to the first output terminal D1+; see annotated drawing 1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Zheng (WO 2020/199326) in view of Cho (US 2007/0002195).
Regarding claim 6, Zheng (figure 20) discloses wherein each of the connection lines comprises: a first connection portion disposed in a layer same as at least one layer of the second transistors (the substrate layer). However, Zheng is silent regarding a second connection portion electrically connected to the first connection portion through a via and disposed at a layer same as a layer of the data lines. Cho (figure 4) teaches a second connection portion electrically connected to the first connection portion through a via and disposed at a layer same as a layer of the data lines (104, 124, 128). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the connection lines as taught by Cho in order to reduce the material cost and equipment investment cost and simplify the manufacturing process.
Regarding claim 16, Zheng (figure 20) discloses wherein each of the connection lines comprises: a first connection portion disposed in a layer same as at least one layer of the second transistors (the substrate layer). However, Zheng is silent regarding a second connection portion electrically connected to the first connection portion through a via and disposed at a layer same as a layer of the data lines. Cho (figure 4) teaches a second connection portion electrically connected to the first connection portion through a via and disposed at a layer same as a layer of the data lines (104, 124, 128). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the connection lines as taught by Cho in order to reduce the material cost and equipment investment cost and simplify the manufacturing process.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAUREN NGUYEN whose telephone number is (571)270-1428. The examiner can normally be reached on Monday - Thursday, 8:00 AM -6:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jennifer Carruth, can be reached at 571-272-9791. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAUREN NGUYEN/Primary Examiner, Art Unit 2871
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