Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This communication is responsive to the Amendment filed on 4/10/2026.
In the Instant Amendment, Claim(s) 1, 2, 5, 8, 13, 16, 19 and 24 has/have been amended; Claim(s) 4, 6, 9-12 and 17 was/were cancelled; Claim(s) 1, 5 and 16 is/are independent claims. Claims 1-3, 7-8, 13-16 and 18-24 have been examined and are pending in this application.
Information Disclosure Statement
The information disclosure statement(s) submitted on 4/10/2026 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Response to Arguments
The objection to claim 5 is withdrawn because of the amendment as suggested.
Applicant's arguments filed 4/10/2026 have been fully considered but they are not persuasive.
Regarding claims 1, 5 and 16, Applicant’s arguments with respect to claim(s) 1, 5 and 16 regarding the new added feature have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the current argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites the limitation "the first layer and the second layer" in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 7, 13-16, 18 and 21-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al (US 20120002089 A1) in views of Kenichi (US 20100237390 A1) and Mehta et al (US 20210168314 A1).
Regarding claim 1, Wang teaches An active pixel for use in a
a first photodiode (PPD);
a first transfer transistor (TX1) directly coupled to and operatively coupled to the first photodiode; and
a second transfer transistor (TX2) directly coupled to and operatively coupled to the first photodiode, wherein the first transfer transistor and the second transfer transistor reside at opposite sides of the first photodiode (Figs. 8A, 23, 27);
a first floating diffusion node (FD1) directly coupled to and operatively coupled to the first transfer transistor and a source follower (SF1) (Fig. 11);
a second floating diffusion node (FD2) directly coupled to and operatively coupled to the second transfer transistor and operatively coupled to the source follower (Fig. 11); and
a transistor (SH) for pixel binning disposed between the first floating diffusion node and the second floating diffusion node (Fig. 24; paras. 0075, 0094; “"2.sup.nd sample" is the value read from FD1 and FD2, after SH has been activated to charge share between FD1 and FD2”),
but fails to teach
An active pixel for use in a digital pixel sensor imaging system;
wherein the first photodiode includes a plurality of discrete implant regions formed by an iterative n-implant layer methodology, the plurality of discrete implant regions each extending in both a width direction and a thickness direction of the first photodiode, the plurality of discrete implant regions having successively increasing impurity concentrations such that an impurity concentration of each successive implant region is greater than an impurity concentration of a previous implant region, thereby providing an impurity concentration gradient within the first photodiode, and wherein an electric field within the first photodiode based on the impurity concentration gradient induces an electron drift current from a first side of the first photodiode to a second side of the first photodiode such that charge from the first photodiode is transferred to both the first transfer transistor and the second transfer transistor.
However, in the same field of endeavor Kenichi teaches
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wherein the first photodiode includes a plurality of discrete implant regions formed by an iterative n-implant layer methodology, the plurality of discrete implant regions each extending in both a width direction and a thickness direction of the first photodiode, the plurality of discrete implant regions having successively increasing impurity concentrations such that an impurity concentration of each successive implant region is greater than an impurity concentration of a previous implant region, thereby providing an impurity concentration gradient within the first photodiode, and wherein an electric field within the first photodiode based on the impurity concentration gradient induces an electron drift current from a first side of the first photodiode to a second side of the first photodiode (Fig. 10; para. 0127: “the photodiode section 4C in the solid-state image capturing element 1C of Embodiment is configured of the four stages of the impurity concentrations and the impurity concentration is formed to be higher as it gets close to the transfer gate 9. The magnitude of the N type impurity concentration is N--<N2-<N1-<N<N+(FD) in the photodiode section 4C. In the meantime, the potential becomes stronger towards the transfer gate 9, and the location proximal to the side wall of the transfer gate 9 is the point with the strongest potential. The signal charges on which photoelectric conversion are performed in the larger photodiode 4C are collected to this point in the horizontal direction (substrate surface direction) and the vertical direction (substrate depth direction), and the complete electric charge transferring is performed more easily for the collected signal charges from the photodiode 4C”) such that charge from the first photodiode is transferred (Figs. 9-10) to both the first transfer transistor and the second transfer transistor (already taught by Wang),
Therefore, it would have been obvious to one of ordinary skill in this art before the effective filing date of the claimed invention (AIA ) to use the teachings as taught by Kenichi in Wang to have wherein the first photodiode includes a plurality of discrete implant regions formed by an iterative n-implant layer methodology, the plurality of discrete implant regions each extending in both a width direction and a thickness direction of the first photodiode, the plurality of discrete implant regions having successively increasing impurity concentrations such that an impurity concentration of each successive implant region is greater than an impurity concentration of a previous implant region, thereby providing an impurity concentration gradient within the first photodiode, and wherein an electric field within the first photodiode based on the impurity concentration gradient induces an electron drift current from a first side of the first photodiode to a second side of the first photodiode such that charge from the first photodiode is transferred to both the first transfer transistor and the second transfer transistor for enabling controlled charge drift toward multiple storages to allow faster complete charge transfer yielding a predicted result.
Moreover, in the same field of endeavor Mehta teaches
An active pixel for use in a digital pixel sensor imaging system (Figs. 5A, C, 3; para. 0081; pixels 310 configured as combined or shared event detection (DVS) and image sensor (IS) pixels 501 that perform both event detection and image sensor functions).
Therefore, it would have been obvious to one of ordinary skill in this art before the effective filing date of the claimed invention (AIA ) to use the teachings as taught by Mehta in the combination to have an active pixel for use in a digital pixel sensor imaging system for higher temporal resolution and dynamic range with lower power consumption yielding a predicted result.
Regarding claim 2, the combination of Wang, Kenichi and Mehta teaches everything as claimed in claim 1. In addition, Wang teaches wherein the first transfer transistor and the second transfer transistor are located on the second side (peripheral side) of the first photodiode (Figs. 8A, 23, 27).
Regarding claim 3, the combination of Wang, Kenichi and Mehta teaches everything as claimed in claim 1. In addition, Wang teaches wherein the first transfer transistor and the second transfer transistor include an active layer intersecting a poly layer and a charge well layer configured as a floating diffusion layer (Fig. 27).
Regarding claim 5, Wang teaches An active pixel for use in a
a first photodiode (PPD);
a first transfer transistor (TX1) directly coupled to and operatively coupled to the first photodiode;
a second transfer transistor (TX2) directly coupled to and operatively coupled to the first photodiode, wherein the first transfer transistor and the second transfer transistor reside at opposite sides of the first photodiode (Figs. 8A, 11);
a floating diffusion node (FD1) directly coupled to and operatively coupled to the first transfer transistor (Fig. 11); and
a drain (of RST2) directly coupled to and operatively coupled to the second transfer transistor (TX2), directly coupled to a power supply line (VDD), and configured to receive charge output by the second transfer transistor (TX2) (Figs. 11-12; para. 0075),
but fails to teach
An active pixel for use in a digital pixel sensor imaging system;
wherein the first photodiode includes a plurality of discrete implant regions formed by an iterative n-implant layer methodology, the plurality of discrete implant regions each extending in both a width direction and a thickness direction of the first photodiode, the plurality of discrete implant regions having successively increasing impurity concentrations such that an impurity concentration of each successive implant region is greater than an impurity concentration of a previous implant region, thereby providing an impurity concentration gradient within the first photodiode, and wherein an electric field within the first photodiode based on the impurity concentration gradient induces an electron drift current from a first side of the first photodiode to a second side of the first photodiode such that charge from the first photodiode is transferred to both the first transfer transistor and the second transfer transistor.
However, in the same field of endeavor Kenichi teaches
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wherein the first photodiode includes a plurality of discrete implant regions formed by an iterative n-implant layer methodology, the plurality of discrete implant regions each extending in both a width direction and a thickness direction of the first photodiode, the plurality of discrete implant regions having successively increasing impurity concentrations such that an impurity concentration of each successive implant region is greater than an impurity concentration of a previous implant region, thereby providing an impurity concentration gradient within the first photodiode, and wherein an electric field within the first photodiode based on the impurity concentration gradient induces an electron drift current from a first side of the first photodiode to a second side of the first photodiode (Fig. 10; para. 0127: “the photodiode section 4C in the solid-state image capturing element 1C of Embodiment is configured of the four stages of the impurity concentrations and the impurity concentration is formed to be higher as it gets close to the transfer gate 9. The magnitude of the N type impurity concentration is N--<N2-<N1-<N<N+(FD) in the photodiode section 4C. In the meantime, the potential becomes stronger towards the transfer gate 9, and the location proximal to the side wall of the transfer gate 9 is the point with the strongest potential. The signal charges on which photoelectric conversion are performed in the larger photodiode 4C are collected to this point in the horizontal direction (substrate surface direction) and the vertical direction (substrate depth direction), and the complete electric charge transferring is performed more easily for the collected signal charges from the photodiode 4C”) such that charge from the first photodiode is transferred (Figs. 9-10) to both the first transfer transistor and the second transfer transistor (already taught by Wang),
Therefore, it would have been obvious to one of ordinary skill in this art before the effective filing date of the claimed invention (AIA ) to use the teachings as taught by Kenichi in Fossum to have wherein the first photodiode includes a plurality of discrete implant regions formed by an iterative n-implant layer methodology, the plurality of discrete implant regions each extending in both a width direction and a thickness direction of the first photodiode, the plurality of discrete implant regions having successively increasing impurity concentrations such that an impurity concentration of each successive implant region is greater than an impurity concentration of a previous implant region, thereby providing an impurity concentration gradient within the first photodiode, and wherein an electric field within the first photodiode based on the impurity concentration gradient induces an electron drift current from a first side of the first photodiode to a second side of the first photodiode such that charge from the first photodiode is transferred to both the first transfer transistor and the second transfer transistor for enabling controlled charge drift toward multiple storages to allow faster complete charge transfer yielding a predicted result.
Moreover, in the same field of endeavor Mehta teaches
An active pixel for use in a digital pixel sensor imaging system (Figs. 5A, C, 3; para. 0081; pixels 310 configured as combined or shared event detection (DVS) and image sensor (IS) pixels 501 that perform both event detection and image sensor functions).
Therefore, it would have been obvious to one of ordinary skill in this art before the effective filing date of the claimed invention (AIA ) to use the teachings as taught by Mehta in the combination to have an active pixel for use in a digital pixel sensor imaging system for higher temporal resolution and dynamic range with lower power consumption yielding a predicted result.
Regarding claim 7, the combination of Wang, Kenichi and Mehta teaches everything as claimed in claim 1. In addition, Wang teaches further comprising:
a second photodiode; a third transfer transistor operatively coupled to the second photodiode; and a fourth transfer transistor operatively coupled to the second photodiode, wherein the third transfer transistor and the fourth transfer transistor reside at opposite sides of the second photodiode (Figs. 8A, 23, 24, 27; another PPD has the same structure as in claim 1), wherein:
Moreover, Kenichi teaches an electron drift current within the second photodiode causes two direction charge transfer of charge of the second photodiode to the third transfer transistor and the fourth transfer transistor (for the same reason as in claim 1 for another pixel).
Regarding claim 13, the combination of Wang, Kenichi and Mehta teaches everything as claimed in claim 11. In addition, Kenichi teaches wherein the first photodiode comprises at least one additional layer having a different impurity concentration than the first layer and the second layer; and wherein a magnitude and a direction of the electric field is adjusted based on the plurality of discrete implant regions that the first photodiode includes (Fig. 10; para. 0127).
Therefore, it would have been obvious to one of ordinary skill in this art before the effective filing date of the claimed invention (AIA ) to use the teachings as taught by Kenichi in the combination to have wherein the first photodiode comprises at least one additional layer having a different impurity concentration than the first layer and the second layer; and wherein a magnitude and a direction of the electric field is adjusted based on the plurality of discrete implant regions that the first photodiode includes for arranging multiple doping layers enabling controlled charge drift toward multiple storages to allow faster complete charge transfer yielding a predicted result.
Regarding claim 14, the combination of Wang, Kenichi and Mehta teaches everything as claimed in claim 1. In addition, Wang teaches wherein the first photodiode is a two-way charge transfer photodiode (Figs. 23, 24).
Regarding claim 15, the combination of Wang, Kenichi and Mehta teaches everything as claimed in claim 1. In addition, Wang teaches wherein the active pixel implements a backside illumination (or illuminated) pinned-photodiode (paras. 0050, 0060, 0084-0087; “The pinned photodiode PPD comprises regions PPD_P, PPD_N in a semiconductor material 10”).
Regarding claim 16, Wang teaches A
one or more active pixels (Figs. 8A), wherein each of the one or more active pixels comprises:
same features as claimed in claim 1 (rejected for the same reasons in claim 1 by the combination of Wang, Kenichi and Mehta).
Regarding claim 18, the combination of Wang, Kenichi and Mehta teaches everything as claimed in claim 16. In addition, Mehta teaches further comprising:
a capacitor (431) operatively coupled to the second floating diffusion node (Fig. 5A; paras. 0081, 0105-0115).
Therefore, it would have been obvious to one of ordinary skill in this art before the effective filing date of the claimed invention (AIA ) to use the teachings as taught by Mehta in the combination to have a capacitor operatively coupled to the second floating diffusion node for allowing the image signal to be properly read enabling the DVS imaging system to optimally convert to digital signals yielding a predicted result.
Regarding claim 21, the combination of Wang, Kenichi and Mehta teaches everything as claimed in claim 1. In addition, Wang teaches wherein a second transistor (RST1 or RST) for pixel resetting operatively coupled to the first floating diffusion node and the second floating diffusion node (Figs. 11-12, 23-24).
Regarding claim 22, the combination of Wang, Kenichi and Mehta teaches everything as claimed in claim 16. In addition, Wang teaches wherein a second transistor (RST1 or RST) for pixel resetting operatively coupled to the first floating diffusion node and the second floating diffusion node (Figs. 11-12, 23-24).
Regarding claim 23, the combination of Wang, Kenichi and Mehta teaches everything as claimed in claim 1. In addition, Wang teaches wherein the second floating diffusion node (FD2) includes a drain node (of TX2, SH or RST) (Figs. 23-24).
Regarding claim 24, the combination of Wang, Kenichi and Mehta teaches everything as claimed in claim 1. In addition, Wang wherein the source follower (SF) includes a voltage node (VDD) to dump accumulated photo charge (Figs. 23-24; when RST is ON, dump photo charge in FD2 into VDD; when RST and SH are ON, dump photo charges in FD1 and FD2 into VDD).
Claims 8 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al (US 20120002089 A1) in views of Kenichi (US 20100237390 A1) and Mehta et al (US 20210168314 A1) as applied to claim 7 or 16 above, and further in view of Oh et al (US 20140252437 A1).
Regarding claim 8, the combination of Wang, Kenichi and Mehta teaches everything as claimed in claim 7. In addition, Wang teaches wherein the third transfer transistor and the fourth transfer transistor are located on the second side of the second photodiode (Figs. 8A, 23, 24, 27; TX1 and TX2 of another PPD has the same structure as in claim 1),
but fails to teach
wherein a direction of the electron drift current within the first photodiode is opposite of a direction of the electron drift current within the second photodiode.
However, in the same field of endeavor Oh teaches
wherein a direction (D1 of PD1) of the electron drift current within the first photodiode is opposite of a direction (D2 of PD2) of the electron drift current within the second photodiode (Figs. 33, 1-8; paras. 0087-0090, 0096).
Therefore, it would have been obvious to one of ordinary skill in this art before the effective filing date of the claimed invention (AIA ) to use the teachings as taught by Oh in the combination to have wherein a direction of the electron drift current within the first photodiode is opposite of a direction of the electron drift current within the second photodiode for enabling controlled charge drift toward multiple storages from each photodiode to allow faster complete charge transfer of pixels in the pixel array yielding a predicted result.
Regarding claim 19, the combination of Wang, Kenichi and Mehta teaches everything as claimed in claim 16. In addition, Wang teaches
wherein the first transfer transistor and the second transfer transistor are located on the same side of a corresponding active pixel (Fig. 8A; both TXA and TXB are on the same outer side of a corresponding PPD).
Or, in the alternative, fails to teach
wherein the first transfer transistor and the second transfer transistor are located on the same side of a corresponding active pixel.
However, in the same field of endeavor Oh teaches
wherein the first transfer transistor and the second transfer transistor are located on the same side of a corresponding active pixel (Figs. 1, 8, 26).
Therefore, it would have been obvious to one of ordinary skill in this art before the effective filing date of the claimed invention (AIA ) to use the teachings as taught by Oh in the combination to have wherein an electron flow that corresponding to the electron drift current is directed from a first side of each of the one or more active pixels to a second side of each of the one or more active pixels; and wherein the first transfer transistor and the second transfer transistor are located on the same side of a corresponding active pixel for providing different pixel configuration optimizing pixel transfer performance yielding a predicted result.
Regarding claim 20, the combination of Wang, Kenichi and Mehta teaches everything as claimed in claim 16, but fails to teach
wherein a time of flight (ToF) measurement is determined using the one or more active pixels.
However, in the same field of endeavorOh teaches
wherein a time of flight (ToF) measurement is determined using the one or more active pixels (Fig. 31; para. 0095).
Therefore, it would have been obvious to one of ordinary skill in this art before the effective filing date of the claimed invention (AIA ) to use the teachings as taught by Oh in the combination to have wherein a time of flight (ToF) measurement is determined using the one or more active pixels for enabling depth detection allowing capturing 3D image capability yielding a predicted result.
Additional Rejections
Ma et al (US 20210203869 A1) teaches a back-side-illuminated (BSI) image sensor pixel that includes a pinned photodiode (PPD) (para. 0003) which can be combined to address the limitation “backside illumination pinned-photodiode” as claimed in claim 15 for allowing more light to reach photodiode improving low-light performance yielding a predicted result.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Quan Pham whose telephone number is (571)272-4438. The examiner can normally be reached Mon-Fri 9am-7pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sinh Tran can be reached at (571) 272-7564. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Quan Pham/Primary Examiner, Art Unit 2637
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