DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on July 9, 2026 has been entered.
Response to Amendment
The amendment filed July 9, 2026 has been entered. Claims 15-20 and 24-27 remain pending in the application. Applicant' s amendments to the Claims have overcome each and every 101 rejections previously set forth in the Final Office Action mailed April 13, 2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 15-16, 18-20, and 24-27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 11748615 B1) in view of Izadi (WO 2020023483 A1).
Regarding Claims 15 and 25-26, Wu teaches A method comprising (Wu: Abstract; Col. 8, lines 49-61): A device for operating at least one part of an artificial neural network on a hardware accelerator using a result of a neural architecture search, the device comprising one or more processors configured to (Wu: Abstract; Col. 2, lines 16-28; Col. 8, lines 49-61): A non-transitory computer-readable medium on which is stored a computer program including computer-readable instructions for operating at least one part of an artificial neural network on a hardware accelerator using a result of a neural network search, the instruction, when executed by a computer, causing the computer to perform the following steps (Wu: Abstract; 2/16-28; Col. 8, lines 49-61):
providing a first set of values for parameters that define at least one part of a first architecture for an artificial neural network, the at least one part of the first architecture encompassing a plurality of layers of the artificial neural network and a plurality of operations of the artificial neural network (Wu: Abstract; 4/65 ~ 5/18 teach(es) The DNAS engine is configured with a stochastic super net defining a layer-wise search space having a plurality of candidate layers, each of the candidate layers specifying one or more operators for a neural network architecture; neural network model generation system receives, via user interface, various input parameters, such as data specifying a set of one or more desired target devices for which to generate neural network models);
determining a first value of a hardware-conscious cost function, wherein:
the hardware-conscious cost function is representative of a time-dependent hardware property of the hardware accelerator during execution of a task, including at least one of a latency, an energy consumed per period of time, a performance, or a memory bandwidth (Wu: 1/43-55, 6/1-11, 8/49-61 teach(es) the optimality of convolutional neural networks is often conditioned upon many factors, such as input resolution and target hardware devices; differentiable neural architecture search (DNAS) is used to identify and construct hardware-aware efficient neural networks, such as convolutional neural networks; The loss function reflects not only the accuracy of a given architecture but also the latency on the target hardware of target devices);
the first value characterizes the hardware property of the hardware accelerator when the hardware accelerator executes the task for the at least one part of the artificial neural network that is defined by the first set of values for the parameters; and
a first data point of the hardware-conscious cost function is defined by the first set of values for the parameters and the first value of the hardware-conscious cost function (Wu: Abstract; 1/56-67; 4/65 ~ 5/18, 1/43-55, 6/1-11, 8/49-61 teach(es) The DNAS engine is configured with a stochastic super net defining a layer-wise search space having a plurality of candidate layers, each of the candidate layers specifying one or more operators for a neural network architecture; the DNAS engine is configured to process training data to train weights for the operators in the stochastic super net based on a loss function representing a latency of the respective operator on a target platform, and to select a set of candidate neural network architectures from the trained stochastic super net; neural network model generation system receives, via user interface, various input parameters, such as data specifying a set of one or more desired target devices for which to generate neural network models);
determining a gradient of the hardware-conscious cost function between the first data point and each of at least two additional data points of the hardware-conscious cost function; determining which one of the at least two additional data points has a greater gradient (Wu: Abstract; 1/56 ~ 2/4; 5/37-55; 6/12-30, 1/43-55, 6/1-11, 8/49-61 teach(es) The DNAS engine may, for example, be configured to train the stochastic super net by traversing the layer-wise search space using gradient-based optimization of network architecture distribution; during operation of DNAS engine, the architecture of the distribution may be trained during the search process using gradient-based optimization search, such as stochastic gradient descent (SGD), such that the constructed neural net need not be trained after selecting and prior to deployment to target devices);
selecting as a second data point of the hardware-conscious cost function the one of the at least two additional data points that has the greater gradient with respect to the first data point, wherein the second data point of the hardware-conscious cost function is defined by a second set of values for the parameters that define at least one part of a second architecture for the artificial neural network (Wu: Abstract; 4/65 ~ 5/18; 1/43-55, 6/1-11, 8/49-61 teach(es) The DNAS engine is configured with a stochastic super net defining a layer-wise search space having a plurality of candidate layers, each of the candidate layers specifying one or more operators for a neural network architecture; neural network model generation system receives, via user interface, various input parameters, such as data specifying a set of one or more desired target devices for which to generate neural network models; The loss function reflects not only the accuracy of a given architecture but also the latency on the target hardware of target devices) a second value of the hardware-conscious cost function, the second value characterizing an additional time-dependent hardware property of the hardware accelerator when the hardware accelerator executes the task for the at least one part of the artificial neural network that is defined by the second set of values for the parameters (Wu: Abstract; 1/56-67; 1/43-55, 6/1-11, 8/49-61 teach(es) The DNAS engine is configured with a stochastic super net defining a layer-wise search space having a plurality of candidate layers, each of the candidate layers specifying one or more operators for a neural network architecture; the DNAS engine is configured to process training data to train weights for the operators in the stochastic super net based on a loss function representing a latency of the respective operator on a target platform, and to select a set of candidate neural network architectures from the trained stochastic super net; The loss function reflects not only the accuracy of a given architecture but also the latency on the target hardware of target devices);
…, wherein the … data point is defined by a … set of values for the parameters and a … value of the hardware-conscious cost function (Wu: 4/65 ~ 5/18, 1/43-55, 6/1-11, 8/49-61 teach(es) neural network model generation system receives, via user interface, various input parameters, such as data specifying a set of one or more desired target devices for which to generate neural network models);
determining, from the first, second, and …, a data point for which a value of the hardware-conscious cost function of the data point satisfies a condition, the data point defining a result of a neural architecture search (Wu: Wu: 5/37-55; 6/12-30; 1/43-55, 6/1-11, 8/49-61 teach(es) during operation of DNAS engine, the architecture of the distribution may be trained during the search process using gradient-based optimization search, such as stochastic gradient descent (SGD), such that the constructed neural net need not be trained after selecting and prior to deployment to target devices; The loss function reflects not only the accuracy of a given architecture but also the latency on the target hardware of target devices));
when the determined data point is the first data point, operating the at least one part of the first architecture for the artificial neural network on the hardware accelerator based on the first set of values for the parameters; when the determined data point is the second data point, operating the at least one part of the second architecture for the artificial neural network on the hardware accelerator based on the second set of values for the parameters; and when the determined data point is the third data point, operating at least one part of a third architecture for the artificial neural network on the hardware accelerator based on the third set of values for the parameters (Wu: 4/65 ~ 5/18; 8/49-61; 10/58-61; 3/6-25; 5/56-67 teach(es) neural network model generation system receives, via user interface, various input parameters, such as data specifying a set of one or more desired target devices for which to generate neural network models. User may also, for example, specify for each desired target device data characterizing performance characteristics for each convolutional neural network operation with respect to each device, such as the actual or expected latency of executing each operation on the respective device; The loss function reflects not only the accuracy of a given architecture but also the latency on the target hardware of target devices; The loss function reflects not only the accuracy of a given architecture but also the latency on the target hardware of target devices; the optimality of convolutional neural network architectures is conditioned on many factors such as input resolution and target devices; DNAS engine may obtain one or more optimal neural net architectures (models) by sampling from the architecture distribution generated during the training process).
However, Wu does not explicitly teach determining a third data point of the hardware-conscious cost function using an interpolation between the first data point and the second data point.
Izadi from same or similar field of endeavor teaches determining a third data point of the hardware-conscious cost function using an interpolation between the first data point and the second data point (Izadi: Paragraph(s) 0063, 0103 teach(es) the latent parameters parameterize the conditional layer weights by one or more B-splines. A B-spline (or basis spline) is a piecewise polynomial parametric function with bounded support and a specified level of smoothness up to Cd , where d is the degree of the B-spline, that approximately interpolates a set of control points (“knots”); Data processing apparatus for implementing machine learning models can also include, for example, special-purpose hardware accelerator units for processing common and compute intensive parts of machine learning training or production, i.e., inference, workloads).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Wu to incorporate the teachings of Izadi for determining a third data point of the hardware-conscious cost function using an interpolation between the first data point and the second data point.
There is motivation to combine Izadi into Wu because Izadi’s teachings of interpolation would facilitate splining of data points having a specified level of smoothness (Izadi: Paragraph(s) 0063).
Regarding Claim 16, the combination of Wu and Izadi teaches all the limitations of claim 15 above; and Wu further teaches wherein the first value of the hardware-conscious cost function is determined by acquiring the hardware property of the hardware accelerator on the hardware accelerator (Wu: Abstract; 1/56 ~ 2/4; 1/43-55, 6/1-11, 8/49-61 teach(es) The DNAS engine is configured with a stochastic super net defining a layer-wise search space having a plurality of candidate layers, each of the candidate layers specifying one or more operators for a neural network architecture; the DNAS engine is configured to process training data to train weights for the operators in the stochastic super net based on a loss function representing a latency of the respective operator on a target platform, and to select a set of candidate neural network architectures from the trained stochastic super net; The loss function reflects not only the accuracy of a given architecture but also the latency on the target hardware of target devices).
Regarding Claim 18, the combination of Wu and Izadi teaches all the limitations of claim 16 above; and Wu further teaches wherein the hardware property is a latency, the latency being a duration of a computing time, a performance, or energy consumed per period of time, or a memory bandwidth (Wu: 3/26-36 teach(es) a differentiable neural architecture search (DNAS) engine that uses, in some examples, gradient-based optimization to search for architectures from a discrete combinatorial space and directly optimizes for actual/expected characteristics for target devices, such as latency per each type of neural network operation and/or power or energy consumption per type of operation).
Regarding Claim 19, the combination of Wu and Izadi teaches all the limitations of claim 15 above; and Wu further teaches wherein one of the parameters defines: a size of a synapse or neuron or filter in the artificial neural network, and/or a number of filters in the artificial neural network, and/or a number of layers of the artificial neural network that are combined in a task which can be executed by the hardware accelerator without part-results of the task being transferred into or from a memory that is external to the hardware accelerator (Wu: 7/24-40; 8/49-61 teach(es) The macro architecture may be viewed as configuration data defining the search space of super net for use by NN model generation system when constructing the super net and defines the number of layers and the input/output dimensions of each layer. In this example, the first and the last three layers of the network have fixed operators. For the rest of the layers, their block type needs to be searched. The filter numbers for each layer are hand-picked empirically; The loss function reflects not only the accuracy of a given architecture but also the latency on the target hardware of target devices).
Regarding Claim 20, the combination of Wu and Izadi teaches all the limitations of claim 15 above; however the combination does not explicitly teach the method further comprising: determining a measure of similarity between the first data point and each of at least two further data points of the function; determining which one of the at least two further data points has a measure of similarity with the first data point that satisfies a condition; and selecting as a fourth data point of the function the one of the at least two further data points that has the measure of similarity with the first data point that satisfies the condition, wherein the fourth data point of the function is defined by a fourth set of values for the parameters and a fourth value of the function.
Izadi further teaches the method further comprising:
determining a measure of similarity between the first data point and each of at least two further data points of the hardware-conscious cost function; determining which one of the at least two further data points has a measure of similarity with the first data point that satisfies a condition; and selecting as a fourth data point of the hardware-conscious cost function the one of the at least two further data points that has the measure of similarity with the first data point that satisfies the condition, wherein the fourth data point of the hardware-conscious cost function is defined by a fourth set of values for the parameters and a fourth value of the hardware-conscious cost function (Izadi: Paragraph(s) 0081-0082, 0063, 0103 teach(es) the objective function characterizes the accuracy of the network outputs generated by the neural network by measuring a similarity between the network outputs and the corresponding target outputs specified by the training examples, e.g., using a cross-entropy loss term or a squared-error loss term; the latent parameters parameterize the conditional layer weights by one or more B-splines. A B-spline (or basis spline) is a piecewise polynomial parametric function with bounded support and a specified level of smoothness up to Cd , where d is the degree of the B-spline, that approximately interpolates a set of control points (“knots”); Data processing apparatus for implementing machine learning models can also include, for example, special-purpose hardware accelerator units for processing common and compute intensive parts of machine learning training or production, i.e., inference, workloads).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of the combination of Wu and Izadi to incorporate the teachings of Izadi for wherein for the method further comprising: determining a measure of similarity between the first data point and each of at least two further data points of the function; determining which one of the at least two further data points has a measure of similarity with the first data point that satisfies a condition; and selecting as a fourth data point of the function the one of the at least two further data points that has the measure of similarity with the first data point that satisfies the condition, wherein the fourth data point of the function is defined by a fourth set of values for the parameters and a fourth value of the function.
There is motivation to combine Izadi into the combination of Wu and Izadi because Izadi’s teachings of measuring a similarity and interpolation would facilitate characterizing the accuracy of the network outputs generated by the neural network (Izadi: Paragraph(s) 0081-0082, 0063).
Regarding Claim 24, the combination of Wu and Izadi teaches all the limitations of claim 15 above; and Wu further teaches wherein a further value for a further parameter of the artificial neural network is determined independently of the hardware-conscious cost function, and the architecture of the artificial neural network is determined based on the further value (Wu: 4/65 ~ 5/18, 1/43-55, 6/1-11, 8/49-61 teach(es) neural network model generation system receives, via user interface 38, various input parameters, such as data specifying a set of one or more desired target devices for which to generate neural network models).
Regarding Claim 27, the combination of Wu and Izadi teaches all the limitations of claim 20 above; and the combination further teaches further comprising determining a fifth data point of the hardware-conscious cost function using an interpolation between the first data point and the fourth data point, wherein the fifth data point is defined by a fifth set of values for the parameters and a fifth value of the hardware-conscious cost function (Wu: 4/65 ~ 5/18, 1/43-55, 6/1-11, 8/49-61; Izadi: Paragraph(s) 0063, 0103 as stated above with respect to claim 15).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 11748615 B1) in view of Izadi (WO 2020023483 A1), as applied to claim 15, and in further view of Zhou (US 20190354837 A1).
Regarding Claim 17, the combination of Wu and Izadi teaches all the limitations of claim 15 and hardware accelerator above; however the combination does not explicitly teach wherein the first value of the [hardware-conscious cost] function is determined by determining the [hardware] property of the hardware accelerator in a simulation of the hardware accelerator.
Zhou from same or similar field of endeavor teaches wherein the first value for the [hardware-conscious cost] function is determined by determining the [hardware] property of the hardware accelerator in a simulation of the hardware accelerator (Zhou: 0045, 0086-0088 teach(es) FIG. 1 shows a high-level depiction of a resource-efficient neural architect (RENA), according to embodiments of the present disclosure. As shown in FIG. 1, in one or more embodiments, a RENA embodiment may comprise two principal networks: a policy network and a value network (or a performance simulation network); a performance simulation network takes a target network embedding and a training dataset in terms of size, distribution, and regularity to generate approximated accuracy and training time).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of the combination of Wu and Izadi to incorporate the teachings of Zhou for wherein the first value for the hardware-conscious cost function is determined by determining the hardware property of the hardware accelerator in a simulation of the hardware accelerator.
There is motivation to combine Zhou into the combination of Wu and Izadi because Zhou’s teachings of performance simulation network would facilitate providing a resource-efficient neural architect (Zhou: Paragraph(s) 0045, 0086-0088).
Response to Arguments
Applicant's arguments filed July 9, 2026 have been fully considered but they are not persuasive.
Regarding applicant’s argument under Claim Rejections - 35 USC § 103 that “Wu does not compute gradients between discrete data points of a hardware-conscious cost function, compare those gradient values against each other, or select a data point based on which has the greater gradient, as the amended claims require”, “Neither Wu nor Izadi discloses "determining a third data point of the hardware-conscious cost function using an interpolation between the first data point and the second data point, wherein the third data point is defined by a third set of values for the parameters and a third value of the hardware-conscious cost function," as recited in amended claim 15”, and “Wu does not conditionally operate one of three different architectures on a hardware accelerator based on which of three data points of a hardware-conscious cost function satisfies a condition”, examiner respectfully argues that the claims do not recite and define any technical details and contexts of parameters, first value of a function, a property of hardware accelerator, task, gradient of the function, etc., enough to differentiate the claim languages from the teachings of the combination of cited references.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kristensen (US 20210286923 A1) teaches Sensor Simulation And Learning Sensor Models With Generative Machine Learning Methods, inculding hardware acceleration, bandwidth, latency, and architecture.
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/CLAY C LEE/Primary Examiner, Art Unit 3699
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