Status of Claims
In the communication filed on 12/10/2025, claims 1, 8-10, and 14 are pending. Claims 1, 10, and 14 are amended. No claims are new. Claims 2-7 and 11-13 are presently cancelled.
Response to Arguments
The prior objections to the Drawings and Claims are withdrawn due to the amendments.
The prior rejections under U.S.C. 112(b) are withdrawn due to the amendments.
Applicant’s arguments with respect to claims 1, 8-10, and 14 have been considered but are moot because the arguments do not apply to the combination of references being used in the current rejection.
Independent claim 1 is amended to incorporate the subject matter of original dependent claims 2-7, with scope changes to require the plurality of sub-modules (rather than a single sub-module) to be controlled in each of the passive charge mode, active charge mode, and normal operation mode. Independent claims 10 and 14 are each amended to incorporate new subject matter that changes the scope of the claims. Thus, due to the applicant’s change of scope of the independent claims, this final rejection is proper.
Claim Objections
Claim 10 is objected to because of the following informalities:
Claim 10, line 17 recites “the initial charging method of the modular multi-level converter, comprising:”. It is suggested to revise this language to “wherein the initial charging method comprises:”.
In claim 10, line 41, “a differential input voltage” should be revised to “[[a]] the differential input voltage” because this was introduced prior in the claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 8-10, and 14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, lines 1-6 are indefinite as to whether the “modular multi-level converter” comprises “a sub-module control unit” (assumed for examination), or, alternatively, “each of the plurality of sub-modules” includes “a sub-module control unit”.
Claims 8-9 recite “the converter of claim 1” and “the converter of claim 8”, which have insufficient antecedent basis. It is suggested to revise the language to that of claim 1, using “the modular multi-level converter”.
Claim 10, line 25 recites “the capacitor”. This language is unclear as to which capacitor is being referenced. For examination purposes, it is assumed this limitation is referring to each of the plurality of capacitors.
Claim 14, line 12 recites “a passive charge mode controlling the sub-module”. This language is unclear as to which sub-module is being referenced. For examination purposes, it is assumed this language is referring to each sub-module in each of the “first upper sub-module arm”, “first lower sub-module arm”, “second upper sub-module arm”, and “second lower sub-module arm”.
Claim 14, lines 16-17 recite “a part of the sub-modules within the first upper sub-module arm and the first lower sub-module arm”. However, only a single sub-module was introduced prior in each arm (claim 14, lines 3-4). Thus, the language is indefinite as to the plurality of the sub-module(s) in each arm. For examination purposes, it is assumed the “first upper sub-module arm” and the “first lower sub-module arm” each includes a plurality of sub-modules.
Claim 14, lines 24-25 recite “a part of the sub-modules within the second upper sub-module arm and the second lower sub-module arm”. However, only a single sub-module was introduced prior in each arm (claim 14, lines 3-4). Thus, the language is indefinite as to the plurality of the sub-module(s) in each arm. For examination purposes, it is assumed the “second upper sub-module arm” and the “second lower sub-module arm” each includes a plurality of sub-modules.
Claim 14, in the second last line, recites “the first active charging mode”, which has insufficient antecedent basis. It is suggested to revise the language to that of prior in the claim, which uses “first active charge mode”.
Claim Rejections - 35 USC § 103
Claims 1 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Outram (EP 3609069 A1) in view of Zhang’s IEEE article (L. Zhang et al., “A Generalized Precharging Strategy for Soft Startup Process of the Modular Multilevel Converter-Based HVDC Systems”, 08/07/2017, IEEE Transactions on Industry Applications, Vol. 53, No. 6, November/December 2017, pp. 5645-5657) (hereinafter “Zhang”).
NOTE: As of the current date, the Zhang article is available at the following link:
https://ieeexplore.ieee.org/document/8003320?source=IQplus
Regarding Claim 1, Outram discloses a modular multi-level converter (“voltage-source converter (VSC) 100”; Fig. 1; ¶ [1]: “a Modular Multilevel Converter (MMC)”), comprising the following features.
Outram further discloses a plurality of sub-modules (“sub-module 102”; see annotated Fig. 2, included infra), each of the plurality of sub-modules including a capacitor (202) and performing charging and discharging of an alternating current power (“202” gets charged and discharged with power from the AC power interface of Fig. 1).
Outram further discloses a sub-module control unit (“controller” including “104, 103a, 103b, 206” per Abstract section (57); ¶ [68]) controlling charging (Figs. 4(d) + 4(e) show charging path through first diode “204”; ¶ [7]: “charging the capacitors”), discharging (Fig. 4(k) shows discharging path through IGBT1 “201”; ¶ [7]: “discharging the capacitors”), and bypassing (Figs. 4(h) + 4(j) show bypassing path through second diode “205”; Fig. 4(c) shows bypassing path through IGBT2 “203”; ¶ [4]: “bypassing the capacitor”) of the capacitor (202).
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Outram further discloses the sub-module control unit (104, 103a, 103b, 206) controls the plurality of sub-modules (102) to an on state (IGBT1 “201” is controlled on and IGBT2 “203” is controlled off; Figs. 4(a), 4(e), 4(f), 4(k)), an off state (IGBT1 “201” is controlled off and IGBT2 “203” is controlled on; Figs. 4(c) + 4(h)), and a block state (both IGBT1 and IGBT2 controlled off; “dead band” shown in Figs. 4(b), 4(d), 4(g), 4(j)).
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Outram further discloses the sub-module control unit (104, 103a, 103b, 206) controls these states so as to perform a normal operation mode (Fig. 5 shows switching sequence for normal operation).
Outram further discloses in the normal operation mode (Fig. 5), the sub-module control unit (104, 103a, 103b, 206) controls the plurality of sub-modules (102) to the on state (IGBT1 “201” is controlled on and IGBT2 “203” is controlled off; Figs. 4(e) + 4(k)) or the off state (IGBT1 “201” is controlled off and IGBT2 “203” is controlled on; Figs. 4(c) + 4(h)) and independently (each “206” is dedicated to a single sub-module “102”) performs charging (Fig. 4(e)) and discharging (Fig. 4(k)) the sub-modules (102) included in the arm (“valve 101a”; Fig. 1).
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Outram further discloses each of the plurality of sub-modules (102) comprises the following features.
Outram further discloses the capacitor (202) storing the alternating current power (“AC” in Fig. 1). Outram further discloses a first diode (204) providing a charging path (Figs. 4(d) + 4(e) show current path through “204” to charge “202”) to the capacitor (202).
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Outram further discloses a first insulated gate bipolar transistor (IGBT1) (201) providing a discharging path (Fig. 4(k) shows current path through “201” to discharge “202”) of the capacitor (202) by the control (¶ [68]) of the sub-module control unit (206).
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Outram further discloses a second diode (205) providing a bypassing path (Figs. 4(h) + 4(j) show current path through “205” to bypass “202”) of each of the plurality of sub-modules (102).
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Outram further discloses a second insulated gate bipolar transistor (IGBT2) (203) providing the bypassing path (Fig. 4(c) shows current path through IGBT2 “203” to bypass “202”) of each of the plurality of sub-modules (102) by the control (¶ [68]) of the sub-module control unit (206).
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Outram further discloses in the on state (IGBT1 “201” is controlled on and IGBT2 “203” is controlled off, as shown in Figs. 4(a), 4(e), 4(f), 4(k); see annotated Fig. 4, included supra), the sub-module control unit (104, 103a, 103b, 206) controls the IGBT1 (201) to be turned on and the IGBT2 (203) to be turned off.
Outram further discloses that in the on state, during a section where a positive input voltage of each of the plurality of sub-modules is higher than a negative input voltage (section of the on state is depicted in Figs. 4(a) + 4(e); see “P” and “N” input nodes labelled in annotated Figs. 2, 4) of each of the plurality of sub-modules, a differential input voltage between the positive input voltage and the negative input voltage is stored in the capacitor (202) through the first diode (Figs. 4(a) + 4(e) show charging current through first diode “204” to charge the capacitor “202” with the differential voltage VPN).
Outram further discloses that in the on state, during a section where the positive input voltage is lower than the negative input voltage (section of the on state is depicted in Figs. 4(f) + 4(k)), a power being stored in the capacitor (202) is discharged (Figs. 4(f) + 4(k) show discharging current through IGBT1 “201”) due to an input (command signal to turn on IGBT1 “201”) of each of the plurality of sub-modules (102).
Outram further discloses in the off state (IGBT1 “201” is controlled off and IGBT2 “203” is controlled on, as shown in Figs. 4(c) + 4(h); see annotated Fig. 4, included supra), the sub-module control unit (104, 103a, 103b, 206) controls the IGBT1 (201) to be turned off and the IGBT2 (203) to be turned on, thereby bypassing (Figs. 4(c) shows current bypassing through IGBT2 “203”; Fig. 4(h) shows current bypassing through the second diode “205”) the positive input voltage and the negative input voltage (see “P” and “N” input nodes labelled in annotated Figs. 2, 4).
Outram further discloses in the block state (both IGBT1 “201” and IGBT2 “203” controlled off; “dead band” shown in Figs. 4(b), 4(d), 4(g), 4(j); see annotated Fig. 4, included supra), the sub-module control unit (104, 103a, 103b, 206) controls both the IGBT1 (201) and the IGBT2 (203) to be turned off.
Outram further discloses that in the block state, during the section where the positive input voltage of the sub-module is higher than the negative input voltage (section of the block state is depicted in Figs. 4(b) + 4(d); see “P” and “N” input nodes labelled in annotated Figs. 2, 4), the differential input voltage between the positive input voltage and the negative input voltage is stored in the capacitor (202) through the first diode (Figs. 4(b) + 4(d) show charging current through first diode “204” to charge the capacitor “202” with the differential voltage VPN).
Outram further discloses that in the block state, during the section where the positive input voltage of the sub-module is lower than the negative input voltage (section of the block state is depicted in Figs. 4(g) + 4(j)), the positive input voltage and the negative input voltage are bypassed (Figs. 4(g) + 4(j) show current bypassing through the second diode “205”).
Though Outram discloses the normal operation mode, Outram does not disclose “to sequentially perform a passive charge mode, an active charge mode, and a normal operation mode, thereby initializing the plurality of sub-modules,
Outram further does not disclose “wherein, in the passive charge mode, the sub-module control unit controls the plurality of sub-modules to the block state and performs charging of sub-modules included in an arm among the plurality of sub-modules, wherein, in the active charge mode, the sub-module control unit controls the plurality of sub-modules to the off state or the block state and performs charging of only a part of the submodules included in the arm, wherein in the normal operation mode, the sub-module control unit controls the plurality of sub-modules to the on state or the off state and independently performs charging and discharging the sub-modules included in the arm”.
Zhang teaches to sequentially perform a passive charge mode (“uncontrollable precharging (Stage I)”; page 5646, section II) and an active charge mode (“controllable precharging (Stage II)”; page 5646, section II), and a normal operation mode (mode during period after 2.5 seconds in Fig. 13 in which three-phase AC output current is conducted as part of the “high-voltage dc (HVdc) transmission system” described in Abstract and Introduction; see annotated Fig. 13, included infra), thereby initializing (“precharging”) the plurality of sub-modules (SM1-N; see annotated Fig. 1, included infra).
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Zhang further teaches that, in the passive charge mode (“uncontrollable precharging (stage I)”), the control strategy controls the plurality of sub-modules (SM1-N) to the block state (page 5646, section II: “SMs are not controllable and all the switches are blocked”; per Fig. 2, both switches “S1” and “S2” are in off-state for “blocked SM capacitor state”) and performs charging (page 5646, section II: “charging current … flows through the antiparallel diodes to charge the SM capacitors to an uncontrollable steady state voltage VCI,SS”) of sub-modules (SM1-N) included in an arm (page 5646, section II: “two arms per phase, where each arm comprises N series-connected, nominally identical, HB SMs”) among the plurality of sub-modules (SM1-N).
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Zhang further teaches (see annotated Fig. 3, included infra) that, in the active charge mode (“controllable precharging (stage II)”), the control strategy controls the plurality of sub-modules (SM1-N) to the off state (subset are “bypassed”) or the block state (others are “blocked”) and performs charging of only a part (Fig. 4: “Block NBLK SM capacitors with lowest voltages”) of the submodules (SM1-N) included in the arm (page 5647: “NC is the total number of SM capacitors in each arm”).
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NOTE: Though Zhang teaches a control strategy to control the initial charging sequence, Zhang does not explicitly teach this control strategy and associated algorithms being executed by a sub-module control unit. However, it would have been obvious to one of ordinary skill in the art that the prior-introduced sub-module control unit disclosed by Outram is capable of executing algorithms and control strategies to control sub-modules. Thus, one of ordinary skill in the art would understand that the control strategy taught by Zhang is an applicable teaching to potentially incorporate in the sub-module control unit disclosed by Outram.
Zhang further teaches this sequence of a passive charge mode and an active charge mode prior to normal operation to ensure smooth pre-charging of the capacitors in the modular multi-level converter and limit inrush currents without the need for additional measurements and/or auxiliary power supplies (page 5645, Abstract; page 5656, section VIII: “Conclusion”).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the sub-module control unit disclosed by Outram to control the sub-modules to sequentially perform a passive charge mode and an active charge mode prior to the normal operation mode, as taught by Zhang, to limit inrush currents on start-up without requiring additional equipment.
Regarding Claim 8, the combo of Outram and Zhang discloses the converter of claim 1.
Outram further discloses the arm (“valve 101a”; Fig. 1) includes at least two sub-modules (¶ [49]: “each of the valves 101a … comprises a plurality of sub-modules 102”).
The combination of Outram and Zhang discloses the active charge mode (incorporated from Zhang: “controllable precharging (stage II)”).
Outram does not disclose “wherein, in the active charge mode, voltages charged in the at least two sub-modules are compared, so as to perform bypassing in an order starting from a highest level of charged voltage”.
Zhang further teaches in the active charge mode (“controllable precharging (stage II)”; Figs. 3-4), voltages charged in the at least two sub-modules are compared (capacitor voltages are compared with each other and “VCnom” to sort into “lowest voltages” and “highest voltages” per Fig. 4; comparison is performed by the “capacitor voltage sorting algorithm” described in section II, pages 5646-5647), so as to perform bypassing in an order (order determined by the “capacitor voltage sorting algorithm”; Fig. 13 shows one-by-one decreasing of number of blocking sub-modules, meaning a one-by-one increasing of the number of bypassing sub-modules) starting from a highest level of charged voltage (Fig. 4: “Bypass NC - NBLK SM capacitors with highest voltages”).
Zhang further teaches to control the sub-modules to bypass in an order starting from a highest level of charged voltage to ensure smooth pre-charging of the capacitors in the modular multi-level converter and limit inrush currents without the need for additional measurements and/or auxiliary power supplies (page 5645, Abstract; page 5656, section VIII: “Conclusion”).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the active charge mode disclosed by the combination of Outram and Zhang to control the sub-modules to bypass in an order starting from a highest level of charged voltage, as further taught by Zhang, to limit inrush currents on start-up without requiring additional equipment.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Outram (EP 3609069 A1) in view of Zhang’s IEEE article (L. Zhang et al., “A Generalized Precharging Strategy for Soft Startup Process of the Modular Multilevel Converter-Based HVDC Systems”, 08/07/2017, IEEE Transactions on Industry Applications, Vol. 53, No. 6, November/December 2017, pp. 5645-5657) (hereinafter “Zhang”), and Madawala et al. (US 2015/0288287 A1).
Regarding Claim 9, the combo of Outram and Zhang discloses the converter of claim 8.
Outram further discloses the bypassing (¶ [56] describes the “bypass configuration”; see the “off state” of annotated Figs. 4(c) + 4(h)) is performed by generating a number of charged sub-modules (“number of sub-modules in output state” on vertical axis of Figs. 8-9), the number of charged sub-modules being a number of sub-modules performing charging (¶ [55]: “when the current passes through the energy storage device 202 … considered to be in an output state”; thus, “output state” means the sub-module is performing charging).
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Outram does not disclose “wherein the bypassing is performed by comparing a carrier signal with a reference signal, the carrier signal being autonomously generated by the sub-module control unit”.
Madawala teaches the bypassing (bypassing the capacitor “Crn” voltage “Vc,rn” via turning on the IGBT2 “Srn,B” in the sub-module of Fig. 1b; performed “to address imbalances in the modular multi-level converter (M2LC) such as … voltage differences across the capacitances”) is performed by comparing a carrier signal (¶ [109]: “voltage references, VCMRef,rm, are compared against carrier waveforms to generate pulse patterns for switches S1,rm-S4,rm”) with a reference signal (“voltage references VCMRef,rm”).
Madawala further teaches the carrier signal being autonomously generated (¶ [122]: “VCMs were controlled using the coupled controller … with a carrier frequency of 1 kHz” … “with the M2LC PWM, frequency of the carrier waveforms, in phase disposition, was 750 Hz”) by the sub-module control unit (“coupled controller” per ¶ [106, 109, 122] for sub-module shown in Fig. 1b).
Madawala further teaches the comparison of the carrier signal and the reference signal to achieve a high dynamic performance (¶ [83]), which has numerous advantages including a reduction in power losses from conduction and switching (¶ [85]).
It would have been obvious to one of ordinary skill in the art to modify the bypassing mode disclosed by the combination of Outram and Zhang to incorporate a comparison of a carrier signal and a reference signal, as taught by Madawala, to improve the dynamic performance and reduce power losses from conduction and switching of the IGBTs.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Outram (EP 3609069 A1) in view of Zhang’s IEEE article (L. Zhang et al., “A Generalized Precharging Strategy for Soft Startup Process of the Modular Multilevel Converter-Based HVDC Systems”, 08/07/2017, IEEE Transactions on Industry Applications, Vol. 53, No. 6, November/December 2017, pp. 5645-5657) (hereinafter “Zhang”), and Pang et al. (US 2014/0002048 A1).
Regarding Claim 8, the combo of Outram and Zhang discloses the converter of claim 1.
Outram further discloses the arm (“valve 101a”; Fig. 1) includes at least two sub-modules (¶ [49]: “each of the valves 101a … comprises a plurality of sub-modules 102”).
The combination of Outram and Zhang discloses the active charge mode (incorporated from Zhang: “controllable precharging (stage II)”).
Outram does not disclose “wherein, in the active charge mode, voltages charged in the at least two sub-modules are compared, so as to perform bypassing in an order starting from a highest level of charged voltage”.
Pang teaches voltages charged (voltage “uc” across capacitor of each sub-module; Figs. 1-2) in at least two sub-modules (“SM1 – SMn”; Fig. 3) are compared (¶ [40]: “Find out the highest sub module on output state whose capacitor voltage amplitude is the maximum”), so as to perform bypassing (switch states of Fig. 2 which bypass current through “T2” and “D2”) in an order starting from a highest level of charged voltage (¶ [46]: “the output state of the sub module will be change into bypass state, and bypass the capacitor voltage highest sub module all of sub modules on the output state”; put in other words, the sub-module with the highest capacitor voltage is changed to the bypass state first).
Pang further teaches this comparison of sub-modules’ charged voltages and to start bypassing with the highest voltage sub-module for the advantage of improving the efficiency of the modular multilevel converter (¶ [7]) during voltage balancing by reducing the number of switching actions during voltage balancing (¶ [14]).
It would have been obvious to one of ordinary skill in the art to modify the active charge mode disclosed by the combination of Outram and Zhang to compare sub-modules’ charged voltages and start bypassing with the highest voltage sub-module, as taught by Pang, to improve the efficiency of the modular multilevel converter during the voltage balancing performed during the active charge mode.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Outram (EP 3609069 A1) in view of Zhang’s IEEE article (L. Zhang et al., “A Generalized Precharging Strategy for Soft Startup Process of the Modular Multilevel Converter-Based HVDC Systems”, 08/07/2017, IEEE Transactions on Industry Applications, Vol. 53, No. 6, November/December 2017, pp. 5645-5657) (hereinafter “Zhang”), Pang et al. (US 2014/0002048 A1), and Madawala et al. (US 2015/0288287 A1).
Regarding Claim 9, the combination of Outram, Zhang, and Pang discloses the converter of claim 8.
Outram discloses the bypassing (¶ [56] describes the “bypass configuration”; see the “off state” of annotated Figs. 4(c) + 4(h)) is performed by generating a number of charged sub-modules (“number of sub-modules in output state” on vertical axis of Figs. 8-9), the number of charged sub-modules being a number of sub-modules performing charging (¶ [55]: “when the current passes through the energy storage device 202 … considered to be in an output state”; thus, “output state” means the sub-module is performing charging).
Outram does not disclose “wherein the bypassing is performed by comparing a carrier signal with a reference signal, the carrier signal being autonomously generated by the sub-module control unit”.
Madawala teaches the bypassing (bypassing the capacitor “Crn” voltage “Vc,rn” via turning on the IGBT2 “Srn,B” in the sub-module of Fig. 1b; performed “to address imbalances in the modular multi-level converter (M2LC) such as … voltage differences across the capacitances”) is performed by comparing a carrier signal (¶ [109]: “voltage references, VCMRef,rm, are compared against carrier waveforms to generate pulse patterns for switches S1,rm-S4,rm”) with a reference signal (“voltage references VCMRef,rm”).
Madawala further teaches the carrier signal being autonomously generated (¶ [122]: “VCMs were controlled using the coupled controller … with a carrier frequency of 1 kHz” … “with the M2LC PWM, frequency of the carrier waveforms, in phase disposition, was 750 Hz”) by the sub-module control unit (“coupled controller” per ¶ [106, 109, 122] for sub-module shown in Fig. 1b).
Madawala further teaches the comparison of the carrier signal and the reference signal to achieve a high dynamic performance (¶ [83]), which has numerous advantages including a reduction in power losses from conduction and switching (¶ [85]).
It would have been obvious to one of ordinary skill in the art to modify the bypassing mode disclosed by the combination of Outram, Zhang, and Pang to incorporate a comparison of a carrier signal and a reference signal, as taught by Madawala, to improve the dynamic performance and reduce power losses from conduction and switching of the IGBTs.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Outram (EP 3609069 A1) in view of Zhang’s IEEE article (L. Zhang et al., “A Generalized Precharging Strategy for Soft Startup Process of the Modular Multilevel Converter-Based HVDC Systems”, 08/07/2017, IEEE Transactions on Industry Applications, Vol. 53, No. 6, November/December 2017, pp. 5645-5657) (hereinafter “Zhang”).
Regarding Claim 10, Outram discloses an initial charging method (“commutation” shown in Figs. 4-5; ¶ [73-82] describe the switching method of progressing through the commutation states) of a modular multi-level converter (“voltage-source converter (VSC) 100”; Fig. 1; ¶ [1]: “a Modular Multilevel Converter (MMC)”).
Outram further discloses the modular multi-level converter (100) comprises a plurality of sub-modules (102; see annotated Fig. 2, included supra) being equipped with a capacitor (202) and performing charging and discharging of an alternating current power (“202” gets charged and discharged with power from the AC power interface of Fig. 1).
Outram further discloses the modular multi-level converter (100) further comprises a sub-module control unit (“controller” including “104, 103a, 103b, 206” per Abstract section (57); ¶ [68]) controlling charging (Figs. 4(d) + 4(e) show charging path through first diode “204”; ¶ [7]: “charging the capacitors”), discharging (Fig. 4(k) shows discharging path through IGBT1 “201”; ¶ [7]: “discharging the capacitors”), and bypassing (Figs. 4(h) + 4(j) show bypassing path through second diode “205”; Fig. 4(c) shows bypassing path through IGBT2 “203”; ¶ [4]: “bypassing the capacitor”) of the capacitor (202).
Outram further discloses each of the plurality of sub-modules (102) comprises the following features.
Outram further discloses the capacitor (202) storing the alternating current power (“AC” in Fig. 1).
Outram further discloses a first diode (204) providing a charging path (Figs. 4(d) + 4(e) show current path through “204” to charge “202”) to the capacitor (202).
Outram further discloses a first insulated gate bipolar transistor (IGBT1) (201) providing a discharging path (Fig. 4(k) shows current path through “201” to discharge “202”) of the capacitor (202) by the control (¶ [68]) of the sub-module control unit (206).
Outram further discloses a second diode (205) providing a bypassing path (Figs. 4(h) + 4(j) show current path through “205” to bypass “202”) of each of the plurality of sub-modules (102).
Outram further discloses a second insulated gate bipolar transistor (IGBT2) (203) providing the bypassing path (Fig. 4(c) shows current path through IGBT2 “203” to bypass “202”) of each of the plurality of sub-modules (102) by the control (¶ [68]) of the sub-module control unit (206).
Outram further discloses a normal operating step (Fig. 5 shows switching sequence for normal operation; see annotated Fig. 5, included supra), wherein the sub-module control unit (104, 103a, 103b, 206) controls the plurality of sub-modules (102) to an on state (IGBT1 “201” is controlled on and IGBT2 “203” is controlled off; Figs. 4(e) + 4(k)) or the off state (IGBT1 “201” is controlled off and IGBT2 “203” is controlled on; Figs. 4(c) + 4(h)) and independently (each “206” is dedicated to a single sub-module “102”) performs charging (Fig. 4(e)) and discharging (Fig. 4(k)) of the capacitor (202).
Outram further discloses in the on state (IGBT1 “201” is controlled on and IGBT2 “203” is controlled off, as shown in Figs. 4(a), 4(e), 4(f), 4(k); see annotated Fig. 4, included supra), the sub-module control unit (104, 103a, 103b, 206) controls the IGBT1 (201) to be turned on and the IGBT2 (203) to be turned off.
Outram further discloses that in the on state, during a section where a positive input voltage of each of the plurality of sub-modules is higher than a negative input voltage (section of the on state is depicted in Figs. 4(a) + 4(e); see “P” and “N” input nodes labelled in annotated Figs. 2, 4) of each of the plurality of sub-modules, a differential input voltage between the positive input voltage and the negative input voltage is stored in the capacitor (202) through the first diode (Figs. 4(a) + 4(e) show charging current through first diode “204” to charge the capacitor “202” with the differential voltage VPN).
Outram further discloses that in the on state, during a section where the positive input voltage is lower than the negative input voltage (section of the on state is depicted in Figs. 4(f) + 4(k)), a power being stored in the capacitor (202) is discharged (Figs. 4(f) + 4(k) show discharging current through IGBT1 “201”) due to an input (command signal to turn on IGBT1 “201”) of each of the sub-modules (102).
Outram further discloses in the off state (IGBT1 “201” is controlled off and IGBT2 “203” is controlled on, as shown in Figs. 4(c) + 4(h); see annotated Fig. 4, included supra), the sub-module control unit (104, 103a, 103b, 206) controls the IGBT1 (201) to be turned off and the IGBT2 (203) to be turned on, thereby bypassing (Figs. 4(c) shows current bypassing through IGBT2 “203”; Fig. 4(h) shows current bypassing through the second diode “205”) the positive input voltage and the negative input voltage (see “P” and “N” input nodes labelled in annotated Figs. 2, 4).
Outram further discloses in the block state (both IGBT1 “201” and IGBT2 “203” controlled off; “dead band” shown in Figs. 4(b), 4(d), 4(g), 4(j); see annotated Fig. 4, included supra), the sub-module control unit (104, 103a, 103b, 206) controls both the IGBT1 (201) and the IGBT2 (203) to be turned off.
Outram further discloses that in the block state, during the section where the positive input voltage of the sub-module is higher than the negative input voltage (section of the block state is depicted in Figs. 4(b) + 4(d); see “P” and “N” input nodes labelled in annotated Figs. 2, 4), a differential input voltage between the positive input voltage and the negative input voltage is stored in the capacitor (202) through the first diode (Figs. 4(b) + 4(d) show charging current through first diode “204” to charge the capacitor “202” with the differential voltage VPN).
Outram further discloses that in the block state, during the section where the positive input voltage of the sub-module is lower than the negative input voltage (section of the block state is depicted in Figs. 4(g) + 4(j)), the positive input voltage and the negative input voltage are bypassed (Figs. 4(g) + 4(j) show current bypassing through the second diode “205”).
Outram does not disclose “the initial charging method of the modular multi-level converter, comprising a passive charging step, wherein the sub-module control unit controls the plurality of sub-modules to a block state and performs charging of sub-modules, among the plurality of sub-modules included in an arm; an active charging step, wherein the sub-module control unit controls the plurality of sub-modules to an off state or the block state and performs charging of only a part of the sub-modules included in the arm”.
Though Outram discloses the normal operating step, Outram further does not disclose “wherein the passive charging step, the active charging step, and the normal operating step are sequentially performed”.
Zhang teaches the initial charging method (title: “generalized precharging strategy for … HVDC systems”) of the modular multi-level converter (“modular multilevel converter (MMC); Fig. 1), comprising the following steps.
Zhang further teaches a passive charging step (“uncontrollable precharging (Stage I)”; page 5646, section II), wherein the control strategy controls the plurality of sub-modules (SM1-N) to a block state (page 5646, section II: “SMs are not controllable and all the switches are blocked”; per Fig. 2, both switches “S1” and “S2” are in off-state for “blocked SM capacitor state”) and performs charging (page 5646, section II: “charging current … flows through the antiparallel diodes to charge the SM capacitors to an uncontrollable steady state voltage VCI,SS”) of sub-modules (SM1-N), among the plurality of sub-modules (SM1-N) included in an arm (page 5646, section II: “two arms per phase, where each arm comprises N series-connected, nominally identical, HB SMs”).
Zhang further teaches (see annotated Fig. 3, included supra) an active charging step (“controllable precharging (Stage II)”; page 5646, section II), wherein the control strategy controls the plurality of sub-modules (SM1-N) to an off state (subset are “bypassed”) or the block state (others are “blocked”) and performs charging of only a part (Fig. 4: “Block NBLK SM capacitors with lowest voltages”) of the submodules (SM1-N) included in the arm (page 5647: “NC is the total number of SM capacitors in each arm”).
Zhang further teaches a normal operating step (mode during period after 2.5 seconds in Fig. 13 in which three-phase AC output current is conducted as part of the “high-voltage dc (HVdc) transmission system” described in Abstract and Introduction; see annotated Fig. 13, included supra).
Zhang further teaches the passive charging step (“uncontrollable precharging (Stage I)”; page 5646, section II), the active charging step (“controllable precharging (Stage II)”; page 5646, section II), and the normal operating step (mode during period after 2.5 seconds in Fig. 13 in which three-phase AC output current is conducted as part of the “high-voltage dc (HVdc) transmission system” described in Abstract and Introduction) are sequentially performed (annotated Fig. 13, included supra, shows sequence of the passive charging, then active charging, and then normal operating).
NOTE: Though Zhang teaches a control strategy to control the initial charging sequence, Zhang does not explicitly teach this control strategy and associated algorithms being executed by a sub-module control unit. However, it would have been obvious to one of ordinary skill in the art that the prior-introduced sub-module control unit disclosed by Outram is capable of executing algorithms and control strategies to control sub-modules. Thus, one of ordinary skill in the art would understand that the control strategy taught by Zhang is an applicable teaching to potentially incorporate in the sub-module control unit disclosed by Outram.
Zhang further teaches this sequence of a passive charging step and an active charging step prior to the normal operating step to ensure smooth pre-charging of the capacitors in the modular multi-level converter and limit inrush currents without the need for additional measurements and/or auxiliary power supplies (page 5645, Abstract; page 5656, section VIII: “Conclusion”).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the initial charging method and sub-module control unit disclosed by Outram to control the sub-modules to sequentially perform a passive charging step and an active charging step prior to the normal operating step, as taught by Zhang, to limit inrush currents on start-up without requiring additional equipment.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Outram (EP 3609069 A1) in view of Zhang’s IEEE article (L. Zhang et al., “A Generalized Precharging Strategy for Soft Startup Process of the Modular Multilevel Converter-Based HVDC Systems”, 08/07/2017, IEEE Transactions on Industry Applications, Vol. 53, No. 6, November/December 2017, pp. 5645-5657) (hereinafter “Zhang”).
Regarding Claim 14, Outram discloses a modular multi-level converter (“voltage-source converter (VSC) 100”; ¶ [1]: “a Modular Multilevel Converter (MMC)”; see annotated Fig. 1, included infra), comprising the following features.
Outram further discloses a first upper sub-module arm (“valve 101a”; Fig. 1), a first lower sub-module arm (“valve 101b”; Fig. 1), a second upper sub-module arm (duplicate of “101a” connected to a second AC phase, not drawn), and a second lower sub-module arm (duplicate of “101b” connected to a second AC phase, not drawn).
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Outram further discloses each of the sub-module arms including a sub-module (“sub-module 102”; see annotated Fig. 2, included supra) including a capacitor (202) and performing charging and discharging or an alternating current power (“202” gets charged and discharged with power from the AC power interface of Fig. 1).
Outram further discloses a first normal operation mode (see “normal operating mode” in annotated Fig. 5, included supra) controlling the sub-module (102) included in each of the first upper sub-module arm (101a) and the first lower sub-module arm (101b) to an on state (IGBT1 “201” is controlled on and IGBT2 “203” is controlled off; Figs. 4(e) + 4(k)) or the off state (IGBT1 “201” is controlled off and IGBT2 “203” is controlled on; Figs. 4(c) + 4(h)) and independently (“206” is dedicated to a single sub-module “102”) performing charging (Fig. 4(e)) and discharging (Fig. 4(k)) of the sub-module (102) within the first upper sub-module arm (101a) and the first lower sub-module arm (101b).
Outram further discloses a second normal operation mode (the “first normal operation mode” applicable to the first phase arms “101a” and “101b” is also applied to the second and third phase arms of the “three-phase VSC 100” per ¶ [4, 51, 60-61]; thus, the “second normal operation mode” is the “normal operating mode” of the annotated Fig. 5, applied to the second upper/lower sub-module arms) controlling the sub-module (102) included in each of the second upper sub-module arm (duplicate of “101a” connected to a second AC phase) and the second lower sub-module arm (duplicate of “101b” connected to a second AC phase) to the on state (IGBT1 “201” is controlled on and IGBT2 “203” is controlled off; Figs. 4(e) + 4(k)) or the off state (IGBT1 “201” is controlled off and IGBT2 “203” is controlled on; Figs. 4(c) + 4(h)) and independently (“206” is dedicated to a single sub-module “102”) performing charging (Fig. 4(e)) and discharging (Fig. 4(k)) of the sub-module (102) included in each of the second upper sub-module arm (duplicate of “101a” connected to a second AC phase) and the second lower sub-module arm (duplicate of “101b” connected to a second AC phase).
Outram does not disclose “wherein, for initial charging of the modular multi-level converter, the sub-module control unit is configured to operate in: a passive charge mode controlling the sub-module to a block state and performing only charging of the sub-module; a first active charge mode controlling the sub-module included in each of the first upper sub-module arm and the first lower sub-module arm to an off state or the block state and performing charging of only a part of the sub-modules within the first upper sub-module arm and the first lower sub-module arm”.
Outram further does not disclose “a second active charge mode controlling the sub-module included in each of the second upper sub-module arm and the second lower sub-module arm to the off state or the block state and performing charging of only a part of the sub-modules within the second upper sub-module arm and the second lower sub-module arm”.
Though Outram discloses the first normal operation mode and the second normal operation mode, Outram further does not disclose “the sub-module control unit is configured to operate in the passive charge mode, the first active charging mode, the first normal operation mode, the second active charge mode, and the second normal operation mode sequentially”.
NOTE: In view of the instant application’s disclosure, it is interpreted that the sequential execution of the “first active charging mode” and “first normal operation mode” is intended to be performed concurrently with each of the “second active charging mode” and “second normal operation mode”, respectively. Specification ¶ [84-85] describe the “[first] active charging mode” and the “first normal operation mode”. Then, ¶ [86-87] describe that “[m]eanwhile, …” the “second active charge mode” and the “second normal operation mode” are also being performed. ¶ [88] goes on to refer to this as “sequentially controlling” these operating modes of the two different sets/phases of arms. Further, ¶ [98] again uses “[m]eanwhile” to indicate the concurrency of performing these operating steps on each of these two phases. Thus, it is interpreted that the sequentially-operated modes of actively charging and then normally operating the first phase (“first upper sub-module arm” + “first lower sub-module arm”) are intended to be performed concurrently with the equivalent modes being sequentially performed for the second phase (“second upper sub-module arm” + “second lower sub-module arm”). The examiner interprets “sequentially” to mean “by forming or following a logical order or sequence”. This definition does not require a particular order of the steps in the sequence. This definition does not preclude the concurrent execution of a subset of the steps in the sequence.
Zhang teaches that, for initial charging (“precharging”) of the modular multi-level converter (“MMC”; see annotated Fig. 1, included infra), the control strategy is configured to operate in the following modes.
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Zhang further teaches a passive charge mode (“uncontrollable precharging (Stage I)”; page 5646, section II) controlling the sub-module (SM1-N) to a block state (page 5646, section II: “SMs are not controllable and all the switches are blocked”; per Fig. 2, both switches “S1” and “S2” are in off-state for “blocked SM capacitor state”) and performing only charging (page 5646, section II: “charging current … flows through the antiparallel diodes to charge the SM capacitors to an uncontrollable steady state voltage VCI,SS”) of the sub-module (SM1-N).
Zhang further teaches (see annotated Fig. 3, included supra) a first active charge mode (“controllable precharging (Stage II)”, as applied to the “phase-a” upper and lower arms; page 5646, section II describes “controllable precharging”; page 5654: “[f]or ac-side precharging, … all capacitors in three phases can be charged almost simultaneously”; Fig. 17 shows that all three phases are precharged equivalently and simultaneously) controlling the sub-module (SM1-N) included in each of the first upper sub-module arm (phase-a upper arm; see annotated Fig. 1) and the first lower sub-module arm (phase-a lower arm; see annotated Fig. 1) to an off state (subset are “bypassed”) or the block state (others are “blocked”) and performing charging of only a part (Fig. 4: “Block NBLK SM capacitors with lowest voltages”) of the sub-modules (SM1-N) within the first upper sub-module arm (phase-a upper arm) and the first lower sub-module arm (phase-b lower arm).
Zhang further teaches (see annotated Fig. 3, included supra) a second active charge mode (“controllable precharging (Stage II)”, as applied to the “phase-b” upper and lower arms) controlling the sub-module (SM1-N) included in each of the second upper sub-module arm (phase-b upper arm; see annotated Fig. 1) and the second lower sub-module arm (phase-b lower arm; see annotated Fig. 1) to the off state (subset are “bypassed”) or the block state (others are “blocked”) and performing charging of only a part (Fig. 4: “Block NBLK SM capacitors with lowest voltages”) of the sub-modules (SM1-N) within the second upper sub-module arm (phase-b upper arm) and the second lower sub-module arm (phase-b lower arm).
Zhang further teaches the control strategy is configured to operate in the passive charge mode (“uncontrollable precharging” applied to all phases), the first active charging mode (“controllable precharging” applied to phase-a), the first normal operation mode (“phase-a” operating normally, as shown in period after 2.5 seconds in Fig. 13), the second active charge mode (“controllable precharging” applied to phase-b), and the second normal operation mode (“phase-b” operating normally, as shown in period after 2.5 seconds in Fig. 13) sequentially (first: “uncontrollable precharging (stage I)” applied to all phases; second: “controllable precharging (stage II)” applied to each phase concurrently; third: all phases operating normally).
NOTE: Though Zhang teaches a control strategy to control the initial charging sequence, Zhang does not explicitly teach this control strategy and associated algorithms being executed by a sub-module control unit. However, it would have been obvious to one of ordinary skill in the art that the prior-introduced sub-module control unit disclosed by Outram is capable of executing algorithms and control strategies to control sub-modules. Thus, one of ordinary skill in the art would understand that the control strategy taught by Zhang is an applicable teaching to potentially incorporate in the sub-module control unit disclosed by Outram.
Zhang further teaches this sequence of a passive charge mode and an active charge mode prior to normal operation of each of phase of a multi-phase MMC to ensure smooth pre-charging of the capacitors and limit inrush currents without the need for additional measurements and/or auxiliary power supplies (page 5645, Abstract; page 5656, section VIII: “Conclusion”).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the sub-module control unit disclosed by Outram to control the sub-modules to sequentially perform a passive charge mode and first/second active charge modes prior to the first/second normal operation modes, as taught by Zhang, to limit inrush currents on start-up without requiring additional equipment.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DANIEL P MCFARLAND/ Examiner, Art Unit 2859
/DREW A DUNN/ Supervisory Patent Examiner, Art Unit 2859