DETAILED ACTION
Status of Claims
Claims 1 – 10 are pending.
Claim 1 is independent.
This office action is Non-Final.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 3 is objected to because of the following informalities: it appears that claim 3 should depend on claim 2, and not claim 1, which appears to be in error. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 – 4 are rejected under 35 U.S.C. 103 as being unpatentable over Roberts (US Patent Application Publication No. 2020/0174748), in view of May (US Patent Application Publication No. 2008/0301409 A1).
As per claim 1, Roberts teaches a calculation processing device including a fetch unit [presorter 304, fig. 3] which reads data required for a calculation for performing processing of a neural network from a memory including a plurality of data memory slices and provides the data to an operation unit [processing circuits 300, fig. 3], wherein the fetch unit comprises: a fetch buffer [presort buffer 306, fig. 3] to which data stored in each of the data memory slices is fetched [0027: “… when generating the sorted order, the presorter sorts the actual instances of input data, such as by relocating instances of input data in a memory or in a presort buffer. In these embodiments, when processing the instances of input data through the neural network, the neural network processor can retrieve the instances of input data in the sorted order for processing…The presorter then provides, as the sorted order, the index to the neural network processor. When subsequently processing the instances of input data through the neural network, the neural network processor uses the index to determine which is the next instance of input data to be fetched (e.g., from memory, from a presort buffer, etc.) for processing through the neural network …”];
and an interface controller configured to give node identifiers (IDs) each corresponding to the data memory slices to the data fetched to the fetch buffer [input data is indexed and assigned identifiers, 0059 - 0060].
However, Roberts does not explicitly teach “…and control a timing of outputting the fetched data in accordance with the node IDs…”.
May is cited to teach assigning and run threads in a round robin manner. Both May and Roberts are directed to data management across multiple nodes.
As per claim 1, May further teaches … control a timing of outputting the fetched data in accordance with the node IDs [0060, 0061, 0069, fig.3, and fig. 3A: “… Instruction buffers (INSTR) 19 are also provided for temporarily holding instructions fetched from memory 24 before being subsequently issued into the execution unit 16. The execution unit has access to each of the registers 20 and buffers 19. Instructions are fetched from program memory 24 under control of the thread scheduler 18 and placed temporarily in the instruction buffers 19… the thread scheduler 18 maintains a set of n runnable threads, the set being termed "run", from which it issues instructions in turn for execution, preferably in a round-robin manner …”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Roberts and May, as May further teaches controlling the timing of outputting the fetch data based on the assignment order of the executing nodes.
As per claim 2, Roberts teaches the calculation processing device of claim 1, wherein the fetch unit further comprises a plurality of routers each having a data processing mapping table in which a method of processing input data is recorded according to a node ID of the input data [0002 – 0003, 0024 – 0026, 0048: input data is forwarded to other nodes, layer to layer].
As per claim 3, Roberts teaches the calculation processing device of claim 1[[ 2 ]], wherein the memory includes as many data memory slices as a number of the plurality of routers [0002 – 0003, 0024 – 0026: instances can be set to a specific number e.g. number of nodes in each layer to be forwarded].
As per claim 4, May teaches the calculation processing device of claim 3, wherein the interface controller controls a timing of inputting the fetched data to each of the routers in accordance with a node ID [0060 – 0061: “…Instruction buffers (INSTR) 19 are also provided for temporarily holding instructions fetched from memory 24 before being subsequently issued into the execution unit 16. The execution unit has access to each of the registers 20 and buffers 19. Instructions are fetched from program memory 24 under control of the thread scheduler 18 and placed temporarily in the instruction buffers 19… the thread scheduler 18 maintains a set of n runnable threads, the set being termed "run", from which it issues instructions in turn for execution, preferably in a round-robin manner…”].
Allowable Subject Matter
Claims 5 – 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lin; Tsung-Han (US Patent Application Publication No. 2018/0174053) “Unsupervised Learning Using Neuromorphic Computing” is cited to teach a spiking neural network (SNN) implemented on a neuromorphic computers and includes a plurality of neurons, a first set of the plurality of synapses defining feed-forward connections from a first subset of the neurons to a second subset of the neurons, a second subset of the plurality of synapses to define recurrent connections between the second subset of neurons, and a third subset of the plurality of synapses to define feedback connections from the second subset of neurons to the first subset of neurons. A set of input vectors are provided to iteratively modify weight values of the plurality of synapses. Each iteration involves selectively enabling and disabling the third subset of synapses with a different one of the input vectors applied to the SNN. The weight values are iteratively adjusted to derive a solution to an equation comprising an unknown matrix variable and an unknown vector variable
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/TERRELL S JOHNSON/Primary Examiner, Art Unit 2176