DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 9-20 are pending in this application. Claims 9-20 are new; claims 1-8 are canceled.
Priority
The present application, 18003945, filed 12/30/2022 is a National Stage entry of PCT/JP2020/025798, international filing date: 07/01/2020.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/30/2022 and 03/11/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 403 in Fig. 13.
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 9-20 are objected to under 37 C.F.R. 1.71(a) which requires “full, clear, concise, and exact terms” as to enable any person skilled in the art or science to which the invention or discovery appertains, or with which it is most nearly connected, to make and use the same. The following should be corrected.
A. In claim 9 lines 2-3, “N-bit (N is a natural number of 2 or more) fixed-length data” should read “N-bit fixed-length data, wherein N is a natural number of 2 or more” instead for better clarity because a parenthesis is normally used to denote reference characters when used in the claims. Claims 10-15 inherit the same deficiency as claim 9 by reason of dependence. Claim 16 recites a similar limitation in lines 2-3 and is objected to for the same reason. Claims 17-20 inherit the same deficiency as claim 16 by reason of dependence.
B. In claim 10 line 2, “a decimal point position” should read “the decimal point position” instead because a decimal point position is already introduced in claim 9 from which the claim depends.
C. In claim 11 line 5, “arithmetic processing” should read “the arithmetic processing” instead because arithmetic processing is already introduced in claim 9 from which the claim depends. Claim 14 recites a similar limitation in line 9 and is objected to for the same reason. Claims 12-13 inherit the same deficiency as claim 11 by reason of dependence.
D. In claim 14 lines 2-3, “the position of the decimal point” should read “the decimal point position” instead for consistency of claim terminologies.
E. In claim 17 lines 1-3, “further comprising: setting a decimal point position … based on” should read “wherein: setting the decimal point position … is based on” instead for better clarity.
F. In claim 20 line 3, “based on” should read “is based on” instead for better clarity.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 13-14 and 18-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites “the output” in claim lines 4-5. There is insufficient antecedent basis for this limitation in the claim. An output of the multilayered neural network is introduced in claim 10, however, claim 13 does not depend on claim 10. For purposes of examination, this is interpreted as an output instead. Claim 14 recites a similar limitation in lines 4 and 8 and is rejected for the same reason.
Claim 18 lines “the upper limit counter” and “the lower limit counter” in lines 5-6. There is insufficient antecedent basis for these limitations in the claim. For purposes of examination, these are interpreted as counters counting the numbers of times the data crosses the upper limit and the lower limit respectively. Claim 19 recites similar limitations in lines 2-3 and 5-6 and is rejected for the same reason. Claims 19-20 inherit the same deficiency as claim 18 by reason of dependence. Claim 20 inherit the same deficiency as claim 19 by reason of dependence.
Claim 20 recites “the output” in claim line 4. There is insufficient antecedent basis for this limitation in the claim. An output of the multilayered neural network is introduced in claim 17, however, claim 20 does not depend on claim 17. For purposes of examination, this is interpreted as an output instead.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 9-10 and 16-17 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Under Step 1, claims 9-10 recite a processor and, therefore, is a machine. Claims 16-17 recite a series of steps and, therefore, is a process.
Under Step 2A prong 1, claim 9 recites
A data processor comprising:
a decimal point position control circuit configured to set a decimal point position of N-bit (N is a natural number of 2 or more) fixed-length data corresponding to each of a plurality of layers constituting a multilayered neural network; and
an arithmetic processing circuit configured to perform arithmetic processing corresponding to each of the plurality of layers constituting the multilayered neural network according to a processing algorithm of the multilayered neural network on the N-bit fixed-length data for which the decimal point position has been set by the decimal point position control circuit.
The above underlined limitations of perform arithmetic processing on fixed-length data amounts to processing mathematical calculations and falls within the “Mathematical Concepts” and “Mental Processes” grouping of abstract ideas. Further, the step of “set a decimal point position of N-bit fixed-length data” is a process that under its broadest reasonable interpretation, covers performance of the limitation in the mind. That is, other than reciting “a decimal point position control circuit”, nothing in the claim element precludes the step from practically being performed in the human mind. For example, but for the “a decimal point position control circuit” language, the claim encompasses manually setting the decimal point position of a 16-bit data between the third and fourth bit position. Accordingly, the claim is directed to recite an abstract idea.
Under step 2A prong 2, the claim recites the following additional elements: a decimal point position control circuit; a plurality of layers constituting a multilayered neural network; and an arithmetic processing circuit. However, the additional elements of “a decimal point position control circuit” and “an arithmetic processing circuit” are recited at a high-level of generality (i.e., as a generic control circuit for controlling a decimal point position; and as a generic computer arithmetic circuit for performing arithmetic operations) such that they amount to no more than merely reciting the words “apply it” (or an equivalent) with the judicial exception or merely as tools to implement the abstract idea. The additional elements of “a plurality of layers constituting a multilayered neural network” is also recited at a high-level of generality such that it amounts to no more than generally linking the use of the judicial exception to a particular technological environment or field of use. See MPEP 2106.05(h) for more information. The additional elements do not, individually or in combination, integrate the exception into a practical application. Accordingly, the claim is not integrated into a practical application.
Under step 2B, claim 9 does not include additional elements that, individually or in combination, are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “a decimal point position control circuit” and “an arithmetic processing circuit” are recited at a high-level of generality (i.e., as a generic control circuit for controlling a decimal point position; and as a generic computer arithmetic circuit for performing arithmetic operations) such that they amount to no more than merely reciting the words “apply it” (or an equivalent) with the judicial exception or merely as tools to implement the abstract idea. The additional elements of “a plurality of layers constituting a multilayered neural network” is also recited at a high-level of generality such that it amounts to no more than generally linking the use of the judicial exception to a particular technological environment or field of use. See MPEP 2106.05(h) for more information. The claim does not recite additional elements that alone or in combination amount to an inventive concept. Accordingly, the claim does not amount to significantly more than the abstract idea.
Under step 2A prong 1, claim 10 recites the same abstract idea as claim 9 by reason of dependence. Further, claim 10 recites further details of the abstract idea of setting the decimal point position based on an output of the multilayered neural network which falls within the “Mathematical Concepts” and/or “Mental Processes” grouping of abstract ideas. In particular claim 10 does not include additional elements that would require further analysis under step 2A prong 2 and step 2B. Accordingly, the claim is directed to recite an abstract idea.
Regarding claims 16-17, they are directed to a method practiced by the processor of claims 10-11 respectively. All steps performed by the method of claims 16-17 would be practiced by the processor of claims 10-11 respectively. Claims 10-11 analysis applies equally to claims 16-17 respectively.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 9-10 and 16-17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ito (US 20210012192 A1).
Regarding claim 9, Ito teaches an apparatus comprising:
a decimal point position control circuit configured to set a decimal point position of N-bit (N is a natural number of 2 or more) fixed-length data corresponding to each of a plurality of layers constituting a multilayered neural network (Ito Figs. 1, 7, 9-10, 14, 22 and paragraphs [0059, 0077-0078, 0080-0081, 0093, 0136] decimal point position control circuit – determiner 14; N-bit fixed-length data – 8-bit or 16-bit fixed-point data); and
an arithmetic processing circuit configured to perform arithmetic processing corresponding to each of the plurality of layers constituting the multilayered neural network according to a processing algorithm of the multilayered neural network on the N-bit fixed-length data for which the decimal point position has been set by the decimal point position control circuit (Ito Figs. 1, 4, 7, 14 and paragraphs [0052, 0057, 0082, 0093] arithmetic processing circuit – learning unit 12; arithmetic processing – convolution/product-sum calculation).
Regarding claim 10, Ito teaches all the limitations of claim 9 as stated above. Further, Ito teaches wherein the decimal point position control circuit is configured to set a decimal point position of the fixed-length data corresponding to each of the plurality of layers constituting the multilayered neural network based on an output of the multilayered neural network (Ito Figs. 3, 7, 9-10, 14 and paragraphs [0052, 0055, 0059, 0077-0078, 0082] “the calculation result is compared with the correct answer data, and the parameters of each layer 21 are updated on the basis of the comparison result”).
Regarding claims 16-17, they are directed to a method practiced by the processor of claims 10-11 respectively. All steps performed by the method of claims 16-17 would be practiced by the processor of claims 10-11 respectively. Claims 10-11 analysis applies equally to claims 16-17 respectively.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-13 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ito as applied to claims 9 and 16 above, and further in view of Ito (US 20190265949 A1), hereinafter ‘949.
Regarding claim 11, Ito teaches all the limitations of claim 9 as stated above. Further, Ito teaches further comprising an upper limit counter and a lower limit counter configured to count numbers of times data crosses an upper limit and a lower limit of a range, respectively, the range determined according to the decimal point position set by the decimal point position control circuit, in a process of arithmetic processing corresponding to each of the plurality of layers constituting the multilayered neural network performed by the arithmetic processing circuit, wherein the decimal point position control circuit is configured to set the decimal point position of the fixed-length data corresponding to each of the plurality of layers constituting the multilayered neural network based on a value of the upper limit counter (Ito Figs. 1, 8-10 and paragraphs [0060, 0074-0075, 0080-0081] upper limit counter – storage storing the number of appearance of values that exceed the expressible range; lower limit counter - storage storing the number of appearance of values that are below the expressible range; range – expressible range (region).
Ito does not explicitly teach wherein the decimal point position control circuit is configured to set the decimal point position of the fixed-length data corresponding to each of the plurality of layers constituting the multilayered neural network based on a value of the upper limit counter and a value of the lower limit counter.
However, on the same field of endeavor, ‘949 discloses setting a decimal point position of data corresponding to each of a plurality of layers constituting a multilayered neural network based on a value of the upper limit counter and a value of the lower limit counter (‘949 Fig. 32 and paragraphs [0186, 0188, 0191-0192] value of the lower limit counter – number or occurrence of underflow).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Ito using ‘949 and configure the decimal point position control circuit to set the decimal point position of the fixed-length data corresponding to each of the plurality of layers constituting the multilayered neural network based on a value of the upper limit counter and a value of the lower limit counter such that the expressible range satisfies both condition that an overflow rate is less than a first reference value and the underflow rate is less than a second reference value which may further improve accuracy during learning (‘949 Fig. 46 and paragraphs [0192, 0237]).
Therefore, the combination of Ito as modified in view of ‘949 teaches wherein the decimal point position control circuit is configured to set the decimal point position of the fixed-length data corresponding to each of the plurality of layers constituting the multilayered neural network based on a value of the upper limit counter and a value of the lower limit counter.
Regarding claim 12, Ito as modified in view of ‘949 teaches all the limitations of claim 11 as stated above. Further, Ito as modified in view of ‘949 teaches (‘949 paragraphs [0191-0192] first threshold value -
r
o
f
; second threshold value -
r
u
f
).
Ito does not explicitly teach further comprising a storage device configured to store a first threshold value for the value of the upper limit counter and a second threshold value for the value of the lower limit counter.
However, Ito discloses storage devices for storing different data (Ito Fig. 1 and paragraphs [0048, 0058, 0060] storage device – storing units 11, 13, 15).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Ito using ‘949 and configure the system to include a storage device for storing the first threshold value and the second threshold value. Paragraph [0193] of ‘949 discloses that the first threshold value and the second threshold value are user input values. Therefore, the first threshold value and the second threshold value only needs to be provided once if a storage device for storing the first threshold value and the second threshold value is provided rather than providing the threshold values every time the decimal point position has to be updated.
Therefore, the combination of Ito as modified in view of ‘949 teaches further comprising a storage device configured to store a first threshold value for the value of the upper limit counter and a second threshold value for the value of the lower limit counter set to correspond to each of the plurality of layers constituting the multilayered neural network.
Regarding claim 13, Ito as modified in view of ‘949 teaches all the limitations of claim 11 as stated above. Further, Ito as modified in view of ‘949 teaches wherein the decimal point position control circuit is configured to set the decimal point position of the fixed-length data corresponding to each of the plurality of layers constituting the multilayered neural network based on the value of the upper limit counter, the value of the lower limit counter, and the output of the multilayered neural network (Ito Figs. 3, 8-10, 14 and paragraphs [0052, 0055, 0059-0060, 0074-0075, 0077-0078, 0080-0082]; ‘949 paragraphs [0191-0192]).
Regarding claims 18-20, they are directed to a method practiced by the processor of claims 11-13 respectively. All steps performed by the method of claims 18-20 would be practiced by the processor of claims 11-13 respectively. Claims 11-13 analysis applies equally to claims 18-20 respectively.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Ito as applied to claim 9 above, and further in view of Yoda (US 20210208849 A1).
Regarding claim 14, Ito teaches all the limitations of claim 9 as stated above.
Ito does not explicitly teach further comprising: a plurality of decimal point position control circuits each configured to set the position of the decimal point of the fixed-length data corresponding to each of the plurality of layers constituting the multilayered neural network based on the output of the multilayered neural network; and a control method determination circuit configured to select any one of the plurality of decimal point position control circuits for each of the plurality of layers constituting the multilayered neural network based on the output of the multilayered neural network, wherein the arithmetic processing circuit is configured to perform arithmetic processing corresponding to each of the plurality of layers constituting the multilayered neural network according to a processing algorithm of the multilayered neural network on the N-bit fixed-length data for which the decimal point position has been set by any one of the plurality of decimal point position control circuits selected by the control method determination circuit.
However, on the same field of endeavor, Yoda discloses a plurality of decimal point position storage circuits each configured to set the position of the decimal point of data corresponding to each of a plurality of layers constituting a multilayered neural network based on an output of the multilayered neural network; and a control method determination circuit configured to select any one of the plurality of decimal point position storage circuits for each of the plurality of layers constituting the multilayered neural network based on the output of the multilayered neural network, wherein an arithmetic processing circuit is configured to perform arithmetic processing corresponding to each of the plurality of layers constituting the multilayered neural network according to a processing algorithm of the multilayered neural network on the data for which the decimal point position has been set by any one of the plurality of decimal point position storage circuits selected by the control method determination circuit (Yoda Fig. 5 and paragraphs [0056-0061]).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Ito and generalize the teaching of Yoda by configuring the system to include a plurality of determiner that are each configured to acquire a respective candidate decimal point position and an overall manager for selecting which candidate decimal point position of the plurality of candidate decimal point positions to use by the learning unit in order speculatively execute the preceding operation using the plurality of candidate decimal point positions and using the operation result of the speculative operation as the operation result of the concerned layer when the operation matches a candidate decimal point position to reduce processing time due to the speculative operation (Yoda paragraphs [0080-0081]). Furthermore, duplication of parts is obvious to one of ordinary skill in the art. See MPEP 2144.04 VI.B for more information.
Therefore, the combination of Ito as modified in view of Yoda teaches further comprising: a plurality of decimal point position control circuits each configured to set the position of the decimal point of the fixed-length data corresponding to each of the plurality of layers constituting the multilayered neural network based on the output of the multilayered neural network; and a control method determination circuit configured to select any one of the plurality of decimal point position control circuits for each of the plurality of layers constituting the multilayered neural network based on the output of the multilayered neural network, wherein the arithmetic processing circuit is configured to perform arithmetic processing corresponding to each of the plurality of layers constituting the multilayered neural network according to a processing algorithm of the multilayered neural network on the N-bit fixed-length data for which the decimal point position has been set by any one of the plurality of decimal point position control circuits selected by the control method determination circuit.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Ito as applied to claim 9 above, and further in view of Redmon et al. (NPL – “YOLOv3: An Incremental Improvement”), hereinafter, Redmon. Redmon is cited in the IDS submitted on 12/30/2022.
Regarding claim 15, Ito teaches all the limitations of claim 9 as stated above.
Ito does not explicitly teach wherein the multilayered neural network is configured to output metadata from an input image, the metadata including an attribute of an object involved in the input image, detection accuracy of the attribute, and a location of the object in the image.
However, on the same field of endeavor, Redmon discloses a multilayered neural network configured to output metadata from an input image, the metadata including an attribute of an object involved in the input image, detection accuracy of the attribute, and a location of the object in the image (Redmon section 2.1-2.3; see also paragraph [0044] which discloses that Redmon (i.e., NPL 1) output metadata such as an attribute of an object involved in an input image, the accuracy of the attribute, and a position).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Ito using Redmon and configure the multilayered neural network to output metadata from an input image, the metadata including an attribute of an object involved in the input image, detection accuracy of the attribute, and a location of the object in the image in order to implement an object detection/recognition system (Redmon section 3).
Therefore, the combination of Ito as modified in view of Redmon teaches wherein the multilayered neural network is configured to output metadata from an input image, the metadata including an attribute of an object involved in the input image, detection accuracy of the attribute, and a location of the object in the image.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ge et al. (US 20210240439 A) discloses an apparatus comprising a decimal point position determiner that acquires statistical information and determines an optimal decimal point position using the acquired statistical information and an operation section that performs arithmetic processing using the determined decimal point position. See at least Fig. 4.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlo Waje whose telephone number is (571)272-5767. The examiner can normally be reached 9:00-6:00 M-F.
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/Carlo Waje/Examiner, Art Unit 2151 (571)272-5767
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