Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office action is Non-Final and is in response to claims filed on 01/04/2023 via amendment. Claims 7-12 are pending for examination. Claims 7-12 are newly presented.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 01/04/2023 is in compliance with the provisions of 37 CFR 1.97, 1.98, and MPEP § 609. It has been placed in the application file, and the information referred to therein has been considered as to the merits.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 7-12 are rejected under 35 U.S.C. 101 because the claimed invention is directed to abstract ideas without significantly more.
With regards to claim 1, at step 1, the claim is directed to a machine, which is a statutory category of invention.
At Step 2A Prong 1, the examiner notes that the claim is directed to mental processes and/or mathematical concepts. The claim language has been reproduced below:
A two-dimensional data transform device, the device comprising: (mental process, evaluation)
a first column reader configured to (mental process, evaluation) read a first element group of one or more columns in a column direction of original data from an auxiliary storage device in which respective elements of the original data of M rows and N columns are continuously recorded in order in a row direction on the original data, (mental process, evaluation) wherein M and N are integers of 2 or greater; (mental process, evaluation; mathematical relationship)
a first one-dimensional transformer configured to (mental process, evaluation) perform one-dimensional transform on the first element group of each of the one or more columns read by the first column reader; (mathematical calculation)
a first row writer configured to (mental process, evaluation) write the first element group of the one or more columns transformed by the first one-dimensional transformer into the auxiliary storage device as a second element group of one or more rows in the row direction of intermediate data of N rows and M columns; (mental process, evaluation)
a second column reader configured to (mental process, evaluation) read a third element group of one or more columns in the column direction of the intermediate data from the auxiliary storage device after all of the original data is transformed and recorded in the auxiliary storage device as the intermediate data; (mental process, evaluation)
a second one-dimensional transformer configured to (mental process, evaluation) perform one-dimensional transform on the third element group of each of the one or more columns read by the second column reader; and (mathematical calculation)
a second row writer configured to (mental process, evaluation) write the third element group of the one or more columns transformed by the second one-dimensional transformer into the auxiliary storage device as a fourth element group of one or more rows in the row direction of final data of M rows and N columns; (mental process, evaluation)
wherein the first column reader, the first one-dimensional transformer, and the first row writer are configured to (mental process, evaluation) repeat processing until all of the original data is transformed and recorded in the auxiliary storage device as the intermediate data; and (mental process, evaluation; mathematical calculation)
the second column reader, the second one-dimensional transformer, and the second row writer are configured to (mental process, evaluation) repeat processing until all of the intermediate data is transformed and recorded in the auxiliary storage device as the final data. (mental process, evaluation; mathematical calculation)
Each of the non-bolded limitations are mental processes and/or mathematical calculations. The “the device comprising” limitation is an evaluation mental process that can be performed by choosing what the device comprises. The “a first column reader configured to” limitation is an evaluation mental process that can be performed by choosing what the first column reader is configured to do. The “a first element group of one or more columns in a column direction of original data from” limitation is an evaluation mental process that can be performed by choosing how the inputs are read. The “wherein M and N are integers of 2 or greater” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing the size of the inputs. The “a first one-dimensional transformer configured to” limitation is an evaluation mental process that can be performed by choosing what the first one-dimensional transformer is configured to do. The “perform one-dimensional transform on the first element group of each of the one or more columns” limitation is a mathematical calculation that can be performed by performing the one-dimensional transform by hand using pen and paper. The “a first row writer configured to” limitation is an evaluation mental process that can be performed by choosing what the first row writer is configured to do. The “the first element group of the one or more columns transformed by” limitation is an evaluation mental process that can be performed by choosing how the outputs are written. The “a second column reader configured to” limitation is an evaluation mental process that can be performed by choosing what the second column reader is configured to do. The “a third element group of one or more columns in the column direction of the intermediate data” limitation is an evaluation mental process that can be performed by choosing how the inputs are read. The “a second one-dimensional transformer configured to” limitation is an evaluation mental process that can be performed by choosing what the second one-dimensional transformer is configured to do. The “perform one-dimensional transform on the third element group of each of the one or more columns” limitation is a mathematical calculation that can be performed by performing the one-dimensional transform by hand using pen and paper. The “a second row writer configured to” limitation is an evaluation mental process that can be performed by choosing what the second row writer is configured to do. The “the third element group of the one or more columns transformed by” limitation is an evaluation mental process that can be performed by choosing how the outputs are written. The “wherein the first column reader, the first one-dimensional transformer, and the first row writer are configured to” limitation is an evaluation mental process that can be performed by choosing what the first column reader, the first one-dimensional transformer, and the first row writer are configured to do. The “repeat processing until all of the original data is transformed” limitation is an evaluation mental process and mathematical calculation that can be performed by choosing to repeat the processing and performing the calculations by hand using pen and paper. The “the second column reader, the second one-dimensional transformer, and the second row writer are configured to” limitation is an evaluation mental process that can be performed by choosing what the second column reader, the second one-dimensional transformer, and the second row writer are configured to do. The “repeat processing until all of the intermediate data is transformed” limitation is an evaluation mental process and mathematical calculation that can be performed by choosing to repeat the processing and performing the calculations by hand using pen and paper.
At step 2A Prong 2, the additional elements are bolded above. The “read” limitations, as claimed under BRI, are additional elements that are insignificant extra-solution activity. The ‘read’ in the context of the claim encompasses mere data gathering. The “recorded” limitations, as claimed under BRI, are additional elements that are insignificant extra-solution activity. The ‘recorded’ in the context of the claim encompasses mere data gathering. The “write” limitations, as claimed under BRI, are additional elements that are insignificant extra-solution activity. The ‘write’ in the context of the claim encompasses mere data gathering. The remaining additional elements amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f).
At Step 2B, the claim recites “read a first element group of one or more columns in a column direction”, “continuously recorded in order in a row direction on the original data”, “columns read by the first column reader”, “write the first element group of the one or more columns transformed”, “read a third element group of one or more columns in the column direction of the intermediate data”, “recorded in the auxiliary storage device as the intermediate data”, “read by the second column reader”, “write the third element group of the one or more columns transformed”, “recorded in the auxiliary storage device as the intermediate data”, “recorded in the auxiliary storage device as the final data”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network); and
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93.
Regarding claim 8, It recites similar language as claim 7, and is rejected for at least the same reasons therein. Herein, claim 8 is directed towards the statutory category of a machine, thus also satisfying step 1. The “a first data switcher configured to” limitation is an evaluation mental process that can be performed by choosing what the first data switcher is configured to do. The “perform switching of an input of the column reader such that the original data becomes the input data” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the input data is. The “and perform switching of an input of the column reader such that the intermediate data becomes the input data” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the input data is. The “a second data switcher configured to” limitation is an evaluation mental process that can be performed by choosing what the second data switcher is configured to do. The “perform switching of an output of the row writer such that the intermediate data becomes the output data” limitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the output data is. The “perform switching of an output of the row writer such that final data of M rows and N columns becomes the output data” imitation is an evaluation mental process and mathematical relationship that can be performed by choosing what the output data is. Under step 2A prong 2, none of the remaining additional elements regarding the generic computer components (i.e. the first data switcher, the second data switcher etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under step 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
Regarding claim 9, It recites similar language as claim 8, and is rejected for at least the same reasons therein. Herein, claim 9 is directed towards the statutory category of a method, thus also satisfying step 1. Moreover, Under steps 2A Prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
Regarding claim 10, It recites similar language as claim 9, and is rejected for at least the same reasons therein. Herein, claim 10 is directed towards the statutory category of an article of manufacture, thus also satisfying step 1. The “A non-transitory computer readable medium for” limitation is an evaluation mental process that can be performed by choosing what the non-transitory computer readable medium is for. The “that, when executed by a computer, cause the computer to perform the method” limitation is an evaluation mental process that can be performed by choosing what the instructions do. Under step 2A prong 2, the “storing” limitation as claimed under BRI, is an additional element that are insignificant extra-solution activity. The ‘storing’ in the context of the claim encompasses mere data gathering. None of the remaining additional elements regarding the generic computer components (i.e. the non-transitory computer readable medium, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under Step 2B, the claim recites “A non-transitory computer readable medium for storing instructions”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network); and
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93.
Regarding claim 11, It recites similar language as claim 7, and is rejected for at least the same reasons therein. Herein, claim 11 is directed towards the statutory category of a method, thus also satisfying step 1. Moreover, Under steps 2A Prong 2 and 2B, the claim does not recite any additional elements that integrate the abstract idea into a practical application, nor do they amount to significantly more than the judicial exception.
Regarding claim 12, It recites similar language as claim 11, and is rejected for at least the same reasons therein. Herein, claim 12 is directed towards the statutory category of an article of manufacture, thus also satisfying step 1. The “A non-transitory computer readable medium for” limitation is an evaluation mental process that can be performed by choosing what the non-transitory computer readable medium is for. The “that, when executed by a computer, cause the computer to perform the method” limitation is an evaluation mental process that can be performed by choosing what the instructions do. Under step 2A prong 2, the “storing” limitation as claimed under BRI, is an additional element that are insignificant extra-solution activity. The ‘storing’ in the context of the claim encompasses mere data gathering. None of the remaining additional elements regarding the generic computer components (i.e. the non-transitory computer readable medium, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). Under Step 2B, the claim recites “A non-transitory computer readable medium for storing instructions”, and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network); and
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-12 are rejected under 35 U.S.C. 103 as being unpatentable over Liou et al. (US 4791598 A) hereinafter Liou in view of Sadafale et al. (US 20130034150 A1) hereinafter Sadafale.
With regards to claim 7, Liou teaches A two-dimensional data transform device, the device comprising: a first column reader configured to read a first element group of one or more columns in a column direction of original data from an auxiliary storage device in which respective elements of the original data of M rows and N columns are continuously recorded in order in a row direction on the original data, wherein M and N are integers of 2 or greater; (Liou Column 2 Lines 51-68 and Column 3 Line 1: Our two-dimensional DCT processor comprises an input one-dimensional (N.times.1) Column DCT processor to which the N.times.N input data block is sequentially applied column by column… Each of the columns of the data matrix is applied to the input N.times.1 processor in sequence to produce the N.times.N intermediate matrix (Y))
a first one-dimensional transformer configured to perform one-dimensional transform on the first element group of each of the one or more columns read by the first column reader; (Liou Column 2 Lines 51-54: Our two-dimensional DCT processor comprises an input one-dimensional (N.times.1) Column DCT processor to which the N.times.N input data block is sequentially applied column by column)
a first row writer configured to write the first element group of the one or more columns transformed by the first one-dimensional transformer into the auxiliary storage device as a second element group of one or more rows in the row direction of intermediate data of N rows and M columns; (Liou Column 2 Lines 62-68 and Column 3 Lines 1-4: The accumulators concurrently compute the elements of the column transform by shifting and adding of the data retrieved from the ROMs. The resultant intermediate vector is stored in one row of a N.times.N transposition memory which comprises a RAM. Each of the columns of the data matrix is applied to the input N.times.1 processor in sequence to produce the N.times.N intermediate matrix (Y) which is the product (X.sup.t C) of the transpose of the data matrix (X.sup.t) and the discrete cosine matrix (C) represented by the constants stored in the ROM)
a second column reader configured to read a third element group of one or more columns in the column direction of the intermediate data from the auxiliary storage device after all of the original data is transformed and recorded in the auxiliary storage device as the intermediate data; (Liou Column 3 Lines 5-8: A second or output row N.times.1 DCT processor is then used to compute the one-dimensional N.times.1 DCT for each column of X.sup.t C, which is retrieved from storage in the memory)
a second one-dimensional transformer configured to perform one-dimensional transform on the third element group of each of the one or more columns read by the second column reader; (Liou Column 3 Lines 5-8: A second or output row N.times.1 DCT processor is then used to compute the one-dimensional N.times.1 DCT for each column of X.sup.t C, which is retrieved from storage in the memory)
wherein the first column reader, the first one-dimensional transformer, and the first row writer are configured to repeat processing until all of the original data is transformed and recorded in the auxiliary storage device as the intermediate data; (Liou Column 2 Lines 62-68 and Column 3 Lines 1-4: The accumulators concurrently compute the elements of the column transform by shifting and adding of the data retrieved from the ROMs. The resultant intermediate vector is stored in one row of a N.times.N transposition memory which comprises a RAM. Each of the columns of the data matrix is applied to the input N.times.1 processor in sequence to produce the N.times.N intermediate matrix (Y) which is the product (X.sup.t C) of the transpose of the data matrix (X.sup.t) and the discrete cosine matrix (C) represented by the constants stored in the ROM)
and the second column reader, the second one-dimensional transformer, and [the second row writer] are configured to repeat processing until all of the intermediate data is transformed and recorded in the auxiliary storage device as the final data (Liou Column 3 Lines 5-8: A second or output row N.times.1 DCT processor is then used to compute the one-dimensional N.times.1 DCT for each column of X.sup.t C, which is retrieved from storage in the memory).
Liou fails to teach and a second row writer configured to write the third element group of the one or more columns transformed by the second one-dimensional transformer into the auxiliary storage device as a fourth element group of one or more rows in the row direction of final data of M rows and N columns; [and the second column reader, the second one-dimensional transformer, and] the second row writer [are configured to repeat processing until all of the intermediate data is transformed and recorded in the auxiliary storage device as the final data].
However, Sadafale teaches and a second row writer configured to write the third element group of the one or more columns transformed by the second one-dimensional transformer into the auxiliary storage device as a fourth element group of one or more rows in the row direction of final data of M rows and N columns; (Sadafale [0041]: the 2-D forward transform may be implemented as a cascade of 1-D transform steps 224, 228, with each 1-D transform followed by a transpose step 226, 230; Sadafale [0080]: the intermediate input matrix of transform coefficients is transposed to provide a transposed intermediate input matrix of transform coefficients. The transpose operation involves an interchanging of the rows and columns of the intermediate input matrix; Sadafale [0088]: The memory module 908 is configured to store the multimedia data subsequent to one of encoding of multimedia data and decoding of multimedia data)
[and the second column reader, the second one-dimensional transformer, and] the second row writer [are configured to repeat processing until all of the intermediate data is transformed and recorded in the auxiliary storage device as the final data] (Sadafale [0041]: the 2-D forward transform may be implemented as a cascade of 1-D transform steps 224, 228, with each 1-D transform followed by a transpose step 226, 230; Sadafale [0080]: the intermediate input matrix of transform coefficients is transposed to provide a transposed intermediate input matrix of transform coefficients. The transpose operation involves an interchanging of the rows and columns of the intermediate input matrix; Sadafale [0088]: The memory module 908 is configured to store the multimedia data subsequent to one of encoding of multimedia data and decoding of multimedia data).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teaching Liou with the second row writer as taught by Sadafale. One of ordinary skill in the art would be motivated to make this combination because it also enables a saving of area and power in a system for decoding multimedia data to be achieved as taught by Sadafale (Sadafale [0048]).
With regards to claim 8, Liou teaches A two-dimensional data transform device, the device comprising: a column reader configured to read a first element group of one or more columns in a column direction of input data that is two-dimensional data of M rows and N columns or N rows and M columns from an auxiliary storage device, wherein M and N are integers of 2 or greater; (Liou Column 2 Lines 51-68 and Column 3 Line 1: Our two-dimensional DCT processor comprises an input one-dimensional (N.times.1) Column DCT processor to which the N.times.N input data block is sequentially applied column by column… Each of the columns of the data matrix is applied to the input N.times.1 processor in sequence to produce the N.times.N intermediate matrix (Y))
a one-dimensional transformer configured to perform one-dimensional transform on the first element group of each of the one or more columns read by the column reader; (Liou Column 2 Lines 51-54: Our two-dimensional DCT processor comprises an input one-dimensional (N.times.1) Column DCT processor to which the N.times.N input data block is sequentially applied column by column)
a row writer configured to write the first element group of one or more columns transformed by the one-dimensional transformer into the auxiliary storage device as a second element group of one or more rows in a row direction of output data that is two-dimensional data of N rows and M columns or M rows and N columns; (Liou Column 2 Lines 62-68 and Column 3 Lines 1-4: The accumulators concurrently compute the elements of the column transform by shifting and adding of the data retrieved from the ROMs. The resultant intermediate vector is stored in one row of a N.times.N transposition memory which comprises a RAM. Each of the columns of the data matrix is applied to the input N.times.1 processor in sequence to produce the N.times.N intermediate matrix (Y) which is the product (X.sup.t C) of the transpose of the data matrix (X.sup.t) and the discrete cosine matrix (C) represented by the constants stored in the ROM)
a first data switcher configured to, for the auxiliary storage device in which respective elements of original data of M rows and N columns are continuously recorded in order in the row direction on the original data, perform switching of an input of the column reader such that the original data becomes the input data, (Liou Column 2 Lines 62-68 and Column 3 Lines 1-4: The accumulators concurrently compute the elements of the column transform by shifting and adding of the data retrieved from the ROMs. The resultant intermediate vector is stored in one row of a N.times.N transposition memory which comprises a RAM. Each of the columns of the data matrix is applied to the input N.times.1 processor in sequence to produce the N.times.N intermediate matrix (Y) which is the product (X.sup.t C) of the transpose of the data matrix (X.sup.t) and the discrete cosine matrix (C) represented by the constants stored in the ROM)
and perform switching of an input of the column reader such that the intermediate data becomes the input data after all of the original data is transformed and recorded in the auxiliary storage device as the intermediate data of N rows and M columns; (Liou Column 5 Lines 51-53: If speed is not important the two N.times.1 DCT computations can be time-shared by the same circuitry)
and wherein the column reader, the one-dimensional transformer, and the row writer are configured to repeat processing until all of the original data is transformed and recorded in the auxiliary storage device as the intermediate data (Liou Column 2 Lines 62-68 and Column 3 Lines 1-4: The accumulators concurrently compute the elements of the column transform by shifting and adding of the data retrieved from the ROMs. The resultant intermediate vector is stored in one row of a N.times.N transposition memory which comprises a RAM. Each of the columns of the data matrix is applied to the input N.times.1 processor in sequence to produce the N.times.N intermediate matrix (Y) which is the product (X.sup.t C) of the transpose of the data matrix (X.sup.t) and the discrete cosine matrix (C) represented by the constants stored in the ROM)
and to further repeat processing until all of the intermediate data is transformed and recorded in the auxiliary storage device as the final data (Liou Column 3 Lines 5-8: A second or output row N.times.1 DCT processor is then used to compute the one-dimensional N.times.1 DCT for each column of X.sup.t C, which is retrieved from storage in the memory).
Liou fails to teach and a second data switcher configured to perform switching of an output of the row writer such that the intermediate data becomes the output data and perform switching of an output of the row writer such that final data of M rows and N columns becomes the output data after all of the original data is transformed and recorded in the auxiliary storage device as the intermediate data.
However, Sadafale teaches and a second data switcher configured to perform switching of an output of the row writer such that the intermediate data becomes the output data (Sadafale [0041]: the 2-D forward transform may be implemented as a cascade of 1-D transform steps 224, 228, with each 1-D transform followed by a transpose step 226, 230; Sadafale [0080]: the intermediate input matrix of transform coefficients is transposed to provide a transposed intermediate input matrix of transform coefficients. The transpose operation involves an interchanging of the rows and columns of the intermediate input matrix; Sadafale [0088]: The memory module 908 is configured to store the multimedia data subsequent to one of encoding of multimedia data and decoding of multimedia data)
and perform switching of an output of the row writer such that final data of M rows and N columns becomes the output data after all of the original data is transformed and recorded in the auxiliary storage device as the intermediate data; (Sadafale [0041]: the 2-D forward transform may be implemented as a cascade of 1-D transform steps 224, 228, with each 1-D transform followed by a transpose step 226, 230; Sadafale [0080]: the intermediate input matrix of transform coefficients is transposed to provide a transposed intermediate input matrix of transform coefficients. The transpose operation involves an interchanging of the rows and columns of the intermediate input matrix; Sadafale [0088]: The memory module 908 is configured to store the multimedia data subsequent to one of encoding of multimedia data and decoding of multimedia data).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teaching Liou with the second data switcher as taught by Sadafale. One of ordinary skill in the art would be motivated to make this combination because it also enables a saving of area and power in a system for decoding multimedia data to be achieved as taught by Sadafale (Sadafale [0048]).
With regards to claim 9, Liou teaches the method comprising: a first step of setting the original data as the input data (Liou Column 2 Lines 51-54: Our two-dimensional DCT processor comprises an input one-dimensional (N.times.1) Column DCT processor to which the N.times.N input data block is sequentially applied column by column)
and setting the intermediate data of N rows and M columns as the output data for the auxiliary storage device in which respective elements of the original data of M rows and N columns are continuously recorded in order in the row direction on the original data; (Liou Column 2 Lines 62-68 and Column 3 Lines 1-4: The accumulators concurrently compute the elements of the column transform by shifting and adding of the data retrieved from the ROMs. The resultant intermediate vector is stored in one row of a N.times.N transposition memory which comprises a RAM. Each of the columns of the data matrix is applied to the input N.times.1 processor in sequence to produce the N.times.N intermediate matrix (Y) which is the product (X.sup.t C) of the transpose of the data matrix (X.sup.t) and the discrete cosine matrix (C) represented by the constants stored in the ROM)
a second step of reading the first element group of one or more columns in the column direction of the input data from the auxiliary storage device; (Liou Column 2 Lines 51-54: Our two-dimensional DCT processor comprises an input one-dimensional (N.times.1) Column DCT processor to which the N.times.N input data block is sequentially applied column by column)
a third step of performing one-dimensional transform on the first element group of each of the one or more columns read in the second step; (Liou Column 2 Lines 51-54: Our two-dimensional DCT processor comprises an input one-dimensional (N.times.1) Column DCT processor to which the N.times.N input data block is sequentially applied column by column)
fourth step of writing the first element group of the one or more columns transformed in the third step into the auxiliary storage device as the second element group of one or more rows in the row direction of the output data; (Liou Column 2 Lines 62-68 and Column 3 Lines 1-4: The accumulators concurrently compute the elements of the column transform by shifting and adding of the data retrieved from the ROMs. The resultant intermediate vector is stored in one row of a N.times.N transposition memory which comprises a RAM. Each of the columns of the data matrix is applied to the input N.times.1 processor in sequence to produce the N.times.N intermediate matrix (Y) which is the product (X.sup.t C) of the transpose of the data matrix (X.sup.t) and the discrete cosine matrix (C) represented by the constants stored in the ROM)
a fifth step of setting the intermediate data as the input data and setting the final data of M rows and N columns as the output data after all of the original data is transformed and recorded in the auxiliary storage device as the intermediate data; (Liou Column 5 Lines 51-53: If speed is not important the two N.times.1 DCT computations can be time-shared by the same circuitry; Liou Column 3 Lines 5-8: A second or output row N.times.1 DCT processor is then used to compute the one-dimensional N.times.1 DCT for each column of X.sup.t C, which is retrieved from storage in the memory)
a sixth step of reading the second element group of one or more columns in the column direction of the input data from the auxiliary storage device; (Liou Column 3 Lines 5-8: A second or output row N.times.1 DCT processor is then used to compute the one-dimensional N.times.1 DCT for each column of X.sup.t C, which is retrieved from storage in the memory)
a seventh step of performing one-dimensional transform on the second element group of each of the one or more columns read in the sixth step; (Liou Column 3 Lines 5-8: A second or output row N.times.1 DCT processor is then used to compute the one-dimensional N.times.1 DCT for each column of X.sup.t C, which is retrieved from storage in the memory)
wherein in the second step, the third step, and the fourth step, processing is repeated until all of the original data is transformed and recorded in the auxiliary storage device as the intermediate data; (Liou Column 2 Lines 62-68 and Column 3 Lines 1-4: The accumulators concurrently compute the elements of the column transform by shifting and adding of the data retrieved from the ROMs. The resultant intermediate vector is stored in one row of a N.times.N transposition memory which comprises a RAM. Each of the columns of the data matrix is applied to the input N.times.1 processor in sequence to produce the N.times.N intermediate matrix (Y) which is the product (X.sup.t C) of the transpose of the data matrix (X.sup.t) and the discrete cosine matrix (C) represented by the constants stored in the ROM)
and wherein in the sixth step, the seventh step, and [the eighth step], processing is repeated until all of the intermediate data is transformed and recorded in the auxiliary storage device as the final data (Liou Column 3 Lines 5-8: A second or output row N.times.1 DCT processor is then used to compute the one-dimensional N.times.1 DCT for each column of X.sup.t C, which is retrieved from storage in the memory).
Liou fails to teach and an eighth step of writing the second element group of the one or more columns transformed in the seventh step into the auxiliary storage device as a third element group of one or more rows in the row direction of the output data; and [and wherein in the sixth step, the seventh step, and] the eighth step, [processing is repeated until all of the intermediate data is transformed and recorded in the auxiliary storage device as the final data].
However, Sadafale teaches and an eighth step of writing the second element group of the one or more columns transformed in the seventh step into the auxiliary storage device as a third element group of one or more rows in the row direction of the output data; (Sadafale [0041]: the 2-D forward transform may be implemented as a cascade of 1-D transform steps 224, 228, with each 1-D transform followed by a transpose step 226, 230; Sadafale [0080]: the intermediate input matrix of transform coefficients is transposed to provide a transposed intermediate input matrix of transform coefficients. The transpose operation involves an interchanging of the rows and columns of the intermediate input matrix; Sadafale [0088]: The memory module 908 is configured to store the multimedia data subsequent to one of encoding of multimedia data and decoding of multimedia data)
[and wherein in the sixth step, the seventh step, and] the eighth step, [processing is repeated until all of the intermediate data is transformed and recorded in the auxiliary storage device as the final data] (Sadafale [0041]: the 2-D forward transform may be implemented as a cascade of 1-D transform steps 224, 228, with each 1-D transform followed by a transpose step 226, 230; Sadafale [0080]: the intermediate input matrix of transform coefficients is transposed to provide a transposed intermediate input matrix of transform coefficients. The transpose operation involves an interchanging of the rows and columns of the intermediate input matrix; Sadafale [0088]: The memory module 908 is configured to store the multimedia data subsequent to one of encoding of multimedia data and decoding of multimedia data).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teaching Liou with the writing the elements to output as taught by Sadafale. One of ordinary skill in the art would be motivated to make this combination because it also enables a saving of area and power in a system for decoding multimedia data to be achieved as taught by Sadafale (Sadafale [0048]).
With regards to claim 10, Liou in view of Sadafale teaches all of the limitations of claim 9 above. Liou fails to teach A non-transitory computer readable medium for storing instructions that, when executed by a computer, cause the computer to perform the method according to claim 9.
However, Sadafale teaches A non-transitory computer readable medium for storing instructions that, when executed by a computer, cause the computer to perform the method according to claim 9 (Sadafale [0091]: For example, the various systems, modules, etc., described herein may be enabled and operated using hardware circuitry (e.g., complementary metal oxide semiconductor (CMOS) based logic circuitry), firmware, software and/or any combination of hardware, firmware, and/or software (e.g., embodied in a machine readable medium)).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teaching Liou in view of Sadafale with the non-transitory computer readable medium as taught by Sadafale. One of ordinary skill in the art would be motivated to make this combination because it also enables a saving of area and power in a system for decoding multimedia data to be achieved as taught by Sadafale (Sadafale [0048]). Also, it would increase the flexibility of the system as it would allow for different instructions to be processed by the system.
With regards to claim 11, Liou teaches A two-dimensional data transform method, the method comprising: a first step of reading a first element group of one or more columns in a column direction of original data from an auxiliary storage device in which respective elements of the original data of M rows and N columns are continuously recorded in order in a row direction on the original data, wherein M and N are integers of 2 or greater; (Liou Column 2 Lines 51-68 and Column 3 Line 1: Our two-dimensional DCT processor comprises an input one-dimensional (N.times.1) Column DCT processor to which the N.times.N input data block is sequentially applied column by column… Each of the columns of the data matrix is applied to the input N.times.1 processor in sequence to produce the N.times.N intermediate matrix (Y))
a second step of performing one-dimensional transform on the first element group of each of the one or more columns read in the first step; (Liou Column 2 Lines 51-54: Our two-dimensional DCT processor comprises an input one-dimensional (N.times.1) Column DCT processor to which the N.times.N input data block is sequentially applied column by column)
a third step of writing the first element group of the one or more columns transformed in the second step into the auxiliary storage device as a second element group of one or more rows in the row direction of intermediate data of N rows and M columns; (Liou Column 2 Lines 62-68 and Column 3 Lines 1-4: The accumulators concurrently compute the elements of the column transform by shifting and adding of the data retrieved from the ROMs. The resultant intermediate vector is stored in one row of a N.times.N transposition memory which comprises a RAM. Each of the columns of the data matrix is applied to the input N.times.1 processor in sequence to produce the N.times.N intermediate matrix (Y) which is the product (X.sup.t C) of the transpose of the data matrix (X.sup.t) and the discrete cosine matrix (C) represented by the constants stored in the ROM)
a fourth step of reading a third element group of one or more columns in the column direction of the intermediate data from the auxiliary storage device after all of the original data is transformed and recorded in the auxiliary storage device as the intermediate data; (Liou Column 3 Lines 5-8: A second or output row N.times.1 DCT processor is then used to compute the one-dimensional N.times.1 DCT for each column of X.sup.t C, which is retrieved from storage in the memory)
a fifth step of performing one-dimensional transform on the third element group of each of the one or more columns read in the fourth step; (Liou Column 3 Lines 5-8: A second or output row N.times.1 DCT processor is then used to compute the one-dimensional N.times.1 DCT for each column of X.sup.t C, which is retrieved from storage in the memory)
wherein in the first step, the second step, and the third step, processing is repeated until all of the original data is transformed and recorded in the auxiliary storage device as the intermediate data; (Liou Column 2 Lines 62-68 and Column 3 Lines 1-4: The accumulators concurrently compute the elements of the column transform by shifting and adding of the data retrieved from the ROMs. The resultant intermediate vector is stored in one row of a N.times.N transposition memory which comprises a RAM. Each of the columns of the data matrix is applied to the input N.times.1 processor in sequence to produce the N.times.N intermediate matrix (Y) which is the product (X.sup.t C) of the transpose of the data matrix (X.sup.t) and the discrete cosine matrix (C) represented by the constants stored in the ROM)
and wherein in the fourth step, the fifth step, and [the sixth step], processing is repeated until all of the intermediate data is transformed and recorded in the auxiliary storage device as the final data (Liou Column 3 Lines 5-8: A second or output row N.times.1 DCT processor is then used to compute the one-dimensional N.times.1 DCT for each column of X.sup.t C, which is retrieved from storage in the memory).
Liou fails to teach and a sixth step of writing the third element group of the one or more columns transformed in the fifth step into the auxiliary storage device as a fourth element group of one or more rows in the row direction of final data of M rows and N columns; and [and wherein in the fourth step, the fifth step, and] the sixth step, [processing is repeated until all of the intermediate data is transformed and recorded in the auxiliary storage device as the final data].
However, Sadafale teaches and a sixth step of writing the third element group of the one or more columns transformed in the fifth step into the auxiliary storage device as a fourth element group of one or more rows in the row direction of final data of M rows and N columns; (Sadafale [0041]: the 2-D forward transform may be implemented as a cascade of 1-D transform steps 224, 228, with each 1-D transform followed by a transpose step 226, 230; Sadafale [0080]: the intermediate input matrix of transform coefficients is transposed to provide a transposed intermediate input matrix of transform coefficients. The transpose operation involves an interchanging of the rows and columns of the intermediate input matrix; Sadafale [0088]: The memory module 908 is configured to store the multimedia data subsequent to one of encoding of multimedia data and decoding of multimedia data)
[and wherein in the fourth step, the fifth step, and] the sixth step, [processing is repeated until all of the intermediate data is transformed and recorded in the auxiliary storage device as the final data] (Sadafale [0041]: the 2-D forward transform may be implemented as a cascade of 1-D transform steps 224, 228, with each 1-D transform followed by a transpose step 226, 230; Sadafale [0080]: the intermediate input matrix of transform coefficients is transposed to provide a transposed intermediate input matrix of transform coefficients. The transpose operation involves an interchanging of the rows and columns of the intermediate input matrix; Sadafale [0088]: The memory module 908 is configured to store the multimedia data subsequent to one of encoding of multimedia data and decoding of multimedia data).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teaching Liou with the writing the elements to output as taught by Sadafale. One of ordinary skill in the art would be motivated to make this combination because it also enables a saving of area and power in a system for decoding multimedia data to be achieved as taught by Sadafale (Sadafale [0048]).
With regards to claim 12, Liou in view of Sadafale teaches all of the limitations of claim 11 above. Liou fails to teach A non-transitory computer readable medium for storing instructions that, when executed by a computer, cause the computer to perform the method according to claim 11.
However, Sadafale teaches A non-transitory computer readable medium for storing instructions that, when executed by a computer, cause the computer to perform the method according to claim 11 (Sadafale [0091]: For example, the various systems, modules, etc., described herein may be enabled and operated using hardware circuitry (e.g., complementary metal oxide semiconductor (CMOS) based logic circuitry), firmware, software and/or any combination of hardware, firmware, and/or software (e.g., embodied in a machine readable medium)).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teaching Liou in view of Sadafale with the non-transitory computer readable medium as taught by Sadafale. One of ordinary skill in the art would be motivated to make this combination because it also enables a saving of area and power in a system for decoding multimedia data to be achieved as taught by Sadafale (Sadafale [0048]). Also, it would increase the flexibility of the system as it would allow for different instructions to be processed by the system.
Conclusion
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/J.O.G./Examiner, Art Unit 2151
/NICHOLAS KLICOS/Primary Examiner, Art Unit 2118
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