Detailed Action
The instant application having Application No. 18004442 has a total of 20 claims pending in the application; there are 3 independent claims and 17 dependent claims, all of which are ready for examination by the examiner. This Office action is in response to the claims filed 6/12/26. Claims 1-20 are pending.
NOTICE OF PRE-AIA OR AIA STATUS
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-7 and 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Schack (U.S. Patent Application Publication No. 2021/0182398), herein referred to as Schack and in view of Morgan (U.S. Patent No. 11,100,230), herein referred to as Morgan, and in view of Narasimhan et al. (U.S. Patent Application Publication No. 2019/0095623), herein referred to as Narasimhan et al. and in view of Nguyen et al. (U.S. Patent Application Publication No. 2006/0267172), herein referred to as Nguyen et al.
Referring to claim 1, Schack discloses as claimed, a computing device comprising: a first memory (see fig. 1, showing a volatile memory 190); a second memory to store initialization components (see fig. 1, showing a non-volatile storage containing installation packages), the initialization components comprising instructions for starting up the computing device (see para. 14, where the installation and firmware packages include an updated filesystem which controls how data is stored on a storage device and retrieved form the storage device. Para. 5 discusses how this process takes place during a boot of a device. Para. 35 and 58-63 disclose where during a reboot, updated installation packages and firmware are necessary for proper operation in some instances); and a processor to: load updated initialization components from an update package into the second memory (see para. 4, where the system includes a processor performing operations such as identifying installation packages and inserting them); wherein, prior to loading of the updated initialization components into the second memory, the second memory has a previous memory information set stored thereon to bring the first memory into the operational state (see fig. 2, where the updated installation package replaces an old installation package) wherein the updated initialization components comprise a common memory information set having information common to a plurality of memories (see para. 19, where the installation packages correspond to firmware, such as filesystem on nodes, which would constitute startup instructions and common memory information), and load the selected memory information set into the second memory to bring the first memory into an operational state (see fig. 4, step 435, where the firmware is loaded to the volatile memory. See para. 14, where the new filesystem controls how data is stored and retrieved form a storage device).
Schack discloses the claimed invention except for select a memory information set that corresponds to the first memory from amongst a plurality of memory information sets in the update package, wherein each of the plurality of memory information sets corresponds to a memory; a third memory, wherein the third memory is a private memory; and store at least one of a previous memory information set or the common memory information set in the third memory; wherein the selected memory information set specifies latencies that affect read and write speeds of the first memory.
However, Morgan discloses select a memory information set that corresponds to the first memory from amongst a plurality of memory information sets in the update package, wherein each of the plurality of memory information sets corresponds to a memory (see col. 4, lines 1-16 and col. 8, lines 4-26, where different sets of firmware correspond to different compute devices and memories);
Schack and Morgan are analogous art because they are from the same field of endeavor of firmware (see Schack, abstract, and see Morgan, abstract, regarding firmware).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Schack to comprise select a memory information set that corresponds to the first memory from amongst a plurality of memory information sets in the update package, wherein each of the plurality of memory information sets corresponds to a memory, as taught by Morgan, in order to support multiple different systems/devices and having updated firmware/installation package options for each of them.
Schack and Morgan disclose the claimed invention except for a third memory, wherein the third memory is a private memory; and store at least one of a previous memory information set or the common memory information set in the third memory; wherein the selected memory information set specifies latencies that affect read and write speeds of the first memory.
However, Narasimhan et al. disclose a third memory, wherein the third memory is a private memory (see fig. 1, showing a memory 110, a secure memory area 120, holding a copy of firmware and firmware storage device 114. See para. 15-16 and 28, where the secure memory area is designed to avoid compromising or corrupting the firmware); and store at least one of a previous memory information set or the common memory information set in the third memory (see para. 10, 17 and 31-33, where the secure memory area stores a copy of firmware 128 from the firmware storage device 114).
Schack and Narasimhan et al. are analogous art because they are from the same field of endeavor of firmware (see Schack, abstract, and see Narasimhan et al., abstract, regarding firmware).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Schack to comprise a third memory, wherein the third memory is a private memory; and store at least one of a previous memory information set or the common memory information set in the third memory, as taught by Narasimhan et al., in order to prevent the firmware from being compromised and insecure (see Narasimhan et al., para. 15).
Schack, Morgan and Narasimhan et al. disclose the claimed invention except for wherein the selected memory information set specifies latencies that affect read and write speeds of the first memory.
However, Nguyen et al. disclose herein the selected memory information set specifies latencies that affect read and write speeds of the first memory (see para. 6, where during boot up, a PC uses serial-presence-detect to read configuration information of a memory and then bring it to an operational state. The configuration information may include speed and latency).
Schack and Nguyen et al. are analogous art because they are from the same field of endeavor of memory devices (see Schack, abstract, and see Nguyen et al., abstract, regarding memory devices).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Schack to comprise the selected memory information set specifies latencies that affect read and write speeds of the first memory, as taught by Nguyen et al., in order to allow for each specific memory to be configured correctly using information specific to it.
As to claim 2, Schack, Morgan, Narasimhan et al. and Nguyen et al. also disclose the computing device of claim 1, further comprising a memory controller to bring the first memory into the operational state using the selected memory information set, subsequent to loading the selected memory information set into the second memory (see Morgan, fig. 1, showing both a management circuit and separate controllers for loading firmware into selected memories).
As to claim 5, Schack, Morgan, Narasimhan et al. and Nguyen et al. also disclose the computing device of claim 1, further comprising a storage, wherein, to load updated initialization components from the update package into the second memory, the processor is to: store the update package in a location in the storage that is earmarked for storing update packages (see Schack, fig. 1, showing a server storing update packages before sending them to a non-volatile storage); set an update flag to indicate that an update is ready to be loaded into the second memory (see Morgan, col. 6, lines 15-30, where a pin or electric potential provides an indicator that a host device is connected and firmware is ready to be provided); detect presence of the updated initialization components in the earmarked location based on the update flag during a subsequent boot sequence of the computing device (see Morgan, col. 8, lines 5-26, where each type of compute device is identified and it is determined if there is a matching firmware); and retrieve the updated initialization components from the earmarked location for loading into the second memory (see Schack, para. 35-36, where the firmware is copied from non-volatile memory to volatile memory).
As to claim 6, Schack, Morgan, Narasimhan et al. and Nguyen et al. also disclose the computing device of claim 1, wherein the first memory is a random access memory (RAM), and wherein the second memory is a non-volatile memory that is to be accessed by the processor during starting-up of the computing device (see Schack, fig. 1, showing a volatile memory 190 as the first memory and nonvolatile storage 180 as the second memory).
Referring to claim 7, Schack discloses as claimed, a computer-implemented method comprising: receiving an update package comprising initialization components and a memory information block (see fig. 2, where an installation package is sent and an older installation package is replaced. The installation package contains an updated filesystem as described in para. 5, which would contain memory information), the initialization components comprising start- up instructions usable for starting a computing device and a common memory information set usable for bringing the first memory of the computing device into the operational state (see para. 14, where the installation and firmware packages include an updated filesystem which controls how data is stored on a storage device and retrieved form the storage device. Para. 5 discusses how this process takes place during a boot of a device. Para. 35 and 58-63 disclose where during a reboot, updated installation packages and firmware are necessary for proper operation in some instances), loading the initialization components from the update package into a second memory of the computing device (see fig. 1 and 2, where installation packages are updated on non-volatile storage 180); wherein, prior to loading of the updated initialization components into the second memory, the second memory stores a previous memory information set usable to bring the first memory into the operational state (see fig. 2, where the updated installation package replaces an old installation package) wherein the common memory information set has information common to a plurality of memories (see para. 19, where the installation packages correspond to firmware, such as filesystem on nodes, which would constitute startup instructions and common memory information), loading the selected memory information set into the second memory (see fig. 2, where updated installation packages replace old installation packages on the non-volatile or second memory); and bringing the first memory into the operational state using the selected memory information set (see fig. 4, step 435, where the firmware is loaded to the volatile memory. See para. 14, where the new filesystem controls how data is stored and retrieved form a storage device).
Schack discloses the claimed invention except for the memory information block comprising a plurality of memory information sets, each memory information set corresponding to a memory; selecting a memory information set that corresponds to the first memory from amongst the plurality of memory information sets in the memory information block; storing at least one of the previous memory information set or the common memory information set in a third memory of a computing device, wherein the third memory is a private memory; wherein the selected memory information set specifies latencies that affect read and write speeds of the first memory.
However, Morgan discloses the memory information block comprising a plurality of memory information sets, each memory information set corresponding to a memory (see col. 4, lines 1-16 and col. 8, lines 4-26, where different sets of firmware correspond to different compute devices and memories); selecting a memory information set that corresponds to the first memory from amongst the plurality of memory information sets in the memory information block (see col. 4, lines 1-16 and col. 8, lines 4-26, where a specific firmware can be selected that matches a particular computing device);
Schack and Morgan are analogous art because they are from the same field of endeavor of firmware (see Schack, abstract, and see Morgan, abstract, regarding firmware).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Schack to comprise the memory information block comprising a plurality of memory information sets, each memory information set corresponding to a memory; selecting a memory information set that corresponds to the first memory from amongst the plurality of memory information sets in the memory information block, as taught by Morgan, in order to support multiple different systems/devices and having updated firmware/installation package options for each of them.
Schack and Morgan disclose the claimed invention except for storing at least one of the previous memory information set or the common memory information set in a third memory of a computing device, wherein the third memory is a private memory wherein the selected memory information set specifies latencies that affect read and write speeds of the first memory.
However, Narasimhan et al. disclose storing at least one of the previous memory information set or the common memory information set in a third memory of a computing device (see para. 10, 17 and 31-33, where the secure memory area stores a copy of firmware 128 from the firmware storage device 114), wherein the third memory is a private memory (see fig. 1, showing a memory 110, a secure memory area 120, holding a copy of firmware and firmware storage device 114. See para. 15-16 and 28, where the secure memory area is designed to avoid compromising or corrupting the firmware).
Schack and Narasimhan et al. are analogous art because they are from the same field of endeavor of firmware (see Schack, abstract, and see Narasimhan et al., abstract, regarding firmware).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Schack to comprise storing at least one of the previous memory information set or the common memory information set in a third memory of a computing device, wherein the third memory is a private memory, as taught by Narasimhan et al., in order to prevent the firmware from being compromised and insecure (see Narasimhan et al., para. 15).
Schack. Morgan and Narasimhan et al. disclose the claimed invention except for wherein the selected memory information set specifies latencies that affect read and write speeds of the first memory.
However, Nguyen et al. disclose herein the selected memory information set specifies latencies that affect read and write speeds of the first memory (see para. 6, where during boot up, a PC uses serial-presence-detect to read configuration information of a memory and then bring it to an operational state. The configuration information may include speed and latency).
Schack and Nguyen et al. are analogous art because they are from the same field of endeavor of memory devices (see Schack, abstract, and see Nguyen et al., abstract, regarding memory devices).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Schack to comprise the selected memory information set specifies latencies that affect read and write speeds of the first memory, as taught by Nguyen et al., in order to allow for each specific memory to be configured correctly using information specific to it.
As to claim 10, Schack, Morgan and Narasimhan et al. also disclose the method of claim 7, wherein selecting the memory information set that corresponds to the first memory comprises comparing an identifier corresponding to the first memory with a plurality of identifiers in the memory information block, wherein each identifier in the memory information block corresponds to a memory information set in the memory information block (see Morgan, col. 8, lines 4-26, where “each firmware is uniquely associated with a type of compute device.” Therefore the firmware is selected based on the type of compute device and whether it matches a specific firmware. Although not explicitly stated, the firmware would therefore need to have some type of unique identifier tying it to the compute device).
As to claim 11, Schack, Morgan, Narasimhan et al. and Nguyen et al. also disclose the method of claim 7, wherein the start-up instructions comprise instructions for Basic Input/ Output System (BIOS) or Unified Extensible Firmware Interface (UEFI) (see Morgan, col. 3, lines 56-60, where the set of firmware may be instructions for BIOS).
Referring to claim 12, Schack discloses as claimed, a non-transitory computer-readable medium comprising instructions for bringing a volatile memory of a computing device into an operational state , the instructions being executable by a processing resource to: load initialization components from an update package into a non- volatile memory of the computing device (see fig. 2, where an installation package is sent and an older installation package is replaced. The installation package contains an updated filesystem as described in para. 5, which would contain memory information. See fig. 1, showing the installation packages being loaded to a non-volatile memory), the initialization components comprising start-up instructions usable for starting a computing device and the update package further comprising a memory information block having a plurality of memory information sets (see para. 19, where the installation packages correspond to firmware, such as filesystem on nodes, which would constitute startup instructions and memory information); and load the selected memory information set into the non-volatile memory for bringing the memory into the operational state (see fig. 4, where a firmware update package is stored in nonvolatile storage and used for later loading into the volatile memory. See para. 14, where the installation and firmware packages include an updated filesystem which controls how data is stored on a storage device and retrieved form the storage device. Para. 5 discusses how this process takes place during a boot of a device. Para. 35 and 58-63 disclose where during a reboot, updated installation packages and firmware are necessary for proper operation in some instances); wherein, prior to loading of the updated initialization components into the second memory, the second memory has a previous memory information set stored thereon to bring the first memory into the operational state (see fig. 2, where the updated installation package replaces an old installation package) wherein the updated initialization components comprise a common memory information set having information common to a plurality of memories (see para. 19, where the installation packages correspond to firmware, such as filesystem on nodes, which would constitute startup instructions and common memory information),
Schack discloses the claimed invention except for select a memory information set that corresponds to the volatile memory from amongst the plurality of memory information sets; each memory information set corresponding to a volatile memory and being usable for bringing the volatile memory into the operational state; store at least one of the previous memory information set or the common memory information set in a third memory of a computing device, wherein the third memory is a private memory; wherein the selected memory information set specifies latencies that affect read and write speeds of the volatile memory.
However, Morgan discloses select a memory information set that corresponds to the volatile memory from amongst the plurality of memory information sets (see col. 4, lines 1-16 and col. 8, lines 4-26, where different sets of firmware correspond to different compute devices and memories); each memory information set corresponding to a volatile memory and being usable for operationalizing the volatile memory(see col. 4, lines 1-16 and col. 8, lines 4-26, where different sets of firmware correspond to different compute devices and memories).
Schack and Morgan are analogous art because they are from the same field of endeavor of firmware (see Schack, abstract, and see Morgan, abstract, regarding firmware).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Schack to comprise select a memory information set that corresponds to the volatile memory from amongst the plurality of memory information sets; each memory information set corresponding to a volatile memory and being usable for operationalizing the volatile memory, as taught by Morgan, in order to support multiple different systems/devices and having updated firmware/installation package options for each of them.
Schack and Morgan disclose the claimed invention except for store at least one of the previous memory information set or the common memory information set in a third memory of a computing device, wherein the third memory is a private memory; wherein the selected memory information set specifies latencies that affect read and write speeds of the volatile memory.
However, Narasimhan et al. disclose store at least one of the previous memory information set or the common memory information set in a third memory of a computing device (see para. 10, 17 and 31-33, where the secure memory area stores a copy of firmware 128 from the firmware storage device 114), wherein the third memory is a private memory (see fig. 1, showing a memory 110, a secure memory area 120, holding a copy of firmware and firmware storage device 114. See para. 15-16 and 28, where the secure memory area is designed to avoid compromising or corrupting the firmware).
Schack and Narasimhan et al. are analogous art because they are from the same field of endeavor of firmware (see Schack, abstract, and see Narasimhan et al., abstract, regarding firmware).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Schack to comprise store at least one of the previous memory information set or the common memory information set in a third memory of a computing device, wherein the third memory is a private memory, as taught by Narasimhan et al., in order to prevent the firmware from being compromised and insecure (see Narasimhan et al., para. 15).
Schack. Morgan and Narasimhan et al. disclose the claimed invention except for wherein the selected memory information set specifies latencies that affect read and write speeds of the volatile memory.
However, Nguyen et al. disclose herein the selected memory information set specifies latencies that affect read and write speeds of the volatile memory (see para. 6, where during boot up, a PC uses serial-presence-detect to read configuration information of a memory and then bring it to an operational state. The configuration information may include speed and latency).
Schack and Nguyen et al. are analogous art because they are from the same field of endeavor of memory devices (see Schack, abstract, and see Nguyen et al., abstract, regarding memory devices).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Schack to comprise the selected memory information set specifies latencies that affect read and write speeds of the volatile memory, as taught by Nguyen et al., in order to allow for each specific memory to be configured correctly using information specific to it.
As to claim 13, Schack, Morgan, Narasimhan et al. and Nguyen et al. also disclose the computer-readable medium of claim 12, further comprising instructions executable by the processing resource to: restart the computing device in response to loading the selected memory information set into the first non-volatile memory; and operationalize the volatile memory using the selected memory information set stored in the non-volatile memory upon the restarting (see Schack, fig. 4, where a reboot occurs after the information set has been updated in the non-volatile memory, then the computing device is rebooted, and the firmware is then loaded into the volatile memory after the reboot.).
As to claim 14, Schack, Morgan, Narasimhan et al. and Nguyen et al. also disclose the computer-readable medium of claim 12, further comprising instructions executable by the processing resource to: load the selected memory information set into the first non-volatile memory by replacing the common memory information set with the selected memory information set in the first non-volatile memory (see Morgan, col. 8, lines 4-26, where a specific type of firmware is matched to a specific compute device and then the firmware is updated to replace the previous firmware or common firmware).
Claims 3-4, 8-9 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Schack in view of Morgan and Narasimhan et al. and Nguyen et al. and in view of Park (U.S. Patent Application Publication No. 2020/0201617), herein referred to as Park.
As to claim 3, Schack, Morgan, Narasimhan et al. and Nguyen et al. disclose the claimed invention except for wherein the processor is to: store both the previous memory information set and the common memory information set in the third memory, wherein the processor is further to: replace the previous memory information set on the second memory with the common memory information set to load the updated initialization components into the second memory; and replace the common memory information set on the second memory with the selected memory information set to load the selected memory information set into the second memory.
However, Park discloses wherein the processor is to: store both the previous memory information set and the common memory information set in the third memory (see fig. 4, showing multiple versions of firmware stored in a memory. Also see para. 112, where a copy of the previous firmware is copied to a memory region), replace the previous memory information set on the second memory with the common memory information set to load the updated initialization components into the second memory (see para. 51, where the memory set being replaced would be replaced with the new or updated memory set. This could occur more than once); and replace the common memory information set on the second memory with the selected memory information set to load the selected memory information set into the second memory (see fig. 4, showing firmware being copied to different memory regions as new updates occur. When combined with Schack and Morgan, this would allow the selected memory information to be loaded and replace the previous version).
Schack and Park are analogous art because they are from the same field of endeavor of firmware (see Schack, abstract, and see Park, abstract, regarding firmware).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Schack to comprise wherein the processor is to: store both the previous memory information set and the common memory information set in the third memory, wherein the processor is further to: replace the previous memory information set on the second memory with the common memory information set to load the updated initialization components into the second memory; and replace the common memory information set on the second memory with the selected memory information set to load the selected memory information set into the second memory, as taught by Park, in order to keep a backup of previous versions to rollback to in case of errors.
As to claim 4, Schack, Morgan, Narasimhan et al. and Nguyen et al. and Park also disclose the computing device of claim 3, further comprising a controller (see Morgan, fig. 1, showing a management circuit as well as controllers), wherein, upon loading the selected memory information set into the second memory, the controller is to: determine if bringing of the first memory into the operational state using the selected memory information set is successful (see Schack, fig. 4, where after the firmware is sent to the volatile memory, it is revalidated and determined if it is valid); in response to a failed bringing of the first memory into the operational state, replace the selected memory information set with the previous memory information set in the second memory, for bringing of the first memory into the operational state using the previous memory information set (see Park, para. 122, where if the firmware load circuit fails to load, the backup firmware may be copied back to the location of the original or updated firmware); determine if bringing of the first memory into the operational state using the previous memory information set is successful; and in response to a failure to bring the first memory into the operational state using the previous memory information set, replace, in the second memory, the previous memory information set with the common memory information set, for bringing of the first memory into the operational state using the common memory information set (see para. 122, where it is determined if the firmware failed to load, and if the firmware load circuit fails to load, the backup firmware may be copied back to the location of the original or updated firmware).
As to claim 8, Schack, Morgan, Narasimhan et al. and Nguyen et al. disclose the claimed invention except for the method of claim 7, further comprising: storing the common memory information set in a third memory of the computing device; determining whether bringing of the first memory into the operational state using the selected memory information set is completed within a predetermined duration; in response to non-completion of the bringing of the first memory into the operational state within the predetermined duration, loading the common memory information set into the second memory; and bringing of the first memory into the operational state using the common memory information set.
However, Park discloses storing the common memory information set in a third memory of the computing device (see para. 112, where a copy of the previous firmware, which would be the common memory set, is copied to a different memory region); determining whether bringing of the first memory into the operational state using the selected memory information set is completed within a predetermined duration (see para. 122, where it is determined if the firmware fails to load, which would need to be given a predetermined duration); in response to non-completion of the bringing of the first memory into the operational state within the predetermined duration, loading the common memory information set into the second memory; and bringing of the first memory into the operational state using the common memory information set (see para.122, where if the firmware fails to load, the previous backup version is loaded back to where the default firmware was previously).
Schack and Park are analogous art because they are from the same field of endeavor of firmware (see Schack, abstract, and see Park, abstract, regarding firmware).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Schack to comprise storing the common memory information set in a third memory of the computing device; determining whether bringing of the first memory into the operational state using the selected memory information set is completed within a predetermined duration; in response to non-completion of the bringing of the first memory into the operational state within the predetermined duration, loading the common memory information set into the second memory; and bringing of the first memory into the operational state using the common memory information set, as taught by Park, in order to keep a backup of previous versions to rollback to in case of errors.
As to claim 9, Schack, Morgan, Narasimhan et al. and Nguyen et al. and Park also disclose the method of claim 7, wherein, prior to loading the initialization components into the second memory, the method comprises: determining if the memory information block comprises a memory information set corresponding to the first memory (see Morgan, col. 8 , lines 4-26, where each firmware is uniquely associated with a particular memory or compute deice); loading the initialization components into the second memory in response to the presence of the memory information set corresponding to the first memory in the memory information block (see Morgan, col. 8, lines 4-26, where if there is a match between the firmware and a compute device/memory, than the firmware is loaded); and determining that loading of the initialization components into the second memory is not to be performed in response to the absence of the memory information set corresponding to the first memory in the memory information block (see Morgan, col. 8, lines 4-26, where each firmware is uniquely associated with a particular memory. Therefore if the memory information for a certain firmware is not present than that firmware will not loaded into the first memory).
As to claim 15, Schack, Morgan, Narasimhan et al. and Nguyen et al. also disclose the computer-readable medium of claim 14, further comprising instructions executable by the processing resource to: bring the volatile memory into the operational state using the selected memory information set stored in the non-volatile memory (see Schack, fig. 4, step 435, where the firmware is loaded to the volatile memory. See para. 14, where the new filesystem controls how data is stored and retrieved form a storage device and would therefore be operationalized).
Schack, Morgan, Narasimhan et al. and Nguyen et al. disclose the claimed invention except for in response to non-completion of the bringing of the volatile memory into the operational state using the selected memory information set within a predetermined duration bring the first memory into the operational state using the common memory information set or a previous memory information.
However, Park discloses in response to non-completion of the operationalization of the volatile memory into the operational state using the selected memory information set within a predetermined duration (see para. 122, where it is determined if the firmware fails to load, which would need to be given a predetermined duration), bring the volatile memory into the operational state using the common memory information set or a previous memory information set, (see para.122, where if the firmware fails to load, the previous backup version is loaded back to where the default firmware was previously).
Schack and Park are analogous art because they are from the same field of endeavor of firmware (see Schack, abstract, and see Park, abstract, regarding firmware).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Schack to comprise in response to non-completion of the operationalization of the volatile memory within a predetermined duration, bring the volatile memory into the operational state using the common memory information set or a previous memory information set, as taught by Park, in order to keep a backup of previous versions to rollback to in case of errors.
As to claim 16, Schack, Morgan, Narasimhan et al. and Nguyen et al. also disclose the computing device of claim 1, wherein bringing the first memory into an operational state includes determining latencies that affect read and write speeds of the first memory (see Nguyen et al., para. 6, where during boot up, a PC uses serial-presence-detect to read configuration information of a memory and then bring it to an operational state. The configuration information may include speed and latency).
Claims 18 and 19 recite similar limitations to claim 16, and would be rejected using the same rationale.
As to claim 20, Schack, Morgan, Narasimhan et al. and Nguyen et al. also disclose the computer-readable medium of claim 12, wherein the plurality of memory information sets respectively include information in accordance with serial presence detect (SPD) (see para. 6, where during boot up, a PC uses serial-presence-detect to read configuration information of a memory and then bring it to an operational state. The configuration information may include speed and latency).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Schack in view of Morgan and Narasimhan et al. and Nguyen et al. and in view of Liu et al. (U.S. Patent Application Publication No. 2021/0004336), herein referred to as Liu et al.
As to claim 17, Schack, Morgan, Narasimhan et al. and Nguyen et al. disclose the claimed invention except for the computing device of claim 1, wherein the first memory and the second memory are directly soldered onto a motherboard of the computing device.
However, Liu et al. disclose wherein the first memory and the second memory are directly soldered onto a motherboard of the computing device (see para. 11, where the memory module is an on-board die soldered on a motherboard).
Schack and Liu et al. are analogous art because they are from the same field of endeavor of memory devices (see Schack, abstract, and see Liu et al., abstract, regarding memory devices).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Schack to comprise wherein the first memory and the second memory are directly soldered onto a motherboard of the computing device, as taught by Liu et al., in order to allow for higher performance, greater reliability and a more compact design. Soldering memory chips to motherboards is well known in the art and would be obvious to implement with Schack.
Response to Arguments
Applicant's arguments filed 6/12/26 have been fully considered but they are not persuasive.
Applicant argues that Nguyen teaches a dedicated flash memory to store configuration information for the RAM according to serial-presence detect (SPD). Applicant argues that the combination of Schack and Nguyen would include Nguyen’s flash memory as a dedicated memory for a RAM module with configuration information for that RAM and would be separate from Schack’s non-volatile storage, because of their different designs, functions and purposes.
However, Nguyen is being combined specifically to teach where a selected memory information set specifies latencies that affect read and write speeds of the memory. Schack already teaches loading firmware or a memory information set from a non-volatile memory device onto a volatile memory device to bring that memory into an operational state. Nguyen simply teaches where the memory information set specifies latencies that affect read and write speeds. Storing initialization information such as with serial presences detect is well known in the art and would be obvious to one of ordinary skill in the art. It allows for specific information about a memory to be accessed during startup and would be helpful in configuring or initializing a memory. The combination of Schack and Nguyen would not need to have 3 or 4 separate memories. Nguyen is being combined to teach that the memory information set can specify latencies that affect read and write speeds. It would be obvious to include that information in Schack’s memory information set.
CLOSING COMMENTS
Conclusion
a. STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
a(1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-20 stand rejected.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.O/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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