DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Figure 15 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Moore et al. (US 2019/0230304, cited in Applicant’s Information Disclose Statement) in view of Gimeno et al. (US 2024/0134014, with an effective filing date Feb. 15, 2021), and further in view of Sanchez et al. (US 2018/0332246).
With regard to claim 1, Moore discloses a ToF sensor (see Fig. 2A) comprising: a pixel area (204) that includes pixels arranged in an X direction and a Y direction; and a clock buffer area (vertical clock tree 252) arranged on one end side of the pixel area in the Y direction, wherein
unit pixel groups (micropixel 254) are two-dimensionally arranged in the pixel area (204), each of the unit pixel groups includes a plurality of pixels adjacent to each other in the X direction and/or the Y direction (para. [0039]), each of the pixels includes a photodiode (SPAD which stands for single-photon avalanche photodiode),
Moore does not specifically disclose a plurality of transfer gates, and a charge accumulation and output circuit, nor that the clock tree includes a clock buffer. However, Gimeno teach in the same field of endeavor, a ToF sensor with an array of photosensitive elements (e. g. photodiodes, equivalent to applicant’s pixels) arranged in an X direction and a Y direction (Fig. 1). Each photodiode is connected to a transfer gate that directs current to a capacitor, which is a charge accumulator (para. [0029]). These elements provide the function of controlling the charge, i. e. the memory of detected optical signal, required to obtain a ToF signal. Therefore, one skilled in the art, e. g. an optical engineer, would have found it obvious to include the additional elements taught by Gimeno for each photodiode (SPAD) in the ToF sensor of Moore.
Neither Moore nor Gimeno disclose that the plurality of clock signals are input into a clock buffer that drives the unit pixel group. However, Sanchez teach in the related field of high-speed imaging, a pixel array in which clock signals from a timing generator for obtaining the detected signals are provided by a binary clock tree (Fig. 6, replication tree 535 connected to pixel array 510 & para. [0072]). The clock signal passes through a series of buffers, including in particular for each row a buffer, e. g. row buffer stage (540). The buffers serve the purpose of providing sufficient power to drive the clock pulse across a large impedance (RC load, para. [0053]). The same requirement for clock pulse power across a large impedance would apply to each of the photodiodes in the ToF sensor array of Moore. Therefore, one skilled in the art, e. g. an electrical or optical engineer, would have found it obvious before the effective filing date of the application, to configure the buffers as part of the binary clock tree as taught by Sanchez, in the ToF sensor of Moore with the additional elements taught by Gimeno.
With regard to claims 2-4, Sanchez teaches that the clock buffer is arranged at each of the binary branch points of the clock signals which are binary branched in the horizontal (X) direction, and the output of the clock buffer is branched in two directions. It is clear from Fig. 6 that each piece of the wiring of the clock buffer is wired to a first branch point at a midpoint of the pixel area in the vertical (Y) direction, bifurcated and connected to the unit pixel groups on one end of the first branch point and the unit pixel groups on the other end side of the first branch point. The limitations of claim 4 regarding the distance between a branch point and a second branch point of claim 4 are obvious from the configuration of first branch point and second branch points shown in Fig. 6 of Sanchez.
With regard to claim 5, two unit pixel groups adjacent to each other with respect to the first branch point (stage 10) in the Y direction are connected to each other (Fig. 6)
Claim(s) 7 is rejected under 35 U.S.C. 103 as being unpatentable over Moore, Gimeno and Sanchez as applied to claims 1 and 3 above, and further in view of Iwane (US 2010/0097486). None of Moore, Gimeno, or Sanchez disclose that an upper wiring layer is used for wiring from an output of the clock buffer to the first branch point, and a lower wiring layer is used for wiring from the first branch point to the transfer gate of each unit pixel group. However, in the same field of endeavor Iwane teaches an image sensing device comprising an array of pixels (photodetectors), in which clock (timing signals, see Fig. 9) are provided to each pixel via wiring (Abstract); specifically, the photodetector (cross section para. [0056] and Fig. 3 ) is connected with a first wiring layer ML1, above a second wiring layer ML2. given the teaching of Iwane. Given the above idea of an upper wiring layer for one section of a circuit (in the instant case output of clock buffer) and a lower wiring layer for another part of the circuit (in the instant case from a branch point to the transfer gate) it would have been an obvious design choice of one skilled in the art before the effective filing date of the application, to apply to the pixel groups in the in the ToF sensor of Moore with the additional elements taught by Gimeno.
Allowable Subject Matter
Claim 6 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Information Disclosure Statement
The information disclosure statement filed on Jan. 9, 2023 and Sept. 6, 2024 have been considered by the Examiner.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Yasu disclose a sensor array with buffered clock tree.
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to ERIC L BOLDA whose telephone number is 571-272-8104. The examiner can normally be reached on M-F from 8:30am to 5pm.
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/ERIC L BOLDA/ Primary Examiner, Art Unit 3645