Prosecution Insights
Last updated: May 29, 2026
Application No. 18/005,386

LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF

Non-Final OA §102§103
Filed
Jan 13, 2023
Priority
Jul 21, 2020 — JP 2020-124695 +1 more
Examiner
ZHANG, YUANDA
Art Unit
2828
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Sony Semiconductor Solutions Corporation
OA Round
2 (Non-Final)
84%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
832 granted / 989 resolved
+16.1% vs TC avg
Moderate +12% lift
Without
With
+11.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
27 currently pending
Career history
1018
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
83.6%
+43.6% vs TC avg
§102
2.6%
-37.4% vs TC avg
§112
5.2%
-34.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 989 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment The Examiner acknowledges and accepts the amendment filed on 04/15/26. Claims 1 and 4 are amended; Claim 20 are newly added; and Claims 1-20 are currently pending. Response to Arguments Claims 1 and 4 Applicant’s arguments, see paragraph on mid page 9 of Remarks, filed 04/15/26, with respect to the rejection of claims 1 and 4 under 35 USC 102a2 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of a different interpretation of the previously applied reference Yu. In particular, the Examiner now interprets the conductive connector 210 of Yu to be the claimed bonding layer. Under this interpretation, Yu discloses the bonding layer 210 being directly disposed on and in directly physical contact with the first conductive layer 208. Therefore, Yu anticipates claims 1 and 4. Claims 12-13 Applicant’s arguments, see all paragraphs on page 10 of Remarks, filed 04/15/26, with respect to 35 USC 103 have been fully considered and are persuasive. The 103 rejections of claims 12-13 have been withdrawn. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-4, 8-11, 14-16 and 19 are rejected under 35 U.S.C. 102a2 as being anticipated by Yu et al. (US PG Pub 2020/0014169 A1, 01/20/23 IDS). Regarding claim 1, Yu discloses a light-emitting device (300, FIG. 9, [0032]), comprising: a first substrate (200, FIG. 9, [0029]) that outputs a drive signal for driving a light-emitting element (200 includes a semiconductor substrate 202 with devices such as transistors for driving laser devices 104, FIG. 9, [0029]); and a second substrate (100, FIG. 9, [0034]) that is laminated on the first substrate and includes the light-emitting element (100 is laminated on 200 including 104, FIG. 9), wherein a first surface side of the first substrate includes: a first pad (204A, FIG. 9, [0029]) that supplies the drive signal to the light-emitting element (“the cathodes of the laser devices 104 are connected to the pads 204A of the interconnect structure 204,” [0035]); a first conductive layer (208, FIG. 9, [0030]) disposed on the first pad; and a bonding layer (210, FIG. 9, [0031]) disposed directly on the first conductive layer, wherein the bonding layer is in direct physical contact with the first conductive layer (FIG. 9), and wherein a second surface side of the second substrate disposed to face the first surface of the first substrate includes: the light-emitting element having a mesa shape (104 has a mesa shape, FIG. 9); and a second pad (114, FIG. 9, [0017]) that is disposed on the light-emitting element and bonded to the first pad via the bonding layer (114 is bonded to 204A via 210, FIG. 9). PNG media_image1.png 408 711 media_image1.png Greyscale Regarding claim 2, Yu discloses the second surface side of the second substrate includes a second conductive layer (126, FIG. 9, [0026]) that is disposed on the second pad and bonded to the bonding layer (126 is disposed on 114 and bonded to 210, FIG. 9). Regarding claim 3, Yu discloses the first conductive layer is a barrier layer for the bonding layer (208 functions as a barrier layer, FIG. 9), and the bonding layer includes three or more metal layers sandwiching a nickel layer, or two or more metal layers including a nickel layer (“The conductive connectors 210 may be formed from a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, bismuth, the like, or a combination thereof,” [0031]). Regarding claim 4, Yu discloses a method for manufacturing a light-emitting device (300, FIG. 9, [0032]), comprising: forming an insulating film (206, FIG. 8, [0029]) on a first surface of a first substrate (200, FIG. 8, [0029]) including a surface of a first pad (204A, FIG. 9, [0029]) that outputs a drive signal for driving a light-emitting element (200 may include a semiconductor substrate 202 with devices such as transistors for driving laser devices 104, FIG. 9, [0029]); exposing an upper surface of the first pad by patterning the insulating film (an upper surface of 204A is exposed by an opening of 206, FIG. 8); forming a first conductive layer (208, FIG. 9, [0030]) on the insulating film and the first pad; forming a bonding layer (210, FIG. 9, [0031]) directly on the first conductive layer; wherein the bonding layer is in direct physical contact with the first conductive layer (FIG. 9); reflowing the bonding layer (“the conductive connectors 210 are formed by initially forming a layer of solder on the contact pads 208 through methods such as evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a layer of solder has been formed on the contact pads 208, a reflow may be performed in order to shape the material into desired bump shapes,” [0031]); and causing the first surface of the first substrate to face a second surface of a second substrate (FIG. 9) and bonding the first pad to a second pad (114, FIG. 9, [0017]) electrically connected to an anode electrode of the light-emitting element having a mesa shape (104 has a mesa shape, FIG. 7) formed on the second substrate via the bonding layer. Regarding claim 8, Yu discloses the first pad contains aluminum (204A may be formed from Al, [0029]), and the first conductive layer is a laminated film of titanium and copper (208 may be multilayered including Ti and Cu, [0030]). Regarding claim 9, Yu discloses in the forming of the first conductive layer, a metal layer containing titanium is formed on the first pad and a metal layer containing copper is formed thereon (208 may be multilayered including Ti and Cu, [0030]), and the bonding layer is formed on the metal layer containing copper (126 contains Cu, [0026]). Regarding claim 10, Yu discloses the bonding layer is a laminated film containing at least one of tin and copper (“The conductive connectors 210 may be formed from a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, bismuth, the like, or a combination thereof,” [0031]). Regarding claim 11, Yu discloses the bonding layer is formed of three or more metal layers sandwiching a nickel layer, or two or more metal layers including a nickel layer (“The conductive connectors 210 may be formed from a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, bismuth, the like, or a combination thereof,” [0031]). Regarding claim 14, Yu discloses forming a second conductive layer (126, FIG. 9, [0026]) on the second pad of the second substrate; and causing the first surface of the first substrate to face the second surface of the second substrate and bonding the bonding layer of the first substrate to the second conductive layer (FIG. 9). Regarding claim 15, Yu discloses a diameter size of the second conductive layer is equal to or larger than a diameter size of the bonding layer (a diameter of a lower part of 126 is substantially equal to a diameter of an upper part of 210, FIG. 9). Regarding claim 16, Yu discloses the first substrate is a wafer (FIG. 9, [0029]), and chip on wafer (CoW) connection is performed in the bonding of the bonding layer of the first substrate to the second conductive layer (a system-on-chip, FIG. 9, [0032]). Regarding claim 19, Yu discloses injecting an insulating material (306, FIG. 12, [0040]) between the first substrate and the second substrate after bonding the bonding layer of the first substrate to the second conductive layer. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (US PG Pub 2010/0230810 A1, 01/11/26 IDS). Regarding claim 5, Yu has disclosed the method outlined in the rejection to claim 4 above except forming a resist film on the first conductive layer after forming the first conductive layer on the first pad; patterning the resist film such that the first conductive layer above the first pad is exposed; forming the bonding layer on the exposed first conductive layer; and removing the resist film. Kang discloses forming a resist film (170, FIG. 6, [0050]) on the first conductive layer (130, FIG. 5, [0050]) after forming the first conductive layer on the first pad (110, FIG. 5, [0050]); patterning the resist film such that the first conductive layer above the first pad is exposed (170 is patterned with an opening part 172, FIG. 6); forming the bonding layer (140, FIG. 7, [0051]) on the exposed first conductive layer; and removing the resist film (FIG. 8, [0055]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Yu with the steps of forming the resist film, patterning the resist film, forming the resist film on the exposed first conductive layer, and removing the resist film as taught by Kang in order to improve the adhesive strength of the solder bump and the reliability in the flip chip bump structure (see abstract of Kang). Regarding claim 6, Yu, as modified, discloses removing a portion of the first conductive layer after removing the resist film (FIG. 9 of Kang), wherein the reflowing of the bonding layer is performed after removing the portion of the first conductive layer (FIGS. 10-11 of Kang). Regarding claim 7, the combination has disclosed the method outlined in the rejection to claim 6 above except the removing of the portion of the first conductive layer is performed by wet etching. It would have been an obvious matter of design choice before the effective filing date of the claimed invention to modify the method of the combination with the removing of the portion of the first conductive layer being performed by wet etching in order to obtain fast etch rate. Allowable Subject Matter Claim 20 is allowed. Claims 12-13 and 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to YUANDA ZHANG whose telephone number is (571)270-1439. The examiner can normally be reached M-F 10:30 AM - 6:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MINSUN HARVEY can be reached at (571)272-1835. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /YUANDA ZHANG/Primary Examiner, Art Unit 2828
Read full office action

Prosecution Timeline

Jan 13, 2023
Application Filed
Jan 16, 2026
Non-Final Rejection mailed — §102, §103
Apr 15, 2026
Response Filed
May 07, 2026
Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12640534
METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE, BONDING METHOD, AND LIGHT EMITTING DEVICE
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Patent 12633723
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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
84%
Grant Probability
96%
With Interview (+11.9%)
2y 4m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 989 resolved cases by this examiner. Grant probability derived from career allowance rate.

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