DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 8-11, 14-16 and 19 are rejected under 35 U.S.C. 102a2 as being anticipated by Yu et al. (US PG Pub 2020/0014169 A1, 01/20/23 IDS).
Regarding claim 1, Yu discloses a light-emitting device (300, FIG. 9, [0032]), comprising:
a first substrate (200, FIG. 9, [0029]) that outputs a drive signal for driving a light-emitting element (200 includes a semiconductor substrate 202 with devices such as transistors for driving laser devices 104, FIG. 9, [0029]); and
a second substrate (100, FIG. 9, [0034]) that is laminated on the first substrate and includes the light-emitting element (100 is laminated on 200 including 104, FIG. 9),
wherein a first surface side of the first substrate includes:
a first pad (204A, FIG. 9, [0029]) that supplies the drive signal to the light-emitting element (“the cathodes of the laser devices 104 are connected to the pads 204A of the interconnect structure 204,” [0035]);
a first conductive layer (208, FIG. 9, [0030]) disposed on the first pad; and
a bonding layer (126, FIG. 9, [0026]) disposed on the first conductive layer, and
a second surface side of the second substrate disposed to face the first surface of the first substrate includes:
the light-emitting element having a mesa shape (104 has a mesa shape, FIG. 9); and
a second pad (114, FIG. 9, [0017]) that is disposed on the light-emitting element and bonded to the first pad via the bonding layer (114 is bonded to 204A via 126, FIG. 9).
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Regarding claim 2, Yu discloses the second surface side of the second substrate includes a second conductive layer (210, FIG. 9, [0031]) that is disposed on the second pad and bonded to the bonding layer (210 is disposed on 114 and bonded to 126, FIG. 9).
Regarding claim 3, Yu discloses the first conductive layer is a barrier layer for the bonding layer (208 functions as a barrier layer, FIG. 9), and the bonding layer includes three or more metal layers sandwiching a nickel layer, or two or more metal layers including a nickel layer (126 may be a composite layer including multiple sub-layers including Ni, [0026]).
Regarding claim 4, Yu discloses a method for manufacturing a light-emitting device (300, FIG. 9, [0032]), comprising:
forming an insulating film (206, FIG. 8, [0029]) on a first surface of a first substrate (200, FIG. 8, [0029]) including a surface of a first pad (204A, FIG. 9, [0029]) that outputs a drive signal for driving a light-emitting element (200 may include a semiconductor substrate 202 with devices such as transistors for driving laser devices 104, FIG. 9, [0029]);
exposing an upper surface of the first pad by patterning the insulating film (an upper surface of 204A is exposed by an opening of 206, FIG. 8);
forming a first conductive layer (208, FIG. 9, [0030]) on the insulating film and the first pad;
forming a bonding layer (126, FIG. 9, [0026]) on the first conductive layer;
reflowing the bonding layer (“a reflow performed to physically and electrically couple the UBMs 126 and conductive connectors 210,” [0034]); and
causing the first surface of the first substrate to face a second surface of a second substrate (FIG. 9) and bonding the first pad to a second pad (114, FIG. 9, [0017]) electrically connected to an anode electrode of the light-emitting element having a mesa shape (104 has a mesa shape, FIG. 7) formed on the second substrate via the bonding layer.
Regarding claim 8, Yu discloses the first pad contains aluminum (204A may be formed from Al, [0029]), and the first conductive layer is a laminated film of titanium and copper (208 may be multilayered including Ti and Cu, [0030]).
Regarding claim 9, Yu discloses in the forming of the first conductive layer, a metal layer containing titanium is formed on the first pad and a metal layer containing copper is formed thereon (208 may be multilayered including Ti and Cu, [0030]), and the bonding layer is formed on the metal layer containing copper (126 contains Cu, [0026]).
Regarding claim 10, Yu discloses the bonding layer is a laminated film containing at least one of tin and copper (126 may be a composite layer that includes multiple sub-layers containing Cu, [0026]).
Regarding claim 11, Yu discloses the bonding layer is formed of three or more metal layers sandwiching a nickel layer, or two or more metal layers including a nickel layer (126 may be a composite layer that includes multiple sub-layers containing Ni, [0026]).
Regarding claim 14, Yu discloses forming a second conductive layer (210, FIG. 9, [0031]) on the second pad of the second substrate; and causing the first surface of the first substrate to face the second surface of the second substrate and bonding the bonding layer of the first substrate to the second conductive layer (FIG. 9).
Regarding claim 15, Yu discloses a diameter size of the second conductive layer is equal to or larger than a diameter size of the bonding layer (a diameter of 210 is slightly larger than a diameter of 126, FIG. 9).
Regarding claim 16, Yu discloses the first substrate is a wafer (FIG. 9, [0029]), and chip on wafer (CoW) connection is performed in the bonding of the bonding layer of the first substrate to the second conductive layer (a system-on-chip, FIG. 9, [0032]).
Regarding claim 19, Yu discloses injecting an insulating material (306, FIG. 12, [0040]) between the first substrate and the second substrate after bonding the bonding layer of the first substrate to the second conductive layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (US PG Pub 2010/0230810 A1, 01/11/26 IDS).
Regarding claim 5, Yu has disclosed the method outlined in the rejection to claim 4 above except forming a resist film on the first conductive layer after forming the first conductive layer on the first pad; patterning the resist film such that the first conductive layer above the first pad is exposed; forming the bonding layer on the exposed first conductive layer; and removing the resist film. Kang discloses forming a resist film (170, FIG. 6, [0050]) on the first conductive layer (130, FIG. 5, [0050]) after forming the first conductive layer on the first pad (110, FIG. 5, [0050]); patterning the resist film such that the first conductive layer above the first pad is exposed (170 is patterned with an opening part 172, FIG. 6); forming the bonding layer (140, FIG. 7, [0051]) on the exposed first conductive layer; and removing the resist film (FIG. 8, [0055]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Yu with the steps of forming the resist film, patterning the resist film, forming the resist film on the exposed first conductive layer, and removing the resist film as taught by Kang in order to improve the adhesive strength of the solder bump and the reliability in the flip chip bump structure (see abstract of Kang).
Regarding claim 6, Yu, as modified, discloses removing a portion of the first conductive layer after removing the resist film (FIG. 9 of Kang), wherein the reflowing of the bonding layer is performed after removing the portion of the first conductive layer (FIGS. 10-11 of Kang).
Regarding claim 7, the combination has disclosed the method outlined in the rejection to claim 6 above except the removing of the portion of the first conductive layer is performed by wet etching. It would have been an obvious matter of design choice before the effective filing date of the claimed invention to modify the method of the combination with the removing of the portion of the first conductive layer being performed by wet etching in order to obtain fast etch rate.
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al.
Regarding claim 12, Yu has disclosed the method outlined in the rejection to claim 11 above except the bonding layer is formed by laminating a first metal layer containing copper on the first conductive layer, laminating a second metal layer containing nickel on the first metal layer, and laminating a third metal layer containing tin on the second metal layer. It would have been an obvious matter of design choice before the effective filing date of the claimed invention to modify the bonding layer of Yu with formed by laminating a first metal layer containing copper on the first conductive layer, laminating a second metal layer containing nickel on the first metal layer, and laminating a third metal layer containing tin on the second metal layer in order to obtain desired bonding strength and thermal conductivity.
Regarding claim 13, Yu has disclosed the method outlined in the rejection to claim 11 above except the bonding layer is formed by laminating a first metal layer containing nickel on the first conductive layer and laminating a second metal layer containing tin on the first metal layer. It would have been an obvious matter of design choice before the effective filing date of the claimed invention to modify the bonding layer of Yu with formed by laminating a first metal layer containing nickel on the first conductive layer and laminating a second metal layer containing tin on the first metal layer in order to obtain desired bonding strength and thermal conductivity.
Allowable Subject Matter
Claims 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: the cited prior art fails to disclose or suggest the steps of “individualizing the plurality of light-emitting elements after forming the second conductive layer, and the bonding of the bonding layer of the first substrate to the second conductive layer is performed after individualizing the plurality of light-emitting elements” as recited in claim 17. In particular, Yu merely discloses individualizing of the plurality of light emitting elements by forming a plurality of laser devices 104 with respective mesas (FIG. 7), but fails to disclose or suggest the individualizing after forming the second conductive layer and the bonding of the bonding layer of the first substrate to the second conductive layer is performed after the individualizing step. Therefore, claim 17 is allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and claim 18 is also allowable as it directly depends on claim 17.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yu et al. (US PG Pub 2019/0252312 A1) discloses a light-emitting device comprising a plurality of light emitting elements flip-chip bonded to a wafer for providing a drive signal to the light emitting elements (see FIG. 5-6).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YUANDA ZHANG whose telephone number is (571)270-1439. The examiner can normally be reached M-F 10:30 AM - 6:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MINSUN HARVEY can be reached at (571)272-1835. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YUANDA ZHANG/Primary Examiner, Art Unit 2828