DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Response to Amendment
The amendment filed September 23, 2026 has been entered. Claims 6, 8, and 11-13 remain pending in this application. Claims 1-5, 7, and 9-10 have been cancelled at applicant’s request. Claim 6 has been amended. Claims 11-13 have been added. No new matter has been added.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 6, 8, and 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0279597 A1 to Jian-Ping Wang, et al. (hereafter Wang) in view of US 2019/0258482 A1 to Akhilesh Ramlaut Jaiswal, et al. (hereafter Jaiswal) and further in view of US 2021/0210127 A1 to Marc Drouard, et al. (hereafter Drouard).
Regarding Amended Independent Claim 6, Wang discloses a method for calculating a Hamming distance based on the spin orbit torque magnetic random access memory array (A spin orbit torque memory device wherein cells comprise a magnetic tunnel junction, a first transistor coupled to the bottom of the MTJ, a second transistor couple to the top of the MTJ, and relevant Read, Write, and Source lines: Wang, Figure 3 and ¶¶[0048-49]),
wherein the spin orbit torque magnetic random access memory array comprises:
m write word lines, m read word lines, n write bit lines, n read bit lines, n source lines, and n rows and n columns of memory cells (Wang, Figure 3; as modified by Drouard, Figure 3b),
wherein the memory cell is a spin orbit torque magnetic random access memory cell, and each of m and n is a positive integer (Wang, Figure 3);
each memory cell located in the same column is connected to the same write bit line (Depicted horizontally, Wang, Figure 3),
each memory cell located in the same column is connected to the same read bit line (Depicted horizontally, Wang, Figure 3), and
each memory cell located in the same row is connected to the same write word line (Depicted vertically, Wang, Figure 3), and
each memory cell located in the same row is connected to the same read word line (Depicted vertically, Wang, Figure 3);
wherein the spin orbit torque magnetic random access memory cell comprises a magnetic tunnel junction (Wang, ¶[0042]);
a first transistor, a drain terminal of the first transistor being connected to a bottom of the magnetic tunnel junction (Wang, ¶[0042] and Figure 3); and
a second transistor, a drain terminal of the second transistor being connected to a top of the magnetic tunnel junction (Wang, ¶[0042] and Figure 3);
wherein the method comprises:
turning on the second transistor (Second transistor: Wang, Figure 3) and injecting an initialization current (Injecting an initialization current: Wang, ¶[0045]),
so that the magnetic tunnel junction produces a spin transfer torque effect (Setting the orientation of the magnetic moment: Wang, ¶[0045]) and
the magnetic tunnel junction is initialized to a high resistance state (Setting to a high resistance state: Wang, ¶[0044]);
encoding
performing an in-memory XOR operation on the first binary string information and the second binary string information (Performing an XOR comparison of data: Wang, ¶[0107]), and
storing in-memory XOR operation results in the spin orbit torque magnetic random access memory array (Storing the results of the operation back to an array cell: Wang, ¶[0053]); and
turning on the second transistor controlled by the bit read line,
reading the in-memory XOR operation results stored in the spin orbit torque magnetic random access memory array according to a voltage difference between the source line and the read bit line (Turning on the read resistor and reading the corresponding data: Wang, ¶[0051]), and
determining the Hamming distance (Performing a bitwise comparison to determine similarity: Wang, ¶[0110]),
wherein the in-memory XOR operation results are stored in the spin orbit torque magnetic random access memory cells (Wang, ¶[0085]) located in a diagonal of the spin orbit torque magnetic random access memory array (Wang, ¶[0077]; Note, while Wang does not expressly disclose storing XOR operation results in a diagonal, it does teach storing each match bit in a selected cell of the array and subsequently calculating the similarity based on that data. Selecting diagonal cells is one obvious layout for the stored results, analogous to Wang’s placement of Cout in a designated column, and constitutes a rearrangement of parts not holding patentable significance).
Wang discloses separate even and odd select lines along each column, where the even select lines are connected to even cells and odd select lines are connected to odd cells; Note, columns in Wang are depicted horizontally and rows are depicted vertically (Wang, ¶[0049]). Wang does not, therefore, depict a conventional memory array wherein all cells in a column are connected to a common source line. Drouard, however, discloses a conventional memory array wherein each memory cell located in the same column is connected to the same source line (Drouard, Figure 3b), which Drouard refers to as the state of the prior art (Drouard, Figure 3b). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to interpret the method of Wang when applied to the conventional memory array of Drouard, with a reasonable expectation of success. Both inventions are well known in the field of SOT ferromagnetic memory cell arrays and the combination of known inventions with predictable results is obvious and not patentable.
Wang discloses performing an XOR using computational RAM, not encoding both strings as voltages on the write bit line and the source line of the result cell. Jaiswal, however, discloses a spin-torque memory cell array wherein:
a first binary string information and a second binary string information in the write bit line and the source line, respectively, turning on the first transistor (Performing an XOR operation by driving a first binary operand to an array line, enabling the cell transistor, and writing the XOR into the cell: Jaiswal, ¶[0049]).
Jaiswal teaches this line-voltage operand encoding method saves energy on average (~50%) as no energy as both the SL and the BL are zero volts unless the bits differ (Jaiswal, ¶[0050]). A person having ordinary skill in the art, before the effective filing date of this application, would have been motivated to combine the efficient XOR line-voltage operand method of Jaiswal to Wang’s existing WBL-SL write path architecture, with a reasonable expectation of success. Using both ends of the SOT channel (WBL and SL) rather than a single line is a natural extension of Jaiswal’s three-terminal SOT cell. Both inventions are well known in the field of spin-torque memory cell operands and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 8, Wang discloses the method for calculating a Hamming distance according to claim 6, wherein
the first binary string information and the second binary string information comprise N-bit characters, and N is a positive integer (The similarity output string matches the N number of source lines: Wang, Figure 13).
Regarding New Claim 11, Wang discloses the method for calculating a Hamming distance according to Claim 6, wherein the magnetic tunnel junction comprises:
a spin orbit coupling layer, a ferromagnetic free layer, a tunneling layer, a ferromagnetic reference layer, and a top electrode layer, from bottom to top; the drain terminal of the first transistor is connected with the spin orbit coupling layer, and the drain terminal of the second transistor is connected with the top electrode layer (Wang, ¶[0042]).
Regarding New Claim 12, Wang discloses the method for calculating a Hamming distance according to Claim 11, wherein
each of the ferromagnetic free layer and the ferromagnetic reference layer is composed of a material with perpendicular magnetic anisotropy, and the material with perpendicular magnetic anisotropy is any one of CoFeB, Co2FeAl,Co, CoFe, Fe3GeTe2 and Ni3GeTe2 (Wang, Table 2).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0279597 A1 to Jian-Ping Wang, et al. (hereafter Wang), US 2019/0258482 A1 to Akhilesh Ramlaut Jaiswal, et al. (hereafter Jaiswal), and US 2021/0210127 A1 to Marc Drouard, et al. (hereafter Drouard), further in view of US 11,069,390 B2 to Jiamian Hu, et al. (hereafter Hu).
Regarding New Claim 13, Wang discloses the method for calculating a Hamming distance according to Claim 11, but fails to disclose the further limitations of Claim 13. Hu, however, discloses a ferromagnetic memory cell, wherein,
Dzyaloshinskii-Moriya interaction coefficient between the spin orbit coupling layer and the ferromagnetic free layer is 0.1 to 1 mJ/m2 (Hu, col.8:13-26 and Hu, Table 2).
Hu teaches the range of 0.2 to 3.2 mJ/m2 achieves deterministic perpendicular magnetization switching at the widest range of the lateral size of the CoFeB layer, with the most flexibility at the lower end of that range. Picking a range of 0.1 to 1 mJ/m2 constitutes a routine optimization of a known result-effective coefficient without any new showing of criticality for the claimed endpoints and is therefore obvious over the prior art. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of this application to apply the 0.2 to 3.2 mJ/m2 range Hu to the method of Wang, with a reasonable expectation of success. Both inventions are well known in the field of ferromagnetic memory element arrays, and the combination of known inventions with predictable results is obvious and not patentable.
Response to Arguments
Applicant's arguments filed September 23, 2026 have been fully considered but they are not persuasive.
Applicant begins by arguing Wang fails to disclose, “the in-memory XOR operation results are stored in the spin orbit torque magnetic random access memory cells located in a diagonal of the spin orbit torque magnetic random access memory array.” (Applicant’s Arguments/Remarks, p. 6 ¶1). Wang also makes use of even/odd source lines for controlling columns of memory cells. Once this difference between Wang and the present invention is accounted for, as is taught by Drouard to be the common expectation of a person having ordinary skill in the art, this difference is minimized, if not eliminated.
Even were this not the case, the present invention would still be obvious over Wang. Once one XOR bit is produced through a comparison of two N-bit strings, those N bits have to occupy N cells. Wang already has an m-by-n memory array and column shared source bit and source lines. Putting bit I in cell (i,i) does not change change the transistor that is turned on, the current path, the present, or the final count. It is the same type of choice Wang already makes when it places Cout in column 1108 rather than 1102, for example. A diagonal is one such reasonable assignment, but is only one such example and not an inherently new function. Wang teaches storing each match bit in a selected cell of the array and counting the 1s. Selecting the diagonal cells for those bits is an obvious layout of that stored result, analogous to Wang’s placement of Cout in a designated column. This argument is therefore unpersuasive.
Applicant further argues Wang fails on a more basic level, in that it doesn’t calculate, or even mention, Hamming distance (Applicant’s Arguments/Remarks, p. 6 ¶3). This is a specious distinction, however. Wang discloses identifying a similarity score, mathematically equivalent to the Hamming distance. One counts the number of matches, the other the number of mismatches, and each is equal to N minus the other. Therefore, this argument is unpersuasive.
Applicant’s remaining arguments filed with respect to the claims have been fully considered but are thought to be fully addressed by the modified and new grounds of rejections above. Applicant’s response is considered to be a bona fide attempt at a response and is being accepted as a complete response.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824
/PHO M LUU/Primary Examiner, Art Unit 2824
