DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement, filed December 2 2022, fails to comply with 37 CFR 1.98(a)(2), which requires a legible copy of each cited foreign patent document; each non-patent literature publication or that portion which caused it to be listed; and all other information or that portion which caused it to be listed. It has been placed in the application file, but the information referred to therein has not been considered. Applicant is advised to cite the written opinion with a copy of the written opinion provided.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). See the rejection under 35 U.S.C. 112 below.
Drawings
The drawings are objected for failing to comply with PCT Rule 11.13(a), which requires the drawings be in black, and that all drawings be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, solid black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. The weight of all lines and letters must be heavy enough to permit adequate reproduction. This requirement applies to all lines however fine, to shading, and to lines representing cut surfaces in sectional views. When blurry, non-thick lines are seen on the drawings and submitted to the USPTO, the blurry lines become pixelated. Applicant is advised that the drawings are to be re-drawn with durable, clean, solid black, sufficiently dense and dark, and uniformly thick and well-defined lines.
The drawings are further objected for failing to comply with PCT Rule 11.13(h), which requires that the height of the numbers and letters shall not be less than 0.32 cm. Examiner believes the letters and numbers in the drawings do not meet this requirement, although they have not measured every letter and number.
The drawings are objected to because of the minor informalities:
Fig. 8: Within the PE#i+1 segment of the figure, there exists a tile that uses dashed lines compared to the tiles around it. Examiner believes that this is an error and should be addressed.
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 13 is objected to because of the following informalities:
Line 2: Insert “the” before “specific” for clarity.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“first controller... control the first operation unit… data network controlled… control signal transmitted…” in claim 1 invoke 112(f). However, Examiner could not find the corresponding structure in the specification or drawings. Examiner finds the function supported by the first controller (e.g. [00106]), but could not find any structural support to conclude the structure of the first controller. For the purposes of prior art examination, Examiner is interpreting as any circuit that performs the function.
“second controller… control the second operation unit…” in claim 1 invokes 112(f). However, Examiner could not find the corresponding structure in the specification or drawings. Examiner finds the function supported by the second controller (e.g. [00106]), but could not find any structural support to conclude the structure of the second controller. For the purposes of prior art examination, Examiner is interpreting as any circuit that performs the function.
“controller of the first PE… controlling a data network” in claim 9 invokes 112(f). However, Examiner could not find the corresponding structure in the specification or drawings. Examiner finds the function supported by the controller of the first PE (e.g. [00105]), but could not find any structural support to conclude the structure of the controller of the first PE. For the purposes of prior art examination, Examiner is interpreting as any circuit that performs the function.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3-9, and 11-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 14, where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “patch” and “patches” in claim 14 is used by the claim to mean “to get or to retrieve something,” while the accepted meaning is “to apply a patch to (a computer program)” or “ to connect (things, such as circuits) by a patch cord” (definitions from Merriam Webster). The term is indefinite because the specification does not clearly redefine the term. For the sake of examination, Examiner will interpret “patch” as “fetch” and “patches” as “fetches”.
Claims 1 and 9 contain the claim limitations “first controller”, “second controller”, and/or “controller of the first PE”, which invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The specification is devoid of adequate structure to perform the claimed function. In particular, the specification states that the claimed functions are done by the “first controller”, “second controller”, or “controller of the first PE”. The use of the term “first controller”, “second controller”, and “controller of the first PE” is not adequate structure for performing the claimed functions mentioned previously because it does not describe a particular structure for performing the functions. The specification does not provide sufficient details such that one of ordinary skill in the art would understand which structure would perform the claimed function. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Claims 3-8 and 11-17 are rejected for inheriting the rejection of the claims in which they depend on.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 3-9, and 11-17 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 1 and 9, as described above, the disclosure does not provide adequate structure to perform the claimed functions of controlling the first operation unit, controlling the data network, transmitting the control signal, or controlling the second operation unit. The application does not demonstrate that the applicant has made an invention that achieves the claimed functions because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention.
Claims 3-8 and 11-17 are rejected for inheriting the rejection of the claims in which they depend on.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-6, 9, 14, and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Eisen et al. (US 20160202991 A1) in view of Dolly et al. (US 20180046916 A1).
Regarding claim 1, Eisen teaches a device for (Fig. 3: Processor core 20), the device comprising:
a first processing element (PE) comprising a first operation unit and a first controller configured to control the first operation unit (Fig. 3 and [0021-0022]: Disp0 (dispatch queue), ES0 (execution slice), LS0 (load-store slice), and CS0 (cache slice) as the first processing element. Disp0 and the hardware to control dispatching as the first controller, which controls instructions to be dispatched to ES0. ES0 as the operation unit); and
a second PE comprising a second operation unit and a second controller configured to control the second operation unit (Fig. 3 and [0021-0022]: Disp1, ES1, LS1, and CS1 as the second processing element. Disp1 and the hardware to control dispatching as the second controller, which controls instructions to be dispatched to ES1. ES1 as the second operation unit),
wherein the first PE and the second PE are reconfigured into one fused PE for parallel processing
wherein first operators included in the first operation unit and second operators included in the second operation unit form a data network, and the data network is controlled based on control signals of the first controller in the fused PE (Fig. 6 and [0026, 0029]: Execution slices 42AA and 42BB (which can correlate to ES0 and ES1) are connected via an execution interlock control, which provides coordination between the slices to support a single instruction stream between the slices. Disp0 dispatches instructions to either ES0 or ES1 through the dispatch routing network 36, which is then processed by the slice and placed in the execution reservation stations 73 of the respective execution slice, and from there, the execution slices coordinate the execution of the single instruction. Therefore, the instructions controls the data network. Execution reservation station as the operators since they operate instructions into the execution pipelines 74A-C and 72. The wires from the execution reservation stations connecting to the execution pipelines and the execution interlock control as the data network. The instructions as the control signals. The execution reservation stations of ES0 and ES1 as the first operators and second operators, respectively),
wherein the control signals of the first controller are transmitted through a control transfer path, the control transfer path being separated from a data transfer path of the data network (Figs. 3 and 6, [0021, 0029]: Instructions from Disp0 are sent through the dispatch routing network 36. The execution interlock control communicates and transfers data between execution slice pairs. Therefore, it’s a data transfer path, separated from the dispatch routing network),
wherein the data transfer path is configured as a linear structure that sequentially connects a plurality of operator groups included in the fused PE (Fig. 6 and [0029]: The execution reservation stations of ES0 and ES1 are configured to be linearly connected to one another through the execution interlock control wire, therefore the data transfer path has a linear structure. The execution reservation stations of each execution slice as the plurality of operator groups), and
wherein the control transfer path is configured as a tree structure that provides the control signals to the plurality of operator groups in parallel (Figs. 3 and 6, [0029]: The dispatch routing network 36 has multiple branches (connections) to each of the execution slices and dispatch queues, therefore the dispatch routing network has a tree structure. When an instruction is dispatched from Disp0 and arrives at the fused PE, the instruction is processed through execution reservation stations 73 of one of the execution slices, before communicating the necessary data to the other slice (specifically to the reservation stations) through the execution interlock control such that the instructions arrive in parallel).
Eisen does not teach that the device is for an artificial neural network (ANN) processing or teach that the fused PE is used for parallel processing for a specific ANN model.
Dolly teaches a device for ANN processing and teaches a processing element used for a specific ANN model (Abstract: A system designed to perform sparse convolutional neural network processing, which is a specific ANN model, where processing elements are used to process non-zero elements)
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Eisen with the teachings of Dolly to have utilized a device to process an ANN model. One of ordinary skill would understand that ANN models require high performance and energy efficiency to keep up with computing needs (see [0003]). Therefore, utilizing the processor of Eisen would be reasonable to use in neural network processing.
Regarding claim 5, Eisen, in view of Dolly, teaches the device of claim 1, wherein an output by a last operator of the first operators is applied as an input of a leading operator of the second operators in the fused PE (Eisen, Figs. 3 and 6, [0029]: In the current combination, when an instruction is dispatched from Disp0 and arrives at the fused PE, the instruction is processed through execution reservation 73 of one of the execution slices. A first reservation station from the reservation stations 73 of one of the execution slices would be a last operator, in which its output (e.g., an instruction) would be transmitted through the execution interlock control wire and be applied as an input of a second reservation station (i.e., the leading operator) from the reservation stations of the other execution slice).
Regarding claim 6, Eisen, in view of Dolly, teaches the device of claim 1, wherein the first operators included in the first operation unit and the second operators included in the second operation unit are segmented into the plurality of operator groups (Eisen, Fig. 6 and [0029]: The reservation stations of ES0 and ES1 corresponds to the plurality of operation groups, but are separated (i.e., segmented) between ES0 and ES1. Therefore, the first operators and second operators are segmented into the plurality of operator groups).
Regarding claims 9, the claim recites a method similar to the device of claim 1. Therefore, the claim is rejected on the same premises.
Regarding claim 14, Eisen, in view of Dolly, teaches the device of claim 1, wherein each PE further comprises a data memory that stores data and a data patch unit that patches the data from the data memory (Eisen, Fig. 3 and [0021-0022]: See 112(b) rejection above. In the current combination, each slice comprises of a cache slice, which stores data, and a load-store slice that fetches/stores data to their respective cache slice. The cache slice as the data memory and the load-store slice as the data patch unit).
Regarding claim 16, Eisen, in view of Dolly, teaches the device of claim 1, wherein the plurality of operator groups include a first plurality of operator groups related to the first operators in the first operation unit (Eisen, Figs. 3 and 6, [0029]: In the current combination, the plurality of operator groups includes the reservation stations 73 of ES0 and ES1. The first operation unit includes the reservation stations 73 of ES0. Therefore, the plurality of operator groups includes a first plurality of operator groups (i.e., reservation stations 73 of ES0), which is related to the first operators in the first operation unit), and a second plurality of operator groups related to the second operators in the second operation unit (Eisen, Figs. 3 and 6, [0029]: In the current combination, the plurality of operator groups includes the reservation stations 73 of ES0 and ES1. The second operation unit includes the reservation stations 73 of ES1. Therefore, the plurality of operator groups includes a second plurality of operator groups (i.e., reservation stations 73 of ES1), which is related to the second operators in the second operation unit).
Regarding claim 17, Eisen, in view of Dolly, teaches the device of claim 1, wherein all of the first operators and the second operators are sequentially connected in the fused PE (Eisen, Fig. 6 and [0029]: In the current combination, the first and second operators (recall that it corresponds to execution reservation stations 73 in ES0 and ES1) are connected sequentially from left to right (i.e., reservation stations 73 of ES0 connected to reservation stations 73 of ES1)).
Claims 4 is rejected under 35 U.S.C. 103 as being unpatentable over Eisen et al. (US 20160202991 A1) in view of Khoche (US 20200028377 A1).
Regarding claim 4, Eisen, in view of Dolly, teaches the device of claim 1.
Eisen, in view of Dolly, does not teach that the second controller in the fused PE is disabled in the fused PE.
Note that Disp1 may be joined as a result of fusing the execution slices together (see [0026]), therefore the queue is utilized, but the logic for the queue may not be utilized for as long as the slices are fused.
Khoche teaches the use of a standby mode to disable a controller’s circuitry ([0035]: In sleep mode, the clock that drives the controller is disabled).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Eisen, in view of Dolly, with the teachings of Khoche to have placed the circuitry of Disp1 in standby mode when joining Disp1 and Disp0. One of ordinary skill would appreciate controlling the power consumption of unused circuitry as to reduce power consumption (see Khoche [0035]).
Claims 7 is rejected under 35 U.S.C. 103 as being unpatentable over Eisen et al. (US 20160202991 A1) in view of Dolly et al. (US 20180046916 A1), Cheng et al. (US 20200134428 A1), and Shah et al. (US 10248533 B1).
Regarding claim 7, Eisen, in view of Dolly, teaches the device of claim 1.
Eisen, in view of Dolly, does not explicitly teach that the first PE and the second PE perform processing on a second ANN model and a third ANN model different from the specific ANN model independently of each other.
Cheng teaches to process a recurrent neural network autoencoder and a multilayer perceptron autoencoder in parallel (see [0017]), which is different from the specific ANN model in Dolly.
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Eisen, in view of Dolly, with the teachings of Cheng to have processed the autoencoders in parallel. One of ordinary skill may realize that having multiple autoencoders run in parallel may be beneficial as they can have these models interact with one another and provide useful results or interactions (see [0017]). Additionally, it would make use of potential idle slices and to improve hardware utilization as a whole.
Eisen, in view of Dolly and Cheng, still does not teach that the first PE and the second PE are to perform processing of the autoencoders.
Shah teaches a processing element implementing an autoencoder (Col. 10, lines 4-5).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Eisen, in view of Dolly and Cheng, with the teachings of Shah to have processed the autoencoders using processing elements. Given that autoencoders requires processing power to compute the data required of the autoencoder models, one of ordinary skill would appreciate using processing elements such as the one mentioned in Eisen to aid in processing these models.
Claims 8 is rejected under 35 U.S.C. 103 as being unpatentable over Eisen et al. (US 20160202991 A1) in view of Dolly et al. (US 20180046916 A1) and Cioloboc (“Why use a pre-trained model rather than creating your own?”, see Non-Final Office Action mailed 10/21/2025).
Regarding claim 8, Eisen, in view of Dolly, teaches the device of claim 1, wherein the device is an accelerator configured to perform inference (Eisen, Fig. 3: Processor 20 consists of multiple execution slices, where output data of each execution slice is written back to all execution slices as new input data, which accelerates processing. Therefore, Processor 20 performs inference and is an accelerator) based on the DNN model (Dolly, Abstract: The initial input data is based on the convolutional neural network model processed by the execution elements, where the convolutional neural network is a type of deep neural network model (see pertinent art section “Understanding Deep Learning: DNN, RNN, LSTM, CNN and R-CNN”)).
Eisen, in view of Dolly, does not teach that the specific ANN model is a pre-trained deep neural network (DNN) model.
Cioloboc teaches using a pre-trained deep neural network model (see Section “What is Transfer Learning”)
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Eisen, in view of Dolly, with the teachings of Cioloboc to perform parallel processing using the pre-trained deep neural network model. One of ordinary skill would understand that creating and training a CNN model would be time consuming, whereas there are multiple CNN models that can be tweaked for a specific use, which requires less time than creating one (see Section “what is Transfer Learning” and “Why should I use a pre-trained model?”).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Eisen et al. (US 20160202991 A1) in view of Dolly et al. (US 20180046916 A1) and Gupta et al. (US 9971821 B1).
Regarding claim 12, Eisen teaches the method of claim 9.
Eisen does not teach a processor-readable recording medium storing instructions for performing the method according to claim 9.
Gupta teaches a processor-readable recording medium storing instructions for performing a method (Col. 1, lines 57-62).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Eisen, in view of Dolly, to have stored instructions in a non-transitory computer-readable medium to perform the aforementioned method. Storing the instructions in a computer-readable medium would allow one of ordinary skill to model, simulate, and test the design as it’s fundamental to debug and finalize designs prior to processing these instructions on a chip to avoid issues.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Eisen et al. (US 20160202991 A1) in view of Dolly et al. (US 20180046916 A1) and Sergio (EP 3640856 A1).
Regarding claim 13, Eisen, in view of Dolly, teaches the device of claim 1, wherein the first PE and the second PE are reconfigured into the fused PE, based on a memory size per PE (Eisen, [0026]: Execution slices are combined when an instruction’s width is twice the size of the instructions that can be handled by an execution slice (i.e., an increase in memory size to store the wider instructions)).
Eisen, in view of Dolly, does not teach the first PE and the second PE are reconfigured into the fused PE, based on a size of specific ANN model and a memory size per PE.
Sergio teaches to perform operations corresponding to a convolutional neural network model using a combination of instruction sets, which vary in size (Fig. 13 and Col. 16, line 46 to Col. 17, line 9: The processor 993 may execute operations corresponding to training a CNN, which includes using a combination of instruction sets, including VLIW (i.e., an instruction size of the convolutional neural network)).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Eisen, in view of Dolly, with the teachings of Sergio to have are reconfigured the first PE and the second PE into the fused PE based on executing VLIW instructions. One of ordinary skill would recognize that by executing VLIW instructions, a processor can execute multiple instructions at a time, exploiting instruction parallelism, which may be preferred by one of ordinary skill.
Claims 15 is rejected under 35 U.S.C. 103 as being unpatentable over Eisen et al. (US 20160202991 A1) in view of Dolly et al. (US 20180046916 A1) and Kothinti et al. (US 20190087241 A1).
Regarding claim 15, Eisen, in view of Dolly, teaches the device of claim 1. Eisen, in view of Dolly, does not teach that each operator group corresponds to
an operator array.
Kothinti teaches a reservation station corresponding to a reservation station array (Fig. 13 and [0023-0024]: A reservation station execution unit comprises of a reservation station array (i.e., the reservation station corresponds to a reservation station array).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Eisen, in view of Dolly, with the teachings of Kothinti to have each reservation station of the reservation stations correspond to a reservation station array, therefore having each operator group correspond to an operator array. Using reservation station arrays allows a block of instructions to be stored in each array unit and executes the instructions in the array unit at a time, unlike the functions of a generic reservation station, which does not bundle the instructions in blocks. By executing a block of instructions, more instructions can be processed at a time, which may be appreciated by one of ordinary skill.
Claims 1, 3, 9, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Eisen et al. (US 20160202991 A1) in view of Dolly et al. (US 20180046916 A1).
Note: the following rejections follow a different interpretation of the prior art and does not correspond to any of the rejections above.
Regarding claim 1, Eisen teaches a device for (Fig. 3: Processor core 20), the device comprising:
a first processing element (PE) comprising a first operation unit and a first controller configured to control the first operation unit (Fig. 3 and [0021-0022]: Disp0 (dispatch queue), ES0 (execution slice), LS0 (load-store slice), and CS0 (cache slice) as the first processing element. Disp0 and the hardware to control dispatching as the first controller, which controls instructions to be dispatched to ES0. ES0 as the operation unit); and
a second PE comprising a second operation unit and a second controller configured to control the second operation unit (Fig. 3 and [0021-0022]: Disp1, ES1, LS1, and CS1 as the second processing element. Disp1 and the hardware to control dispatching as the second controller, which controls instructions to be dispatched to ES1. ES1 as the second operation unit),
wherein the first PE and the second PE are reconfigured into one fused PE for parallel processing been reconfigured into one fused processing element, where the fusion is purposed to improve parallel processing by executing longer instruction words),
wherein first operators included in the first operation unit and second operators included in the second operation unit form a data network, and the data network is controlled based on control signals of the first controller in the fused PE (Fig. 6 and [0026, 0029]: Execution slices 42AA and 42BB (which can correlate to ES0 and ES1) are connected via an execution interlock control, which provides coordination between the slices to support a single instruction stream between the slices. Disp0 dispatches instructions to either ES0 or ES1 through the dispatch routing network 36, which is then processed by the slice and placed in the execution reservation station 73 of the respective execution slice, and from there, the execution slices coordinate the execution of the single instruction. Therefore, the instructions controls the data network. Execution reservation station and execution pipeline 72 as the operators since they operate based on the instructions received. The wires from the execution reservation stations connecting to the execution pipelines and the execution interlock control as the data network. The instructions as the control signals. The execution reservation station and execution pipeline 72 of ES0 and ES1 as the first operators and second operators, respectively),
wherein the control signals of the first controller are transmitted through a control transfer path, the control transfer path being separated from a data transfer path of the data network (Figs. 3 and 6, [0022-0030]: Instructions from Disp0 are sent through the dispatch routing network 36. The execution interlock control communicates and transfers data between execution slice pairs and writes back the data through the store data bus 39. Therefore, it’s a data transfer path, separated from the dispatch routing network),
wherein the data transfer path is configured as a linear structure that sequentially connects a plurality of operator groups included in the fused PE (Fig. 6 and [0022-0030]: The execution reservation stations 73 of ES0 and ES1 are configured to be connected through the execution interlock control wire and passes data to be processed through the execution pipeline in a sequential process from the execution reservation stations to the load-store slices and eventually the cache slices, therefore the data transfer path has a linear structure. The execution pipeline and the execution reservation station of each execution slice as the plurality of operator groups), and
wherein the control transfer path is configured as a tree structure that provides the control signals to the plurality of operator groups in parallel (Figs. 3 and 6, [0029]: The dispatch routing network 36 has multiple branches (connections) to each of the execution slices and dispatch queues, therefore the dispatch routing network has a tree structure. When an instruction is dispatched from Disp0 and arrives at the fused PE, the instruction is processed through execution reservation 73 of one of the execution slices, before communicating the necessary data to the other slice (specifically to the reservation stations) through the execution interlock control such that the instructions arrive in parallel to the execution pipeline 72 if the instruction is to store data through the store data bus 39).
Eisen does not teach that the device is for an artificial neural network (ANN) processing or teach that the fused PE is used for parallel processing for a specific ANN model.
Dolly teaches a device for ANN processing and teaches a processing element used for a specific ANN model (Abstract: A system designed to perform sparse convolutional neural network processing, which is a specific ANN model, where processing elements are used to process non-zero elements)
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Eisen with the teachings of Dolly to have utilized a device to process an ANN model. One of ordinary skill would understand that ANN models require high performance and energy efficiency to keep up with computing needs (see [0003]). Therefore, utilizing the processor of Eisen would be reasonable to use in neural network processing.
Regarding claim 3, Eisen, in view of Dolly, teaches the device of claim 1, wherein the control transfer path has a lower latency than the data transfer path (Eisen, Fig. 3 and [0021-0022]: The dispatch routing network 36 only needs to move data from dispatch units such as disp0 to one or more of the super slices. As for the data transfer path, located within the super slices, the data has to pass through the issue queue, execution pipelines, and through the load-store slices. Therefore, the data transfer path must have a higher latency than the dispatch routing network (e.g., the control transfer path)).
Regarding claims 9 and 11, the claims recite a method similar to the device of claims 1 and 3, respectively. Therefore, the claims are rejected on the same premises.
Response to Arguments/Amendments
Applicant’s amendments, filed December 31 2025, with respect to the specification objections raised by the Examiner has not been fully addressed. Therefore, the abstract and title objections have been withdrawn, but the other specification objections are maintained. See specification objections above.
Applicant’s amendments, filed December 31 2025, with respect to the drawing objections raised by the Examiner has not been fully addressed. Therefore, some of the objections of the drawings has been withdrawn. Furthermore, Examiner made new objections to the drawings. See drawing objections above.
Applicant's arguments, see Page 10 to Page 13, filed December 31 2025, with respect to the 112(f) interpretation of claim elements have been fully considered but they are not persuasive.
Applicant argues, on page 11, first paragraph, that the claim elements “first controller” and “second controller” are described in paragraphs [0061, 0064-0065] of the original disclosure.
Examiner respectfully disagrees with this argument. The terms “operation unit controller” and “controller” does not describe what the structure of the “controller” is exactly. The paragraphs mentioned merely describe what the accelerator comprises, not what the operation unit controller is structured. Therefore, the remarks regarding that the specification describes the “first controller” and “second controller” is considered not persuasive.
Applicant argues, on page 13, last paragraph, that the term “controller” is not a generic placeholder as it connotates a computing structure to one of ordinary skill in the art and does not constitute a means-plus-function limitation as a result.
Examiner respectfully disagrees with this argument. See MPEP 2181 regarding 112(f) interpretation. The term “controller” does not provide enough information for one of ordinary skill in the art to understand its structure and requires the specification for details of its structure. As for the term “controller”, the term itself does not define a structure, whether that be software, hardware, or some other component that defines a structure. Hence, the term “controller” of the claim elements “first controller” and “second controller” is interpreted as a “nonce” term, which satisfies the first prong of the 3-prong analysis for 112(f), which then results in the claim limitations be analyzed under the second and third prongs (see “Claim Interpretation” above). Furthermore, the examples in which the Applicant has provided to indicate that “controller” are commonly understood terms do not provide enough details as the Wikipedia page provides a list of what a “controller” could be referring to in the field of computing and the Britannica page makes no reference to a “controller”. Therefore, the remarks regarding that the claim elements do not invoke 112(f) is considered not persuasive.
Examiner will maintain the 112(f) interpretations for “first controller” and “second controller”. If Applicant wishes to not interpret these elements under 112(f), then they may amend the claims to insert a term with a known structure alongside the claim elements, provided there exists support for the amendments in the specification (See MPEP 2181(I)(A)).
Applicant’s amendments, filed December 31 2025, with respect to the 112(b) rejections raised by the Examiner has not been fully addressed. The 112(b) rejections with respect to antecedent basis problems has been addressed by Applicant, but the 112(b) rejections with respect to the written description has not been addressed. Therefore, the 112(b) rejections with respect to antecedent basis of claims 8 and 9 has been withdrawn, but the 112(b) rejections with respect to the written description is maintained. Furthermore, a new 112(b) rejection is raised. See 112(b) rejections above.
Applicant's arguments, see Page 14 to Page 22, filed December 31 2025, with respect to the rejection(s) of claim(s) 1-12 under 35 U.S.C. 103 have been fully considered and are mostly persuasive. Therefore, the rejection(s) has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of a different interpretation of the previously applied references and newly found prior art reference(s). See 103 rejections above.
Applicant argues, on Page 21, last paragraph and Page 22, first paragraph, that Eisen is silent on the path structure of the execution interlock control and does not disclose that the control transfer path is configured as a tree structure.
Given that the elements “linear structure” and “tree structure” are recited at a high level in the claims, Examiner takes the broadest reasonable interpretation of the elements. Examiner maps the “dispatch routing network” as the control path and a tree structure because it has a “tree-like” structure (i.e., branching connections similar to that of a tree) and the execution interlock control is mapped to have a linear structure because it’s “linearly connecting” the execution slices. Therefore, the remarks that Eisen is silent on the path structure of the execution interlock control and does not disclose that the control transfer path is configured as a tree structure is considered not persuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/E.A./Examiner, Art Unit 2183
/JYOTI MEHTA/Supervisory Patent Examiner, Art Unit 2183