DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 9/23/2024 and 12/2/2022 have been considered by the examiner.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 14 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because the claimed “processor-readable recording medium”, under the broadest reasonable interpretation, would include both statutory and non-statutory embodiments such as signals. The word "recording" is insufficient to convey only statutory embodiments to one of ordinary skill in the art absent an explicit and deliberate limiting definition or clear differentiation between storage media and transitory media in the disclosure. As such, the claim is drawn to a form of energy. Energy is not one of the four categories of invention and therefore the claim is not statutory.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 9 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding Claim 9, the limitations drawn to “memory at a lowest level… stores weights for at least two deep neural network models…” extend beyond what is shown in the specification. The specification describes storing weights for a single trained model in memory but does not teach storing weights for multiple trained models in the lowest tier.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 5-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ross [US 10,049,322].
Claim 1, Ross discloses a device for artificial neural network (ANN) processing [Abstract], the device comprising: memories configured to read/write (R/W) data related to an ANN model [memory hierarchy to store ANN weights, Col. 5, lines 10-25]; and at least one operation unit configured to perform operations regarding a plurality of layers included in the ANN model based on the data [compute units coupled to memories for layer ANN operations, Col. 7, lines 1-15], wherein the memories comprise at least one memory-subsystem corresponding to a combination of a plurality of memories of different types, and wherein each operation unit is configured to perform R/W of the data through a memory-subsystem associated with the each operation unit itself among the at least one memory-subsystem [operation units associated with specific memory subsystems, col. 7, lines 20-35].
Claim 2, Ross discloses the device of claim 1, wherein: R/W for weights of a first layer of the ANN model is performed through a first type memory of the associated memory-subsystem, R/W for weights of a second layer of the ANN model, on which an operation is performed after the first layer, is performed through a second type memory of the associated memory-subsystem, and R/W for weights of a third layer of the ANN model, on which an operation is performed after the second layer, is performed through a third type memory of the associated memory- subsystem [mapping ANN layers to different memory layers, see Col. 7, line 58 – Col. 8, line 35].
Claim 5, Ross discloses the device of claim 2, wherein the weights of the second layer are prefetched from the second type memory during the processing time of the first layer, and wherein the weights of the third layer are prefetched from the third type memory during the processing times of the first layer and the second layer [Col. 3, line 1-12].
Claim 6, Ross discloses the device of claim 1, wherein each memory-subsystem is a combination of an SRAM, a DRAM, and a NAND flash memory [See Col. 5, line 5-25 and Col. 12, lines 30-38].
Claim 7, Ross discloses the device of claim 6, wherein the SRAM is coupled to each operation unit in an on-chip form [on chip implementation of cell arrangement in the array, Col. 5, line 40-Col. 6, line 15].
Claim 8, Ross discloses the device of claim 1, wherein the plurality of memories of different types within each memory-subsystem have a hierarchical memory structure [Col. 5, lines 10-25, hierarchical arrangement of memory elements].
Claim 9, Ross discloses the device of claim 8, wherein a memory at a lowest level in the hierarchical memory structure stores weights for at least two deep neural network (DNN) models trained in advance through deep learning [storing weights in weight register, Col. 7, line 20- Col. 8, line 20].
Claim 10, Ross discloses the device of claim 1, wherein a type of a memory to be used for a corresponding layer is determined based on a result of compiling the ANN model [Col. 6, lines 49-62].
Claim 11, Ross discloses the device of claim 1, wherein the device is an accelerator configured to perform inference based on a previously trained deep neural network (DNN) model [Col. 3, lines 1-16 and Col. 3, lines 42-65].
Claim 12, Ross discloses the device of claim 1, wherein the device is a data center on an Internet protocol (IP) network, configured to respond to inference requests from multiple users via a network interface card (NIC) [see Col. 11, line 37-Col. 12, line 29].
Claim 13 is rejected using the same rationale as that of Claims 1 and 2.
Claim 14, Ross discloses a processor-readable recording medium storing instructions for performing the method according to claim 13 [Col. 11, line 15-36].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Ross [US 10,049,322] in view of Kim et al. [US 10,698,730].
Claim 3, Ross discloses the device of claim 2. Ross does not teach but Kim et al. discloses a read latency of the second type memory is longer than a read latency of the first type memory and shorter than a read latency of the third type memory [Col. 14, lines 61- Col. 15, line 15]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Ross to include latency aware allocations since doing so ensures that the latency of critical data is minimized while bulk storage is kept in high density storage thus enhancing performance.
Claim 4, Ross in view of Kim et al. discloses the device of claim 2, wherein a processing time for the first layer is equal to or longer than the read latency of the second type memory [different latency of dynamic vs. static memories], and wherein a sum of the processing time for the first layer and a processing time for the second layer is equal to or greater than the read latency of the third type memory [see Col. 14, line 41-67].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chou et al. [US 2022/0351032]; Memory for Artificial Neural Network Accelerator. Discloses Artificial Neural Network and its related computer systems.
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/MIDYS ROJAS/ Primary Examiner, Art Unit 2133