DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
RESPONSE TO ARGUMENTS
Applicant's arguments filed 7/30/2026 have been fully considered but they are not persuasive.
In response to applicant’s arguments with regard to the independent claim 1 rejected under 35 U.S.C. 103(a) that the combination of the references does not teach/suggest the claimed feature “… the plurality of operation instructions comprise at least one multi-stage pipeline operation …” because the combination of the references does not teach/suggest a single computing instruction, when parsed, yields a plurality of operation instructions that can form one or more complete pipeline operations, with the processing circuit array being correspondingly configured into one or more groups of sub-arrays, each sub-array serving as different stages of a respective pipeline; applicant's arguments have fully been considered, but are not found to be persuasive.
Please note that the features upon which applicant relies (i.e., a single computing instruction, when parsed, yields a plurality of operation instructions that can form one or more complete pipeline operations, with the processing circuit array being correspondingly configured into one or more groups of sub-arrays, each sub-array serving as different stages of a respective pipeline) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
As applicant appears to be applying the above arguments for independent claim 1 towards independent claim 22, the examiner will also apply the above response for independent claim 1 towards independent claim 22.
In response to applicant’s arguments with regard to the independent claim 1 rejected under 35 U.S.C. 103(a) that the combination of the references does not teach/suggest the claimed feature “… dynamically configuring a processing circuit array into a plurality of sub-arrays … a plurality of operation instructions forming one or more multi-stage pipeline operations with each sub-array serving as different stages …” because Tanner is fixed structure; applicant's arguments have fully been considered, but are not found to be persuasive.
The examiner respectfully disagrees, the examiner is relying on the other cited references in combination with Tanner, not on Tanner along, for the teaching/suggesting of the above claimed features.
Furthermore, please note that one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
As applicant appears to be applying the above arguments for independent claim 1 towards independent claim 22, the examiner will also apply the above response for independent claim 1 towards independent claim 22.
In response to applicant’s arguments with regard to the independent claim 1 rejected under 35 U.S.C. 103(a) that the combination of the references does not teach/suggest the claimed feature “… a plurality of operation instructions forming one or more multi-stage pipeline operations … different sub-arrays serving as different stages of such a pipeline operation …” because Kesiraju does not disclose the above claimed features; applicant's arguments have fully been considered, but are not found to be persuasive.
The examiner respectfully disagrees, the examiner is relying on the other cited references in combination with Kesiraju, not on Kesiraju along, for the teaching/suggesting of the above claimed features.
Furthermore, please note that one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
As applicant appears to be applying the above arguments for independent claim 1 towards independent claim 22, the examiner will also apply the above response for independent claim 1 towards independent claim 22.
In response to applicant’s arguments with regard to the independent claim 1 rejected under 35 U.S.C. 103(a) that the combination of the references does not teach/suggest the claimed feature “… a single operation being split into multiple pipeline stages …” and “… one instruction triggering multiple complete pipelines …” because KIM does not disclose the above claimed features as KIM’s disclosure do not support multiple pipelines executing in parallel; applicant's arguments have fully been considered, but are not found to be persuasive.
Please note that the features upon which applicant relies (i.e., a single operation being split into multiple pipeline stages, one instruction triggering multiple complete pipelines, multiple pipelines executing in parallel) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
As applicant appears to be applying the above arguments for independent claim 1 towards independent claim 22, the examiner will also apply the above response for independent claim 1 towards independent claim 22.
In response to applicant’s arguments with regard to the independent claim 1 rejected under 35 U.S.C. 103(a) that the combination of the references does not teach/suggest the claimed feature “… at least one …” because the combination of the references do not disclose the scenario of multiple pipeline executing in parallel as “multiple pipelines” are completely absent; applicant's arguments have fully been considered, but are not found to be persuasive.
Please note that the features upon which applicant relies (i.e., multiple pipeline executing in parallel, multiple pipelines) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
As applicant appears to be applying the above arguments for independent claim 1 towards independent claim 22, the examiner will also apply the above response for independent claim 1 towards independent claim 22.
In response to applicant’s arguments with regard to the independent claim 1 rejected under 35 U.S.C. 103(a) that the combination of the references does not teach/suggest the claimed features because Brothers’ hardware structure does not have sub-array inter-stage connections dynamically established via configuration information; applicant's arguments have fully been considered, but are not found to be persuasive.
The examiner respectfully disagrees, the examiner is relying on the other cited references in combination with Brothers, not on Brothers along, for the teaching/suggesting of the above claimed features.
Furthermore, please note that one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
As applicant appears to be applying the above arguments for independent claim 1 towards independent claim 22, the examiner will also apply the above response for independent claim 1 towards independent claim 22.
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, the motivation to combine Kesiraju’s array architectures, KIM’s neural network layers and Brothers’ neural network instructions into Tanner’s apparatus for the benefit of implementing an optimized architecture (Kesiraju, [0003]-[0004]), increasing processing speed (KIM, [0066]) and optimizing power and performance (Brothers, [0025]).
In response to applicant's argument that Tanner, Kesiraju and Brothers is nonanalogous art, it has been held that a prior art reference must either be in the field of the inventor’s endeavor or, if not, then be reasonably pertinent to the particular problem with which the inventor was concerned, in order to be relied upon as a basis for rejection of the claimed invention. See In re Oetiker, 977 F.2d 1443, 24 USPQ2d 1443 (Fed. Cir. 1992). In this case, Tanner, Kesiraju and Brothers are in the field of the inventor’s endeavor as Tanner, Kesiraju and Brothers array circuitry is used in machine learning/neural network (e.g. artificial intelligence).
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
In response to applicant’s arguments with regard to the independent claim 1 rejected under 35 U.S.C. 103(a) that the combination of the references does not teach/suggest the claimed feature “… at least one multi-stage pipeline operation …” because KIM do not disclose multiple pipelines and thus cannot cover the “more” scenario encompassed by “at least one”; applicant's arguments have fully been considered, but are not found to be persuasive.
Please note that the features upon which applicant relies (i.e., multiple pipelines) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Furthermore, “at least one” can be interpreted as “one or more” and applicant remarks seems to indicate that KIM does teach/suggest “one”; therefore, KIM does teach/suggest the above claimed features.
As applicant appears to be applying the above arguments for independent claim 1 towards independent claim 22, the examiner will also apply the above response for independent claim 1 towards independent claim 22.
I. REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-10, 14-19, 22, 40 and 42 are rejected under 35 U.S.C. 103 as being unpatentable over Tanner (US Pub.: 2021/0048991) in view of Kesiraju et al. (US Pub.: 2020/0272597), KIM et al. (US Pub.: 2021/0117781) and Brothers et al. (US Pub.: 2017/0011288).
As per claim 1, Tanner teaches/suggests a computing apparatus, comprising: a processing circuit array, which is formed by connecting a plurality of processing circuits, wherein the processing circuit array is configured to operating accordingly (e.g. associated with array of processing elements operating accordingly: [0047]; [0479]-[0480]), wherein the plurality of operation instructions are obtained by parsing a computing instruction received by the computing apparatus ([0409]) ([0047]; [0409]; and [0479]-[0496]).
Tanner does not teach the computing apparatus comprising:
in a one-dimensional or multi-dimensional array structure, a plurality of processing circuit sub-arrays in response to receiving a plurality of operation instructions, wherein the plurality of operation instructions comprise at least one multi-stage pipeline operation, and each processing circuit sub-array is configured to serve as a different stage of the multi-stage pipeline operation; and
the computing apparatus further comprises a control circuit configured to configure the processing circuit array according to configuration information extracted from the plurality of operation instructions or from a configuration instruction to obtain the plurality of processing circuit sub-arrays.
Kesiraju teaches/suggests a computing apparatus, comprising: in a one-dimensional or multi-dimensional array structure (Fig. 3-4) (Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; and [0114])
KIM teaches/suggests a computing apparatus, comprising: a plurality of processing circuit sub-arrays, wherein the plurality of operation instructions comprise at least one multi-stage pipeline operation, and each processing circuit sub-array is configured to serve as a different stage of the multi-stage pipeline operation; and to obtain the plurality of processing circuit sub-arrays (e.g. associated with neurons/PEs for each of the multiple layers of neural network) (Fig. 1; and [0053]-[0056]).
Brothers teaches/suggests a computing apparatus, comprising: operating in response to receiving a plurality of operation instructions; and the computing apparatus further comprises a control circuit configured to configure the processing circuit array according to configuration information extracted from the plurality of operation instructions or from a configuration instruction (e.g. associated with parsing instructions for controlling processing units within NN processor) ([0022]-[0024]; and [0049]-[0055]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Kesiraju’s array architectures, KIM’s neural network layers and Brothers’ neural network instructions into Tanner’s apparatus for the benefit of implementing an optimized architecture (Kesiraju, [0003]-[0004]), increasing processing speed (KIM, [0066]) and optimizing power and performance (Brothers, [0025]) to obtain the invention as specified in claim 1.
As per claim 5, Tanner, Kesiraju, KIM, and Brothers teach/suggest all the claimed features of claim 1 above, where Tanner, Kesiraju, KIM, and Brothers further teach/suggest the computing apparatus comprising: wherein the multi-stage pipeline operation comprises at least two operations instructions (Tanner, [0047]; [0409]; [0479]-[0496]; Kesiraju, Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; [0114]; KIM, Fig. 1; [0053]-[0056]; and Brothers, [0022]-[0024]; [0049]-[0055]).
As per claim 6, Tanner, Kesiraju, KIM, and Brothers teach/suggest all the claimed features of claim 1 above, where Tanner, Kesiraju, KIM, and Brothers further teach/suggest the computing apparatus comprising: wherein the operation instruction comprises a predicate, and each processing circuit judges whether to perform an associated operation instruction according to the predicate (Tanner, [0047]; [0069]; [0409]; [0411]; [0413]; [0479]-[0496]; Kesiraju, Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; [0114]; KIM, Fig. 1; [0053]-[0056]; and Brothers, [0022]-[0024]; [0049]-[0055]).
As per claim 7, Tanner, Kesiraju, KIM, and Brothers teach/suggest all the claimed features of claim 1 above, where Tanner, Kesiraju, KIM, and Brothers further teach/suggest the computing apparatus comprising: wherein the processing circuit array is a one-dimensional array, and one or a plurality of processing circuits in the processing circuit array are configured to serve as one processing circuit sub-array (Tanner, [0047]; [0409]; [0452]-[0453]; [0479]-[0497]; [0530]; Kesiraju, Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; [0114]; KIM, Fig. 1; [0053]-[0056]; and Brothers, [0022]-[0024]; [0049]-[0055]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 8, Tanner, Kesiraju, KIM, and Brothers teach/suggest all the claimed features of claim 1 above, where Tanner, Kesiraju, KIM, and Brothers further teach/suggest the computing apparatus comprising: wherein the processing circuit array is a two-dimensional array, wherein one or more rows of processing circuits in the processing circuit array are configured to serve as one processing circuit sub-array; or one or more columns of processing circuits in the processing circuit array are configured to serve as one processing circuit sub-array; or one or more rows of processing circuits along a diagonal direction of the processing circuit array are configured to serve as one processing circuit sub-array (Tanner, [0047]; [0409]; [0452]-[0453]; [0479]-[0497]; [0530]; Kesiraju, Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; [0114]; KIM, Fig. 1; [0053]-[0056]; and Brothers, [0022]-[0024]; [0049]-[0055]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 9, Tanner, Kesiraju, KIM, and Brothers teach/suggest all the claimed features of claim 8 above, where Tanner, Kesiraju, KIM, and Brothers further teach/suggest the computing apparatus comprising: wherein the plurality of processing circuits located in the two-dimensional array are configured to be connected in a predetermined two-dimensional interval mode with one or more of the remaining processing circuits in the same row, column, or diagonal in at least one of row, column, or diagonal directions of the plurality of processing circuits (Tanner, [0047]; [0409]; [0452]-[0453]; [0479]-[0497]; [0530]; Kesiraju, Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; [0114]; KIM, Fig. 1; [0053]-[0056]; and Brothers, [0022]-[0024]; [0049]-[0055]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 10, Tanner, Kesiraju, KIM, and Brothers teach/suggest all the claimed features of claim 9 above, where Tanner, Kesiraju, KIM, and Brothers further teach/suggest the computing apparatus comprising: wherein the predetermined two-dimensional interval mode is associated with the number of processing circuits spaced in the connection (Tanner, [0047]; [0409]; [0452]-[0453]; [0479]-[0497]; [0530]; Kesiraju, Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; [0114]; KIM, Fig. 1; [0053]-[0056]; and Brothers, [0022]-[0024]; [0049]-[0055]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 14, Tanner, Kesiraju, KIM, and Brothers teach/suggest all the claimed features of claim 7 above, where Tanner, Kesiraju, KIM, and Brothers further teach/suggest the computing apparatus comprising: wherein the plurality of processing circuits in the processing circuit sub-array are formed into one or a plurality of closed loops (Tanner, [0047]; [0409]; [0452]-[0453]; [0479]-[0497]; [0530]; Kesiraju, Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; [0114]; KIM, Fig. 1; [0053]-[0056]; and Brothers, [0022]-[0024]; [0049]-[0055]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 15, Tanner, Kesiraju, KIM, and Brothers teach/suggest all the claimed features of claim 1 above, where Tanner, Kesiraju, KIM, and Brothers further teach/suggest the computing apparatus comprising: wherein each processing circuit sub-array is suitable for performing at least one of following operations: an arithmetic operation, a logical operation, a comparison operation, and a lookup table operation (Tanner, [0047]; [0409]; [0452]-[0453]; [0479]-[0497]; [0530]; Kesiraju, Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; [0114]; KIM, Fig. 1; [0053]-[0056]; and Brothers, [0022]-[0024]; [0049]-[0055]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 16, Tanner, Kesiraju, KIM, and Brothers teach/suggest all the claimed features of claim 1 above, where Tanner, Kesiraju, KIM, and Brothers further teach/suggest the computing apparatus further comprising: a data operating circuit, which comprises a pre-operating circuit and/or a post-operating circuit, wherein the pre-operating circuit is configured to perform pre-processing on input data of at least one operation instruction, and the post-operating circuit is configured to perform post-processing on output data of at least one operation instruction (Tanner, [0047]; [0409]; [0452]-[0453]; [0479]-[0497]; [0530]; Kesiraju, Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; [0114]; KIM, Fig. 1; [0053]-[0056]; and Brothers, [0022]-[0024]; [0049]-[0055]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 17, Tanner, Kesiraju, KIM, and Brothers teach/suggest all the claimed features of claim 16 above, where Tanner, Kesiraju, KIM, and Brothers further teach/suggest the computing apparatus comprising: wherein the pre-processing comprises data placement and/or lookup table operations, and the post-processing comprises data type conversion and/or compression operations (Tanner, [0047]; [0409]; [0452]-[0453]; [0479]-[0497]; [0530]; Kesiraju, Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; [0114]; KIM, Fig. 1; [0053]-[0056]; and Brothers, [0022]-[0024]; [0049]-[0055]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 18, Tanner, Kesiraju, KIM, and Brothers teach/suggest all the claimed features of claim 17 above, where Tanner, Kesiraju, KIM, and Brothers further teach/suggest the computing apparatus comprising: wherein the data placement comprises sending input data and/or output data of the operation instruction to corresponding processing circuits for operations after splitting or merging the input data and/or the output data of the operation instruction accordingly according to a data type of the input data and/or the output data of the operation instruction (Tanner, [0047]; [0409]; [0452]-[0453]; [0479]-[0497]; [0530]; Kesiraju, Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; [0114]; KIM, Fig. 1; [0053]-[0056]; and Brothers, [0022]-[0024]; [0049]-[0055]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 19, claim 19 is rejected in accordance to the same rational and reasoning as the above rejection of claim 1, where Tanner, Kesiraju, KIM, and Brothers further teach/suggest an integrated circuit chip, comprising the computing apparatus of claim 1 (Tanner, [0047]; [0408]-[0409]; [0452]-[0453]; [0479]-[0497]; [0530]; Kesiraju, Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; [0114]; KIM, Fig. 1; [0053]-[0056]; and Brothers, [0022]-[0024]; [0049]-[0055]).
As per claim 22, claim 22 is rejected in accordance to the same rational and reasoning as the above rejection of claim 1, as claim 22 is the method carried out by the computing apparatus of claim 1, where Tanner, Kesiraju, KIM, and Brothers further teach/suggest the method comprising using the plurality of processing circuit sub-arrays to perform the multi-stage pipeline operation in response to receiving the plurality of operation instructions (Tanner, [0047]; [0408]-[0409]; [0452]-[0453]; [0479]-[0497]; [0530]; Kesiraju, Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; [0114]; KIM, Fig. 1; [0053]-[0056]; and Brothers, [0022]-[0024]; [0049]-[0055]).
As per claim 40, Tanner, Kesiraju, KIM, and Brothers teach/suggest all the claimed features of claim 1 above, where Tanner, Kesiraju, KIM, and Brothers further teach/suggest the computing apparatus comprising: wherein an operation code of the computing instruction represents a plurality of operations performed by the processing circuit array, and the control circuit is further configured to acquire and parse the computing instruction to obtain a plurality of operation instructions corresponding to the plurality of operations represented by the operation code (Tanner, [0047]; [0409]; [0452]-[0453]; [0479]-[0497]; [0530]; Kesiraju, Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; [0114]; KIM, Fig. 1; [0053]-[0056]; and Brothers, [0022]-[0024]; [0049]-[0055]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 42, Tanner, Kesiraju, KIM, and Brothers teach/suggest all the claimed features of claim 1 above, where Tanner, Kesiraju, KIM, and Brothers further teach/suggest the computing apparatus comprising: wherein the control circuit comprises a register used for storing configuration information, and the control circuit extracts corresponding configuration information from the register according to the plurality of operation instructions and configures the processing circuit array according to the configuration information to obtain the plurality of processing circuit sub-arrays (Tanner, [0047]; [0409]; [0452]-[0453]; [0479]-[0497]; [0530]; Kesiraju, Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; [0114]; KIM, Fig. 1; [0053]-[0056]; and Brothers, [0022]-[0024]; [0049]-[0055]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features.
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Tanner (US Pub.: 2021/0048991) in view of Kesiraju et al. (US Pub.: 2020/0272597), KIM et al. (US Pub.: 2021/0117781) and Brothers et al. (US Pub.: 2017/0011288) as applied to claim 1 above, and further in view of Vorbach et al. (US Pub.: 2012/0216012).
As per claim 11, Tanner, Kesiraju, KIM, and Brothers teach/suggest all the claimed features of claim 1 above, where Tanner, Kesiraju, KIM, and Brothers further teach/suggest the computing apparatus comprising sub-arrays in the processing circuit array are configured to serve as one processing circuit sub-array (Tanner, [0047]; [0409]; [0452]-[0453]; [0479]-[0497]; [0530]; Kesiraju, Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; [0114]; KIM, Fig. 1; [0053]-[0056]; and Brothers, [0022]-[0024]; [0049]-[0055]), but do not expressly teach/suggest the computing apparatus comprising wherein the processing circuit array is a three-dimensional array, and one or a plurality of three-dimensional architecture are operating accordingly.
Vorbach teach/suggest an apparatus comprising wherein the processing circuit array is a three-dimensional array, and one or a plurality of three-dimensional architecture are operating accordingly ([0012]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Vorbach’s three dimensional architecture into Tanner, Kesiraju, KIM, and Brothers’ apparatus for the benefit of improving data processing efficiency, power consumption and software scalability (Vorbach, [0005]; and [0016]) to obtain the invention as specified in claim 11.
As per claim 12, Tanner, Kesiraju, KIM, Brothers, and Vorbach teach/suggest all the claimed features of claim 11 above, where Tanner, Kesiraju, KIM, Brothers, and Vorbach further teach/suggest the computing apparatus comprising wherein the three-dimensional array is a three-dimensional array composed of a plurality of layers, wherein each layer comprises a two-dimensional array of a plurality of processing circuits arranged along row, column, and diagonal directions, wherein a processing circuit located in the three-dimensional array is configured to be connected in a predetermined three-dimensional interval mode with one or more of the remaining processing circuits in the same row, column, diagonal, or a different layer in at least one of row, column, diagonal, and layer directions of the processing circuit (Tanner, [0047]; [0409]; [0452]-[0453]; [0479]-[0497]; [0530]; Kesiraju, Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; [0114]; KIM, Fig. 1; [0053]-[0056]; Brothers, [0022]-[0024]; [0049]-[0055]; and Vorbach, [0012]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 13, Tanner, Kesiraju, KIM, Brothers, and Vorbach teach/suggest all the claimed features of claim 12 above, where Tanner, Kesiraju, KIM, Brothers, and Vorbach further teach/suggest the computing apparatus comprising wherein the predetermined three-dimensional interval mode is associated with the number of intervals and the number of layers of intervals between to-be-connected processing circuits (Tanner, [0047]; [0409]; [0452]-[0453]; [0479]-[0497]; [0530]; Kesiraju, Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; [0114]; KIM, Fig. 1; [0053]-[0056]; Brothers, [0022]-[0024]; [0049]-[0055]; and Vorbach, [0012]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features.
II. PERTINENT RELATED PRIOR ART
NIKITOPOULOS et al. (US Pub.: 2018/0176049): discloses processing elements being allocated in a dynamic manner, whereby a processing element originally allocated to one sub-tree can be re-allocated to another sub-tree.
III. CLOSING COMMENTS
CONCLUSION
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN KUAN LEE whose telephone number is (571)272-0671. The examiner can normally be reached Monday-Friday.
IMPORTANT NOTE
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHUN KUAN LEE/Primary Examiner
Art Unit 2181 September 23, 2026
