DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 12/30/2022, 09/06/2024, and 11/14/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
Claims 3-5, 7, and 9 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites “the number of data required to be written and read in each dimension” in line 2. There is insufficient antecedent basis for this limitation as the claim does not introduce a number of data that is required to be written and read in each dimension. For purposes of examination this will be interpreted as any number of data that is written and read in each dimension.
Claim 4 recites “wherein the address interval is determined according to the number of data in the current dimension and space occupied by each piece of data” and follows from claims 2-3 which describes that the data conversion instruction comprises the inter-dimension offset information which comprises the address interval. If the address interval is provided by the instruction (as claims 1-3 describe the instruction comprises the address interval), then it is unclear how the address interval is also determined according to the number of data in the current dimension and space occupied by each piece of data (as described in claim 4). In other words, the address interval is either provided by the instruction or it is determined from the number of data and space of each data, it does not make sense to determine the address interval from the number of data and space of each data if the instruction provides the address interval. Examiner notes that [28] of the specification describes that the inter-dimension offset information includes the address interval in one exemplary scenario and that the address interval is determined according to the number of data in the current dimension and space occupied by each piece of data in another exemplary scenario, which indicates that these are different embodiments. For purposes of examination, this limitation will be interpreted as the address interval corresponding to the number of data in the current dimension and space occupied by each piece of data.
Claim 4 recites “each piece of data” in line 3. There is insufficient antecedent basis for this limitation as the claim does not introduce pieces of data and it is unclear whether this may refer to pieces of the to-be-converted data or pieces of the number of data to be written and read in each dimension. For purposes of examination this will be interpreted as referring to pieces of data in each dimension.
Claim 5 recites “the dimension” in line 5. It is unclear which dimension of the multiple dimensions introduced in claim 2 this refers to. For purposes of examination this will be interpreted as any dimension.
Claim 5 recites “the write and read operations” in lines 10-11. It is unclear whether this refers to the write and read operations introduced in claim 1 or the write and read operation introduced in line 8. For purposes of examination this limitation will be interpreted as referring to the write and read operations introduced in line 8.
Claim 7 recites “the multi-dimensional data” in lines 3-4. There is insufficient antecedent basis for this limitation as the claim does not introduce multi-dimensional data. For purposes of examination this will be interpreted as any multi-dimensional data.
Claim 9 recites “an intermediate matrix” in lines 5, 13, 21, 29, and 37. It is unclear whether these refer to the same intermediate matrix or if they are different. It is further unclear which intermediate matrix references to “the intermediate matrix” refer to. For purposes of examination, each introduced intermediate matrix will be interpreted as a different intermediate matrix and each reference to the intermediate matrix will be interpreted as referring to a respective intermediate matrix.
Claim 9 recites “the matrix” in lines 8, 16, 24, 32, and 40. It is unclear which of the previously introduced matrices this refers to. For purposes of examination, they will be interpreted as referring to respective destination matrices.
Claims dependent on a rejected base claim are further rejected based on their dependence.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7-8, 14-16, 20-22, 24, 26, and 51 are rejected under 35 U.S.C. 103 as being unpatentable over Valentine US 2019/0347100 in view of Tran US 2019/0187985.
Regarding claim 1, Valentine teaches:
1. A data processing apparatus comprising:
a data caching circuit configured to perform data caching (Fig. 14 cache 1413); and
a data conversion circuit configured to perform read operations on to-be- converted data in the data caching circuit according to a data conversion instruction, so as to implement a data conversion on the to-be-converted data ([0120] describes that execution circuits 1427 may perform the matrix operations disclosed, Fig. 14 shows the execution circuitry as receiving data from cache 1413, and [0184] discloses that the source matrix may be stored in memory or other storage accessible to the execution circuitry, this indicates that the execution circuitry 2410 (i.e., a data conversion circuit) that executes the tile transpose instruction (i.e., a data conversion instruction), see [0185], is configured to perform read operations on the source data (i.e., to-be-converted data) in the cache according to the tile transpose instruction to implement a transpose/data converse on the to-be-converted source data).
Valentine does not teach the data conversion circuit being configured to perform write operations on to-be-converted data in the data caching circuit.
However, Tran teaches writing data to L1 cache from another level of cache or main memory upon a cache miss, see [0064].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Valentine to write data to the data cache (from another level of cache or main memory) upon a cache miss as taught by Tran such that the combination would perform write operations on to-be-converted data into/in the data caching circuit when the tile transpose instruction accesses source data not in the cache. One of ordinary skill in the art would have been motivated to make this modification to enable accessing the data when it is not in the cache.
Claim 26 is directed to a method for the data processing apparatus of claim 1 and is rejected for the same reasons as claim 1.
Regarding claim 2, Valentine in view of Tran teaches:
2. The data processing apparatus of claim 1, wherein the to-be- converted data is multi-dimensional data (Valentine [0182]: the source data is a matrix, which is multi-dimensional data), and the data conversion instruction comprises source and destination matrix operands (Valentine [0183]).
Valentine does not teach:
the data conversion instruction comprises data volume information and inter-dimension offset information about performing the write and read operations in each dimension in the multi-dimensional data.
However, Tran further teaches generating addresses to extract a rectangle/matrix using parameters ELEM_BYTES, ICNT0, DIM1, ICNT1, and a start address, see [0158] and [0181], where the iteration counts indicate the number of iterations of the respective loop level (i.e., data volume information) and DIM1 is the number of bytes between starting points for consecutive iterations of loop level 1 (i.e., inter-dimension offset information), see [0140].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the transpose instruction of Valentine to specify the parameters for extracting a source matrix as taught by Tran such that the transpose instruction of the combination would include data volume information and inter-dimension offset information for performing write and read operations in each dimension of the multi-dimensional data. One of ordinary skill in the art would have been motivated to make this modification to efficiently specify paths through memory using a small number of parameters (Tran [0139])
Regarding claim 3, Valentine in view of Tran teaches:
3. The data processing apparatus of claim 2, wherein the data volume information comprises the number of data required to be written and read in each dimension (Tran [0245]: the iteration count corresponds to the number of elements/data required to be read from the source and written to the destination in each dimension), and the inter-dimension offset information comprises an address interval required to be spanned from a current dimension to a next dimension (Tran [0138]: each loop level moves the pointer to a new location based on the size of the dimension of the loop level, which indicates that the DIM parameter is an address interval that goes from a current dimension corresponding to a current loop level to a next dimension corresponding to a next loop level).
Regarding claim 4, Valentine in view of Tran teaches:
4. The data processing apparatus of claim 3, wherein the address interval is determined according to the number of data in the current dimension and space occupied by each piece of data (the address interval is the number of bytes between starting points for each loop iteration, see [0140], which corresponds to the number of data in the current dimension and the space occupied by each data).
Regarding claim 7, Valentine in view of Tran teaches:
7. The data processing apparatus of claim 1, wherein the data conversion comprises performing one or more operations of a bypass operation, a multi-angle rotation operation, a mirroring operation, or a sequential conversion operation on the multi-dimensional data (Valentine [1098] describes that the execution circuitry loops over each row and loops over each column for each row to perform the tile transpose instruction, which is a sequential conversion operation on the source matrix/multi-dimensional data).
Regarding claim 8, Valentine in view of Tran teaches:
8. The data processing apparatus of claim 1, wherein the to-be- converted data is a to-be-converted matrix (Valentine Fig. 24, the source data to-be-converted is a matrix), and the data caching circuit comprises a caching storage array (Valentine Fig. 14 cache 1413 is a caching storage array in the sense that it has an array of storage locations)
Regarding claim 14, Valentine in view of Tran teaches:
14. The data processing apparatus of claim 1, wherein the data caching circuit is configured to cache multi-dimensional data (Valentine Fig. 14 cache 1413 caches the source matrix/multidimensional data); and
the data conversion circuit is configured to perform write and read operations on the multi- dimensional data in the data caching circuit according to the data conversion instruction, so as to implement a data conversion on the multi-dimensional data (Valentine [0182] discloses executing a tile transpose instruction (i.e., using a data conversion/execution circuit) to cause rows of a source matrix to be written as columns of a destination matrix, which involves write operations (to the destination) and read operations (from the source) on to be converted/transposed source data (stored in cache in the combination with Tran) according to the tile transpose instruction to implement a data conversion/transpose of the source data),
Valentine in view of Tran, as currently mapped, does not teach:
wherein the data conversion instruction comprises a descriptor used for indicating a shape of the multi-dimensional data, and
the descriptor is used to determine a storage address corresponding to the multi-dimensional data, wherein the data conversion circuit is configured to perform the write and read operations on the multi-dimensional data according to the storage address.
However, Tran further teaches generating addresses to extract a rectangle/matrix using parameters ELEM_BYTES, ICNT0, DIM1, ICNT1, and a start address, see [0158] and [0181], where the iteration counts indicate the number of iterations of the respective loop level (i.e., data volume information) and DIM1 is the number of bytes between starting points for consecutive iterations of loop level 1 (i.e., inter-dimension offset information), see [0140].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the transpose instruction of Valentine to specify the parameters for extracting a source matrix as taught by Tran such that the parameters are collectively a descriptor and the start address is used to determine a storage address when performing the write and read operations. One of ordinary skill in the art would have been motivated to make this modification to efficiently specify paths through memory using a small number of parameters (Tran [0139]).
Regarding claim 15, Valentine in view of Tran teaches:
15. The data processing apparatus of claim 14, wherein the data conversion instruction comprises identification of the descriptor (in the combination, the fields of the tile transpose instruction that identifies the parameters ELEM_BYTES, ICNT0, DIM1, ICNT1, and start address register is an identification of the descriptor) and/or content of the descriptor (this “or” limitation is not required under BRI), and the content of the descriptor comprises at least one shape parameter representing the shape of the multi-dimensional data and at least one address parameter representing an address of the multi- dimensional data.
Regarding claim 16, Valentine in view of Tran teaches:
16. The data processing apparatus of claim 15, wherein the address parameter (this limitation is not required under BRI since the address parameter follows from the optional limitation describing content of the descriptor) of the multi-dimensional data comprises a base address of a data datum point of the descriptor in data storage space of the multi-dimensional data,
wherein the shape parameter (this limitation is not required under BRI since the shape parameter follows from the optional limitation describing content of the descriptor) of the multi-dimensional data comprises at least one of followings:
a size of the data storage space in at least one of N dimensional directions, a size of a storage area of the multi-dimensional data in at least one of N dimensional directions, an offset of the storage area in at least one of N dimensional directions, positions of at least two vertices at diagonal positions of N dimensional directions relative to the data datum point, and a mapping relationship between a data description position of the multi-dimensional data indicated by the descriptor and a data address of the multi-dimensional data indicated by the descriptor, wherein N is an integer greater than or equal to 0,
wherein the data conversion instruction comprises data volume information and/or inter- dimension offset information about performing write and read operations in each dimension in the multi-dimensional data (in the combination, the iteration counts indicate the number of iterations of the respective loop level (i.e., data volume information) and DIM1 is the number of bytes between starting points for consecutive iterations of loop level 1 (i.e., inter-dimension offset information)), and the data volume information and/or the inter-dimension offset information are determined according to the address parameter and/or the shape parameter in the descriptor (this limitation is not required under BRI since the address parameter and shape parameter follow from the optional limitation describing content of the descriptor).
Regarding claim 20, Valentine in view of Tran teaches:
20. The data processing apparatus of claim 14, wherein the data conversion circuit is configured to perform the write and read operations on the multi-dimensional data, so as to perform one of following conversion operations on the multi-dimensional data:
a data mirroring operation, a multi-angle data rotation operation, or a data transposition operation (Valentine [0182]: the execution circuitry/data conversion circuit executes the tile transpose instruction to read the data from the source and write it to the destination (i.e., performs write and read operations on the multi-dimensional data) which performs a data transpose operation).
Regarding claim 21, Valentine in view of Tran teaches:
21. The data processing apparatus of claim 14, wherein the data conversion instruction comprises an operation parameter, and the data conversion circuit is configured to convert the multi-dimensional data according to the operation parameter (Valentine [0182]-[0183]: the opcode of the tile transpose instruction is an operation parameter and the execution circuitry that executes the tile transpose instruction converts/transposes the multi-dimensional source data according to the opcode).
Regarding claim 22, Valentine in view of Tran teaches:
22. The data processing apparatus of claim 21, wherein the data conversion circuit is configured to:
perform write and read operations on one or a plurality of parts of the multi-dimensional data in the data caching circuit according to the operation parameter, so as to implement a data conversion on the one or the plurality of parts of the multi-dimensional data (Valentine [0182]: the execution of the tile transpose instruction reads and writes the source matrix, i.e., performs write and read operations on a plurality of parts of the multi-dimensional data (stored in cache in the combination) so as to implement a data conversion/transpose on the source).
Regarding claim 24, Valentine in view of Tran teaches:
24. The data processing apparatus of claim 21, wherein the data conversion circuit is configured to:
combine a plurality of parts of unconverted multi-dimensional data read from the data caching circuit for outputting according to the operation parameter (Valentine [0198] discloses transposing the source by looping over columns and then rows of the destination to write each element of the source, which combines elements (i.e., parts of unconverted multi-dimensional data) in the destination and the elements are read from the source (which is cache in the combination) for outputting to the destination according to the tile transpose opcode).
Regarding claim 51, Valentine in view of Tran teaches:
51. An integrated circuit chip, comprising the data processing apparatus of claim 1 (Valentine [0104] discloses that the matrix operations circuitry may be in a care, which is indicates that the apparatus is in an integrated circuit chip).
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Valentine US 2019/0347100 in view of Tran US 2019/0187985 and Bradford US 2019/0042248.
Regarding claim 23, Valentine in view of Tran teaches:
23. The data processing apparatus of claim 21,
Valentine in view of Tran does not teach:
wherein the data conversion circuit is configured to:
concatenate a plurality of parts of converted multi-dimensional data read from the data caching circuit for outputting according to the operation parameter
However, Bradford teaches:
a data conversion circuit is configured to:
concatenate a plurality of parts of converted multi-dimensional data for outputting according to an operation parameter (Fig. 3B and corresponding description: the execution/data conversion circuitry rotates/converts multi-dimensional data read from the source matrix and concatenates it in the load buffer for outputting to the destination according to the opcode of the matrix transpose instruction 351)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the execution circuitry of Valentine in view of Tran to concatenate converted multi-dimensional data as taught by Bradford. One of ordinary skill in the art would have been motivated to make this modification to transpose data in the execution circuitry, which would reduce traffic between the execution circuitry and destination.
Claims 1 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Valentine US 2019/0347100 in view of Lao US 2003/0088600.
Regarding claim 1, Valentine teaches:
1. A data processing apparatus comprising:
a data caching circuit configured to perform data caching (Fig. 14 cache 1413); and
a data conversion circuit configured to perform read operations on to-be- converted data in the data caching circuit according to a data conversion instruction, so as to implement a data conversion on the to-be-converted data ([0120] describes that execution circuits 1427 may perform the matrix operations disclosed, Fig. 14 shows the execution circuitry as receiving data from cache 1413, and [0184] discloses that the source matrix may be stored in memory or other storage accessible to the execution circuitry, this indicates that the execution circuitry 2410 (i.e., a data conversion circuit) that executes the tile transpose instruction (i.e., a data conversion instruction), see [0185], is configured to perform read operations on the source data (i.e., to-be-converted data) in the cache according to the tile transpose instruction to implement a transpose/data converse on the to-be-converted source data).
Valentine does not teach the data conversion circuit being configured to perform write operations on to-be-converted data in the data caching circuit.
However, Lao teaches transposing data using a cache/workspace by performing write operations to write the data column-wise to the cache and read operations to read the data row-wise from the cache, see [0044]
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the processor of Valentine to transpose instructions by performing write operations to the cache and read operations from the cache as taught by Lao. One of ordinary skill in the art would have been motivated to make this modification to transpose the data in a cache/workspace free up memory bandwidth and register resources and to reduce the risk of the transpose being interrupted/overwritten.
Claim 26 is directed to a method for the data processing apparatus of claim 1 and is rejected for the same reasons as claim 1.
Claims 14, 21, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Valentine US 2019/0347100 in view of Lao US 2003/0088600 and Tran 2019/0187985.
Regarding claim 14, Valentine in view of Lao teaches:
14. The data processing apparatus of claim 1, wherein the data caching circuit is configured to cache multi-dimensional data (Valentine Fig. 14 cache 1413 caches the source matrix/multidimensional data); and
the data conversion circuit is configured to perform write and read operations on the multi- dimensional data in the data caching circuit according to the data conversion instruction, so as to implement a data conversion on the multi-dimensional data (in the combination, the execution circuitry of Valentine would perform write operations to write the source matrix/multi-dimensional data into the cache column wise and read operations to read the multi-dimensional data from the cache row-wise to implement a transpose/data conversion on the multi-dimensional data as taught by Lao [0044]),
Valentine in view of Tran, as currently mapped, does not teach:
wherein the data conversion instruction comprises a descriptor used for indicating a shape of the multi-dimensional data, and
the descriptor is used to determine a storage address corresponding to the multi-dimensional data, wherein the data conversion circuit is configured to perform the write and read operations on the multi-dimensional data according to the storage address.
However, Tran further teaches generating addresses to extract a rectangle/matrix using parameters ELEM_BYTES, ICNT0, DIM1, ICNT1, and a start address, see [0158] and [0181], where the iteration counts indicate the number of iterations of the respective loop level (i.e., data volume information) and DIM1 is the number of bytes between starting points for consecutive iterations of loop level 1 (i.e., inter-dimension offset information), see [0140].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the transpose instruction of Valentine in view of Lao to specify the parameters for the write and read operations for transposing a source matrix as taught by Tran such that the parameters are collectively a descriptor and the start address is used to determine a storage address when performing the write and read operations. One of ordinary skill in the art would have been motivated to make this modification to efficiently specify paths through memory using a small number of parameters (Tran [0139]).
Regarding claim 21, Valentine in view of Lao and Tran teaches:
21. The data processing apparatus of claim 14, wherein the data conversion instruction comprises an operation parameter, and the data conversion circuit is configured to convert the multi-dimensional data according to the operation parameter (Valentine [0182]-[0183]: the opcode of the tile transpose instruction is an operation parameter and the execution circuitry that executes the tile transpose instruction converts/transposes the multi-dimensional source data according to the opcode).
Regarding claim 25, Valentine in view of Lao and Tran teaches:
25. The data processing apparatus of claim 21,
writing the multi-dimensional data to the data caching circuit in order of a first dimension of the multi-dimensional data (Lao [0044]: Aij and Aji are copied column-wise into a cache (i.e., in order of a first dimension); and
reading the multi-dimensional data from the data caching circuit in order of a second dimension of the multi-dimensional data for outputting (Lao [0044]: the cache is then read row-wise, i.e., in order of a second dimension).
Prior Art Considerations
The known prior art of record, taken alone or in combination, was not found to teach, in combination with other limitations in the claim, the data conversion instruction further comprising write base address information and read base address information, wherein, in performing the write and read operations, the data conversion circuit is configured to perform following operations: addressing the next dimension according to the write base address information and the inter- dimension offset information, so as to perform the write operation; and addressing the next dimension according to the read base address information and the inter-dimension offset information, so as to perform the read operation, as described in claim 5.
The closest prior art of record was found to be Tran (US 20190187985) and Bradford (US 20190042248). Tran teaches specifying a start address to fetch elements of a stream, see [0245], however, Tran does not teach an instruction specifying read and write base address information that is used with inter-dimension offset information to address a next dimension for a read and write operation. Bradford teaches a base operation field of an instruction, see [0098], however Bradford does not teach specifying two base addresses (read base address information or write based address information) that is used with inter-dimension offset information to address a next dimension for a read and write operation.
Further, the known prior art of record, taken alone or in combination was not found to teach, in combination with other limitations in the claims, the data conversion circuit, in accordance with the data conversion instruction, storing each row of the to-be converted matrix to a row in the caching storage array in an in-row reverse order to form an intermediate matrix and then reading each column of the intermediate matrix to convert the to-be-converted matrix into a corresponding 270-degree rotated matrix, storing each row of the to-be-converted matrix to a row in the caching storage array in an in-row order to form an intermediate matrix and then reading each column of the intermediate matrix to convert the to-be-converted matrix into a corresponding 90-degree rotated matrix, storing each row of the to-be-converted matrix to a row in the caching storage array in an in-row reverse order to form an intermediate matrix and then reading each row of the intermediate matrix to convert the to-be-converted matrix into a corresponding 180-degree rotated matrix, and storing each row of the to-be-converted matrix to a row in the caching storage array in an in-row reverse order to form an intermediate matrix and then reading each row of the intermediate matrix to convert the to-be-converted matrix into a corresponding mirrored matrix, as described in claim 9.
The closest prior art of record was found to be Lao (US 20030088600). While Lao teaches transposing a matrix by copying column-wise into a cache and then reading row-wise from the cache, see [0044], Lao does not teach a data conversion instruction that causes a data conversion circuit to perform each of the 90-degree rotation, 180-degree rotation, 270-degree rotation, and mirror described in claim 9.
Further, the known prior art of record, taken alone or in combination, was not found to teach, in combination with other limitations in the claim, the data conversion instruction comprising a first descriptor and a second descriptor, where the data conversion circuit is configured to read multi-dimensional data from external memory according to the first descriptor to write the data to the data caching circuit and read the data in the data caching circuit into the external memory according to the second descriptor, as described in claim 19.
The closest prior art of record was found to be Tran (US 20190187985). While Tran teaches stream parameters ELEM_BYTES, ICNT0, DIM1, ICNT1, and a start address (i.e., a first descriptor), see [0158] and [0181], which is used to read data from a source, Tran does not teach an instruction specifying the parameters or parameters for performing two reads- a first read from external memory to cache and a second read from cache to external memory.
Examiner notes that claims 5 and 9 are currently rejected under 112(b) and are not currently allowable.
Claim 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2014/0331032 teaches a load/store unit that dynamically transposes data to an execution unit, see Abstract and Fig. 2B
US 2019/0347544 teaches a matrix transpose instruction having operands that indicate the matrix initial address and size for obtaining the matrix, see [0093]
US 2019/0138309 teaches a PREFETCH2D instruction that indicates the base of a 2d block of elements to be fetched into a target cache, the height and width dimensions of the 2D region to be fetched, which may be the number of bits or elements in each of the width and height dimensions, and a stride field that indicates the stride in bits or number of elements to prefetch, where the stride may be different for each dimension, see [0039]
US 2018/0189227 teaches accessing an input matrix using strided memory operations and storing the result matrix in a transpose or non-transpose form, see Abstract
US 2021/0097375 teaches rotating a weight matrix 180 degrees by flipping the elements along a vertical dimension followed by flipping along a horizontal dimension, see [0047]
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/KASIM ALLI/Examiner, Art Unit 2183 /JYOTI MEHTA/Supervisory Patent Examiner, Art Unit 2183
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