DETAILED ACTION
This action is responsive to the communication filed 9 December 2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
The instant application’s status as a 371 of PCT/CN2022/117731, claiming priority to Chinese Patent Application No. CN202111188690.4, filed 12 October 2021 is acknowledged.
Election/Restrictions
Applicant’s election with traverse of the Species 2 claims 1-7 and 11-18 in the reply filed on 5 September 2025 is acknowledged.
The Requirement for Restriction/Election mailed 1 August 2025 was made final in the Non-Final Rejection mailed 24 September 2025.
Applicant indicated claims 5 and 18 read on the elected Species 2 embodiment. Claims 8-10 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim.
Action on the merits of the Species 2 claims 1-7 and 11-20 are as follows.
Response to Arguments
Applicant’s arguments filed 9 December 2025 with respect to the drawing objection have been fully considered but they are not persuasive.
Regarding the drawing objections, Applicant states:
In this case, an illustration showing a 'wave shape' is not necessary for understanding because a 'wave shape' has a well understood and established meaning, and in view of the existing 'broken line shape' pattern shown in FIG. 13 (attached below) which already resembles a commonly known 'wave shape' but with sharp transitions rather than rounded ones. Therefore, based on the well-established meaning of a 'wave shape', and based on the context of the 'broken line shape' pattern of FIG. 13, one of ordinary skill in the art, based on the Applicant's disclosure, would understand that a 'wave shape' would have a similar pattern as shown in FIG. 13, but with rounded transitions instead of the sharp transitions of FIG. 13. As such, Applicant submits that a drawing showing a 'wave shape' pattern is not necessary for understanding such a feature and requests withdrawal of the objection.
Applicant Arguments/Remarks Made in an Amendment (filed 9 December 2025) at 7-8. The Examiner respectfully disagrees. Reproduced below is a non-exhaustive list of electrode shapes specifically disclosed in each respective references as having a “wave shape” different from the “wave shape” understanding urged by Applicant:
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2024/0329787; [0072]: “As shown in FIG. 4 , the metal line ML2 may be configured in various wave shapes, such as a 1-point wave shape as shown in (a) of FIG. 4 , a 2-point wave shape as shown in (b) of FIG. 4 , a 3-point wave shape as shown in (c) of FIG. 4 , a 4-point wave shape as shown in (d) of FIG. 4 , and the like.”
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2024/0329787; [0082]: “As shown in FIG. 5 , when the metal lines between the nodes are configured in the form of a sine wave, it can be configured in the form of a top/bottom array wave shape as shown in (a) of FIG. 5 , a top array as shown in (b) of FIG. 5 , a bottom array as shown in (c) of FIG. 5 , or mixed arrays as shown in (d) and (e) of FIG. 5 .”
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2023/0418115; [0096]: “In some optional embodiments, the first extension segments 111 have wave shapes, each first extension segment 111 includes at least two bending segments q with different waveforms extending along the first direction Y, and in adjacent first electrodes 1 along the second direction X, bending segments q with a same waveform are partly staggered from each other in the first direction Y.”
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2019/0058153; Claim 1: “[T]he array substrate includes top electrodes [201] in a wave shape . . . .”
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2020/0303472; [0134]: “In order to further alleviate diffraction, both sides in an extending direction of the anode and the cathode in the PMOLED have a wave shape, and the wave crests of the two sides are oppositely disposed and the wave troughs of the two sides are oppositely disposed, as shown in FIG. 17.”
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2014/0203258 ; [0048]: “In the embodiment shown in FIG. 1, the first electrode 12 is configured to have the grating structure with an uneven thickness and a wave shape.”
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2009/0224237; [0068]: “After that, the first conductive layer 63 a and the second conductive layer 63 b having continuous regular wave shape are formed as shown in FIG. 2C by solidifying with drying, baking, or the like.”
In view of the abovementioned electrodes having a “wave shape” disclosed in the art, Applicant’s assertion that there is a “well-established” meaning of a “wave shape” is clearly unsupported.
Moreover, the Examiner respectfully notes that nowhere does the original disclosure state that the “wave shape” should be interpreted in the context of the “broken line shape,” that the “broken line shape” resembles a commonly known “wave shape,” that the “wave shape” is similar to the “broken line shape,” or that the wave shape includes “rounded transitions,” as asserted by Applicant.
Accordingly, Applicant’s argument regarding the drawing objection is unpersuasive.
Applicant’s arguments filed 9 December 2025 with respect to the 35 U.S.C. §§ 102 and 103 rejections of claims 1-7 and 11-20 have been fully considered but they are not persuasive.
Regarding the rejections, Applicant states:
Liu describes an interconnection between the auxiliary cathode and the cathode through a Via3 in the display area, positioned in the anode-spacing region to directly tie together the auxiliary cathode and the cathode in the display area (Liu, paragraphs 0278-0279).
Importantly, Liu's non-display (border) area has an arrangement where each of the auxiliary layer and the cathode layer are separately connected to a peripheral "second electrode 3". Liu's auxiliary cathode 6 is connected to the second conductive pattern 32 of the second electrode via a bridging first conductive connection portion 10 and a via Via4 at their overlap, while Liu's cathode 51 is connected to that same second conductive pattern 32 through a separate overlap region and via X3 (Liu, paragraphs 0297-0300; 0307-0308; 0321-0326).
In other words, Liu discloses using a shared bus arrangement in the non-display area topology rather than a through-layer via directly connecting the auxiliary cathode and the cathode. Therefore, Liu fails to teach or suggest "a second part of the first electrode layer is located in the border area of the display panel, and a through-layer via directly connects the second part of the first electrode layer in parallel to a second part of the cathode layer that is located in the border area" as now recited in Applicant's claim 1 as-amended.
For context, Applicant refers to FIG. 5, as attached below, showing the via passing through the film layers in the border area, directly connecting the first electrode layer 20 to the cathode layer 30.
Applicant Arguments/Remarks Made in an Amendment (filed 9 December 2025) at 9-10. The Examiner respectfully disagrees. At the outset, the Examiner notes that Applicant presents no arguments regarding the identical claim language appearing in currently amended claim 14. In the interest of promoting clarity of the record, both claims 1 and 14 are addressed in the present Response to Arguments section.
The Examiner respectfully asserts that Liu still anticipates currently amended independent claims 1 and 14 (detailed in the rejections of claims 1 and 14, below). With regard to the new limitations appearing in claims 1 and 14, the Examiner respectfully asserts that the first conductive connection portion 10 of Liu reads on said limitations.
The Examiner also notes that nowhere in the original disclosure is a “through-layer via” feature of currently amended independent claims 1 and 14 described, let alone in a manner sufficient to support any of the purported differences from the first conductive connection portion 10 of Liu. Notably, the alleged “through-layer via” feature appears only in a single sectional view of FIG. 5. In describing other vias (e.g., via 21 of the instant application), plan views show circles to which the columnar portions of the vias are contained. No similar views are shown for the “through-layer via” feature. The FIG. 5 view of the “through-layer via” feature, which is the only support for the feature, lacks any other description in the disclosure and could just as well support an argument that the “through-layer via” is a shared connection arrangement. Accordingly, even assuming arguendo that the first conductive connection portion 10 of Liu is a “shared bus arrangement” as Applicant asserts, the disclosure lacks sufficient support to differentiate the “through-layer via” feature, as it is currently claimed, from a “shared bus arrangement.”
Accordingly, Applicant’s arguments are unpersuasive.
Drawings
The objection to the drawings made in the Non-Final Rejection mailed 24 September 2025 is maintained. Additional drawing objections also appear below.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the subject matter of:
Claim 1, specifically wherein “a through-layer via directly connects the second part of the first electrode layer in parallel to a second part of the cathode layer that is located in the border area”;
Claim 13, specifically wherein “a shape of an electrode line at the first electrode layer is a wave shape”;
Claim 14, specifically wherein “a through-layer via directly connects the second part of the first electrode layer in parallel to a second part of the cathode layer that is located in the border area”;
must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
The objections to claims 7 and 20 are withdrawn in view of Applicant’s amendment of claims 7 and 20.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1); MPEP § 608.01(o). Correction of the following is required: antecedent basis for the claimed feature “a through-layer via directly connects the second part of the first electrode layer in parallel to a second part of the cathode layer that is located in the border area” of independent claims 1 and 14 is required.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-7 and 13-20 are rejected under 35 U.S.C. § 102(a)(2) as being anticipated by U.S. Patent Publication No. 2022/0020827 (filed Mar. 15, 2021) (hereinafter “Liu”).
Regarding independent claim 1, Lee discloses: A display panel (FIG. 14a, depicting a display substrate, [0297]), comprising:
a first substrate (FIGS. 14a/15/16/17/18, disclosing a substrate formed from polyimide, [0255]);
a first electrode layer located on a side of the first substrate (FIGS. 14a/16/17/18, auxiliary cathode layer 6 located on the substrate, [0299]);
a cathode layer (FIGS. 14a/15/16/17/18, cathode layer 51, [0300]) located on a side that is of the first electrode layer and that is away from the first substrate (FIGS. 14a/15/16/17/18, depicting wherein the cathode layer 51 on a side of the auxiliary cathode layer 6 facing away from the substrate (formed under the driving circuit layer 85));
wherein the cathode layer (FIGS. 14a/15/16/17/18, cathode layer 51) covers a display area of the display panel (FIGS. 14a/15/16/17/18, depicting in, e.g., FIG. 16, wherein the cathode layer 51 covers the display area of the display substrate, [0300]), and extends to a border area of the display panel (FIGS. 14a/15/16/17/18, depicting in, e.g., FIGS. 17 and 18, wherein the cathode layer extends to a non-display area of the display substrate); and
a first part of the first electrode layer (FIGS. 14a/15/16/17/18, auxiliary cathode layer 6) is located in the display area of the display panel (FIGS. 14a/15/16/17/18, depicting in, e.g., FIG. 16, wherein a first portion of the auxiliary cathode layer 6 is located in the display area of the display substrate),
the first part of the first electrode layer (FIGS. 14a/15/16/17/18, auxiliary cathode layer 6) is connected in parallel to a first part that is of the cathode layer (FIGS. 14a/15/16/17/18, depicting in, e.g., FIG. 16, wherein the cathode layer 51 includes a first portion located in the display area of the display substrate) and that is located in the display area (FIGS. 14a/15/16/17/18, depicting in, e.g., FIG. 16, wherein the first portions of both the auxiliary cathode layer 6 and cathode layer 51 are connected in parallel; [0279]: “According to the specific structure of the above display substrate, in the display substrate provided by the embodiment of the present disclosure, by arranging the auxiliary cathode layer 6 in parallel with the cathode layer 51 . . . .”), and
a second part of the first electrode layer (FIGS. 14a/15/16/17/18, auxiliary cathode layer 6) is located in the border area of the display panel (FIGS. 14a/15/16/17/18, depicting in, e.g., FIGS. 17 and 18, wherein a first portion of the auxiliary cathode layer 6 is located in the non-display area of the display substrate), and
a through-layer via (FIG. 17, first conductive connection portion 10, [0307]) directly connects the second part of the first electrode layer in parallel to a second part of the cathode layer (FIGS. 14a/15/16/17/18, depicting in, e.g., FIGS. 17 and 18, wherein the cathode layer 51 includes a second portion located in the non-display area of the display substrate) that is located in the border area (FIGS. 14a/15/16/17/18, depicting in, e.g., FIGS. 17 and 18, wherein the second portions of both the auxiliary cathode layer 6 and cathode layer 51 are connected in parallel by the first conductive connection portion 10; [0279]: “According to the specific structure of the above display substrate, in the display substrate provided by the embodiment of the present disclosure, by arranging the auxiliary cathode layer 6 in parallel with the cathode layer 51 . . . .”).
Regarding claim 2, Liu further discloses wherein the display panel (FIG. 14a, depicting a display substrate, [0297]) further comprises:
an anode layer (FIGS. 14a/15/16/17/18, anode patterns 4, [0275]) located on a side that is of the cathode layer and that faces the first substrate (FIGS. 14a/15/16/17/18, depicting in, e.g. FIG. 16, wherein the anode patterns 4 are located on a side of the cathode layer 51 facing toward the substrate (formed under the driving circuit layer 85));
a pixel definition layer (FIGS. 14a/15/16/17/18, pixel defining layer 80, [0262]) and a light-emitting layer (FIGS. 14a/15/16/17/18, organic light emission material layers B and R, [0276]) that are located between the anode layer and the cathode layer (FIGS. 14a/15/16/17/18, depicting in, e.g. FIG. 16, wherein the pixel defining layer 80 and organic light emission material layers B and R are located between the anode patterns 4 and the cathode layer 51),
wherein the pixel definition layer (FIGS. 14a/15/16/17/18, pixel defining layer 80) comprises a plurality of pixel definition areas (FIGS. 14a/15/16/17/18, pixel defining layer 80, depicting in, e.g., FIG. 16, wherein the pixel defining layer 80 includes a plurality of openings),
the light-emitting layer (FIGS. 14a/15/16/17/18, organic light emission material layers B and R) comprises a plurality of light-emitting units (FIGS. 14a/15/16/17/18, depicting in, e.g. FIG. 16, wherein there are a plurality of organic light emission material layers, e.g., B and R), and
the light-emitting units are in a one-to-one correspondence with the pixel definition areas and are located in the pixel definition areas (FIGS. 14a/15/16/17/18, depicting in, e.g. FIG. 16, wherein in each opening in the pixel defining layer 80, a single organic light emission material layer B or R is formed, such that the organic light emission material layer B and R is correspond to the openings in the pixel defining layer 80); and
a control circuit layer (FIGS. 14a/15/16/17/18, the portion of the driving circuit layer 85 including an active layer Active, a first insulating layer GI1, a first gate metal layer Gate1, a second insulating layer GI2, a second gate metal layer Gate2, [0255], [0281]) located on a side that is of the anode layer and that is away from the cathode layer (FIGS. 14a/15/16/17/18, depicting in, e.g. FIG. 16, wherein the portion of the driving circuit layer 85 including an active layer Active, a first insulating layer GI1, a first gate metal layer Gate1, a second insulating layer GI2, a second gate metal layer Gate2 is located on a side of the anode patterns 4 facing away from the cathode layer 51).
Regarding claim 3, Liu further discloses wherein the first electrode layer (FIGS. 14a/15/16/17/18, auxiliary cathode layer 6) is located on a side that is of the anode layer and that is away from the cathode layer (FIGS. 14a/15/16/17/18, depicting in, e.g. FIG. 16, wherein the auxiliary cathode layer 6 is located on a side of the anode patterns 4 facing away from the cathode layer 51).
Regarding claim 4, Liu further discloses wherein the first electrode layer (FIGS. 14a/15/16/17/18, auxiliary cathode layer 6) is located between the anode layer and the control circuit layer (FIGS. 14a/15/16/17/18, depicting in, e.g. FIG. 16, wherein the auxiliary cathode layer 6 is located between the anode patterns 4 and the portion of the driving circuit layer 85 including an active layer Active, a first insulating layer GI1, a first gate metal layer Gate1, a second insulating layer GI2, a second gate metal layer Gate2).
Regarding claim 5, Liu further discloses wherein there is a first insulation layer (FIGS. 14a/15/16/17/18, disclosing a third insulating layer ILD disposed on the portion of the driving circuit layer 85 including an active layer Active, a first insulating layer GI1, a first gate metal layer Gate1, a second insulating layer GI2, a second gate metal layer Gate2, [0255]) between the control circuit layer and the first electrode layer (FIGS. 14a/15/16/17/18, disclosing wherein the third insulating layer ILD would be located between the portion of the driving circuit layer 85 including an active layer Active, a first insulating layer GI1, a first gate metal layer Gate1, a second insulating layer GI2, a second gate metal layer Gate2 and the auxiliary electrode layer 6), and
there is a second insulation layer (FIGS. 14a/15/16/17/18, planarization layer 81, [0255], [0277], [0319]) between the first electrode layer and the anode layer (FIGS. 14a/15/16/17/18, depicting in, e.g. FIG. 16, wherein the planarization 81 is located between the auxiliary cathode layer 6 and the anode patterns 4),
wherein the control circuit layer is electrically connected to the anode layer by using a first via (FIGS. 14a/15/16/17/18, disclosing a source-drain metal layer, [0255], [0261]), and the first electrode layer is electrically connected to the cathode layer by using a second via (FIGS. 14a/15/16/17/18, depicting in, e.g. FIG. 15 and 16, wherein the auxiliary cathode layer 6 is electrically connected to the cathode layer 51 by using via hole Via3, [0278]).
Regarding claim 6, Liu further discloses wherein the second via penetrates a gap between adjacent light-emitting units (FIGS. 14a/15/16/17/18, depicting in, e.g. FIG. 15 and 16, wherein the via hole Via3 penetrates a gap between adjacent organic light emission material layer B and R).
Regarding claim 7, Liu further discloses wherein a projection of the first electrode layer (FIGS. 14a/15/16/17/18, auxiliary cathode layer 6) on a plane on which the first substrate is located at least partially overlaps with a projection of the light-emitting layer (FIGS. 14a/15/16/17/18, organic light emission material layer B and R) on the plane on which the first substrate is located (FIGS. 14a/15/16/17/18, depicting in, e.g. FIG. 16, wherein projections of the auxiliary cathode layer 6 and organic light emission material layer B and R overlap in a direction of the substrate (formed under the driving circuit layer 85)).
Regarding claim 13, Liu further discloses wherein a shape of an electrode line at the first electrode layer is a wave shape or a broken line shape (FIGS. 14a/15/16/17/18, depicting in, e.g., FIG. 15, wherein at a portion of the auxiliary electrode layer 6 has a stair-stepped (i.e., broken line) shape; see also Annotated Liu FIG. 15, below).
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Annotated Liu FIG. 15
Regarding independent claim 14, Liu discloses: An electronic device ([0233]-[0234]: “Therefore, when the display device provided by the embodiment of the present disclosure includes the above-mentioned display substrate, it also has the above-mentioned beneficial effects, which will not be repeated here. It should be noted that the display device may be any product or component with a display function, such as a TV, a monitor, a digital photo frame, a mobile phone, a tablet computer, and so on.”), comprising: a display having a display panel (FIG. 14a, depicting a display substrate, [0297]), the display panel comprising:
a first substrate (FIGS. 14a/15/16/17/18, disclosing a substrate formed from polyimide, [0255]);
a first electrode layer located on a side of the first substrate (FIGS. 14a/16/17/18, auxiliary cathode layer 6 located on the substrate, [0299]);
a cathode layer (FIGS. 14a/15/16/17/18, cathode layer 51, [0300]) located on a side that is of the first electrode layer and that is away from the first substrate (FIGS. 14a/15/16/17/18, depicting wherein the cathode layer 51 on a side of the auxiliary cathode layer 6 facing away from the substrate (formed under the driving circuit layer 85));
wherein the cathode layer (FIGS. 14a/15/16/17/18, cathode layer 51) covers a display area of the display panel (FIGS. 14a/15/16/17/18, depicting in, e.g., FIG. 16, wherein the cathode layer 51 covers the display area of the display substrate, [0300]), and extends to a border area of the display panel (FIGS. 14a/15/16/17/18, depicting in, e.g., FIGS. 17 and 18, wherein the cathode layer extends to a non-display area of the display substrate); and
a first part of the first electrode layer (FIGS. 14a/15/16/17/18, auxiliary cathode layer 6) is located in the display area of the display panel (FIGS. 14a/15/16/17/18, depicting in, e.g., FIG. 16, wherein a first portion of the auxiliary cathode layer 6 is located in the display area of the display substrate),
the first part of the first electrode layer (FIGS. 14a/15/16/17/18, auxiliary cathode layer 6) is connected in parallel to a first part that is of the cathode layer (FIGS. 14a/15/16/17/18, depicting in, e.g., FIG. 16, wherein the cathode layer 51 includes a first portion located in the display area of the display substrate) and that is located in the display area (FIGS. 14a/15/16/17/18, depicting in, e.g., FIG. 16, wherein the first portions of both the auxiliary cathode layer 6 and cathode layer 51 are connected in parallel; [0279]: “According to the specific structure of the above display substrate, in the display substrate provided by the embodiment of the present disclosure, by arranging the auxiliary cathode layer 6 in parallel with the cathode layer 51 . . . .”), and
a second part of the first electrode layer (FIGS. 14a/15/16/17/18, auxiliary cathode layer 6) is located in the border area of the display panel (FIGS. 14a/15/16/17/18, depicting in, e.g., FIGS. 17 and 18, wherein a first portion of the auxiliary cathode layer 6 is located in the non-display area of the display substrate), and
a through-layer via (FIG. 17, first conductive connection portion 10, [0307]) directly connects the second part of the first electrode layer in parallel to a second part of the cathode layer (FIGS. 14a/15/16/17/18, depicting in, e.g., FIGS. 17 and 18, wherein the cathode layer 51 includes a second portion located in the non-display area of the display substrate) that is located in the border area (FIGS. 14a/15/16/17/18, depicting in, e.g., FIGS. 17 and 18, wherein the second portions of both the auxiliary cathode layer 6 and cathode layer 51 are connected in parallel by the first conductive connection portion 10; [0279]: “According to the specific structure of the above display substrate, in the display substrate provided by the embodiment of the present disclosure, by arranging the auxiliary cathode layer 6 in parallel with the cathode layer 51 . . . .”).
Regarding claim 15, Liu further discloses wherein the display panel (FIG. 14a, depicting a display substrate, [0297]) further comprises:
an anode layer (FIGS. 14a/15/16/17/18, anode patterns 4, [0275]) located on a side that is of the cathode layer and that faces the first substrate (FIGS. 14a/15/16/17/18, depicting in, e.g. FIG. 16, wherein the anode patterns 4 are located on a side of the cathode layer 51 facing toward the substrate (formed under the driving circuit layer 85));
a pixel definition layer (FIGS. 14a/15/16/17/18, pixel defining layer 80, [0262]) and a light-emitting layer (FIGS. 14a/15/16/17/18, organic light emission material layers B and R, [0276]) that are located between the anode layer and the cathode layer (FIGS. 14a/15/16/17/18, depicting in, e.g. FIG. 16, wherein the pixel defining layer 80 and organic light emission material layers B and R are located between the anode patterns 4 and the cathode layer 51),
wherein the pixel definition layer (FIGS. 14a/15/16/17/18, pixel defining layer 80) comprises a plurality of pixel definition areas (FIGS. 14a/15/16/17/18, pixel defining layer 80, depicting in, e.g., FIG. 16, wherein the pixel defining layer 80 includes a plurality of openings),
the light-emitting layer (FIGS. 14a/15/16/17/18, organic light emission material layers B and R) comprises a plurality of light-emitting units (FIGS. 14a/15/16/17/18, depicting in, e.g. FIG. 16, wherein there are a plurality of organic light emission material layers, e.g., B and R), and
the light-emitting units are in a one-to-one correspondence with the pixel definition areas and are located in the pixel definition areas (FIGS. 14a/15/16/17/18, depicting in, e.g. FIG. 16, wherein in each opening in the pixel defining layer 80, a single organic light emission material layer B or R is formed, such that the organic light emission material layer B and R is correspond to the openings in the pixel defining layer 80); and
a control circuit layer (FIGS. 14a/15/16/17/18, the portion of the driving circuit layer 85 including an active layer Active, a first insulating layer GI1, a first gate metal layer Gate1, a second insulating layer GI2, a second gate metal layer Gate2, [0255], [0281]) located on a side that is of the anode layer and that is away from the cathode layer (FIGS. 14a/15/16/17/18, depicting in, e.g. FIG. 16, wherein the portion of the driving circuit layer 85 including an active layer Active, a first insulating layer GI1, a first gate metal layer Gate1, a second insulating layer GI2, a second gate metal layer Gate2 is located on a side of the anode patterns 4 facing away from the cathode layer 51).
Regarding claim 16, Liu further discloses wherein the first electrode layer (FIGS. 14a/15/16/17/18, auxiliary cathode layer 6) is located on a side that is of the anode layer and that is away from the cathode layer (FIGS. 14a/15/16/17/18, depicting in, e.g. FIG. 16, wherein the auxiliary cathode layer 6 is located on a side of the anode patterns 4 facing away from the cathode layer 51).
Regarding claim 17, Liu further discloses wherein the first electrode layer (FIGS. 14a/15/16/17/18, auxiliary cathode layer 6) is located between the anode layer and the control circuit layer (FIGS. 14a/15/16/17/18, depicting in, e.g. FIG. 16, wherein the auxiliary cathode layer 6 is located between the anode patterns 4 and the portion of the driving circuit layer 85 including an active layer Active, a first insulating layer GI1, a first gate metal layer Gate1, a second insulating layer GI2, a second gate metal layer Gate2).
Regarding claim 18, Liu further discloses wherein there is a first insulation layer (FIGS. 14a/15/16/17/18, disclosing a third insulating layer ILD disposed on the portion of the driving circuit layer 85 including an active layer Active, a first insulating layer GI1, a first gate metal layer Gate1, a second insulating layer GI2, a second gate metal layer Gate2, [0255]) between the control circuit layer and the first electrode layer (FIGS. 14a/15/16/17/18, disclosing wherein the third insulating layer ILD would be located between the portion of the driving circuit layer 85 including an active layer Active, a first insulating layer GI1, a first gate metal layer Gate1, a second insulating layer GI2, a second gate metal layer Gate2 and the auxiliary electrode layer 6), and
there is a second insulation layer (FIGS. 14a/15/16/17/18, planarization layer 81, [0255], [0277], [0319]) between the first electrode layer and the anode layer (FIGS. 14a/15/16/17/18, depicting in, e.g. FIG. 16, wherein the planarization 81 is located between the auxiliary cathode layer 6 and the anode patterns 4),
wherein the control circuit layer is electrically connected to the anode layer by using a first via (FIGS. 14a/15/16/17/18, disclosing a source-drain metal layer, [0255], [0261]), and the first electrode layer is electrically connected to the cathode layer by using a second via (FIGS. 14a/15/16/17/18, depicting in, e.g. FIG. 15 and 16, wherein the auxiliary cathode layer 6 is electrically connected to the cathode layer 51 by using via hole Via3, [0278]).
Regarding claim 19, Liu further discloses wherein the second via penetrates a gap between adjacent light-emitting units (FIGS. 14a/15/16/17/18, depicting in, e.g. FIG. 15 and 16, wherein the via hole Via3 penetrates a gap between adjacent organic light emission material layer B and R).
Regarding claim 20, Liu further discloses wherein a projection of the first electrode layer (FIGS. 14a/15/16/17/18, auxiliary cathode layer 6) on a plane on which the first substrate is located at least partially overlaps with a projection of the light-emitting layer (FIGS. 14a/15/16/17/18, organic light emission material layer B and R) on the plane on which the first substrate is located (FIGS. 14a/15/16/17/18, depicting in, e.g. FIG. 16, wherein projections of the auxiliary cathode layer 6 and organic light emission material layer B and R overlap in a direction of the substrate (formed under the driving circuit layer 85)).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 11 and 12 are rejected under 35 U.S.C. § 103 as being unpatentable over Liu.
Regarding claim 11, Liu discloses in the FIGS. 14a/15/16/17/18 embodiment wherein the first electrode layer (FIGS. 14a/15/16/17/18, auxiliary cathode layer 6) comprises a plurality of first electrode lines (FIGS. 14a/15/16/17/18, depicting in, e.g., FIGS. 14a and 15, wherein the auxiliary cathode layer 6 includes a plurality of electrode lines extending horizontally), the plurality of light-emitting units (FIGS. 14a/15/16/17/18, organic light emission material layer G, B, and R) comprise a plurality of rows of light-emitting units (FIGS. 14a/15/16/17/18, depicting in, e.g., FIGS. 14a and 15, wherein the organic light emission material layer G, B, and R form a plurality of rows), the first electrode lines extend in a row direction (FIGS. 14a/15/16/17/18, depicting in, e.g., FIGS. 14a and 15, wherein the auxiliary cathode layer 6 includes a plurality of electrode lines extending horizontally).
Liu does not disclose in the embodiment disclosed in FIGS. 14a/15/16/17/18 wherein a projection of the first electrode line on the plane on which the first substrate is located is within a projection range of a gap between adjacent rows of the light-emitting units on the plane on which the first substrate is located.
In FIG. 14b, however, Liu discloses wherein a projection of the first electrode line on the plane on which the first substrate is located is within a projection range of a gap between adjacent rows of the light-emitting units on the plane on which the first substrate is located (FIG. 14b, depicting wherein the projections toward the substrate (formed under the driving circuit layer 85) of the plurality of auxiliary cathode layer 6 lines extending horizontally are disposed in the gap between the adjacent rows of organic light emission material layers G, B, and R). Regarding the configuration of the auxiliary cathode layer 6 lines, in [0285], Liu discloses: “The orthographic projection of the auxiliary cathode layer 6 on the substrate is located inside the orthographic projection of the anode spacing area on the substrate, so that the orthographic projection of the auxiliary cathode layer 6 on the substrate does not overlap the orthographic projection of the anode pattern 4 on the substrate, so that the segment step formed by the auxiliary cathode layer 6 will not affect the anode pattern 4, which ensures the flatness of the anode pattern 4 and improves color separation phenomenon during the display of the display substrate.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the disclosed auxiliary cathode layer 51 line configuration of FIGS. FIGS. 14a/15/16/17/18 with the disclosed auxiliary cathode layer 51 line configuration of FIG. 14b in order improve color separation and improve flatness of the anode pattern 4. See Liu [0285].
Regarding claim 12, the FIGS. 14a/15/16/17/18 embodiment of Liu as modified by the FIG. 14b embodiment of Liu further discloses wherein the first electrode layer (FIGS. 14a/14b/15/16/17/18, auxiliary cathode layer 6) further comprises a plurality of second electrode lines (FIGS. 14a/14b/15/16/17/18, depicting in, e.g., FIGS. 14b, wherein the auxiliary cathode layer 6 includes a plurality of electrode lines extending vertically), the second electrode lines extend in a column direction (FIGS. 14a/14b/15/16/17/18, depicting in, e.g., FIGS. 14b, wherein the auxiliary cathode layer 6 includes a plurality of electrode lines extending vertically), the plurality of light-emitting units (FIGS. 14a/14b/15/16/17/18, organic light emission material layer G, B, and R) comprise a plurality of columns of light- emitting units (FIGS. 14a/14b/15/16/17/18, depicting in, e.g., FIGS. 14b, wherein the organic light emission material layer G, B, and R form a plurality of columns), and a projection of the second electrode line on the plane on which the first substrate is located is within a projection range of a gap between adjacent columns of the light-emitting units on the plane on which the first substrate is located (FIG. 14b, depicting wherein the projections toward the substrate (formed under the driving circuit layer 85) of the plurality of auxiliary cathode layer 6 lines extending vertically are disposed in the gap between the adjacent columns of organic light emission material layers G, B, and R).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: U.S. Patent Publication No. 2023/0104461 (filed Dec. 20, 2019).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ADAM D WEILAND/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813