DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 16 April 2026 has been entered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
The instant application’s status as a 371 of PCT/CN2022/117731, claiming priority to Chinese Patent Application No. CN202111188690.4, filed 12 October 2021 is acknowledged.
Election/Restrictions
Applicant’s election with traverse of the Species 2 claims 1-7 and 11-18 in the reply filed on 5 September 2025 is acknowledged.
The Requirement for Restriction/Election mailed 1 August 2025 was made final in the Non-Final Rejection mailed 24 September 2025.
Applicant indicated claims 5 and 18 read on the elected Species 2 embodiment. Claims 8-10 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim.
Action on the merits of the Species 2 claims 1-7 and 11-20 are as follows.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-7 and 11-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Drawings
The objection to the drawings made in the Non-Final Rejection mailed 24 September 2025 is withdrawn, responsive to Applicant’s amendment of the claim.
The objections to the drawings made in the Final Rejection mailed 18 February 2026 are withdrawn, responsive to Applicant’s amendment of the claims.
Claim Objections
Claims 1, 3, 14, and 16 are objected to because of the following informalities:
Regarding claim 1: claim 1 contains grammatical errors and should read: “a cathode layer located on a side control circuit layer located on a side of the anode layer
Regarding claim 3: claim 3 contains grammatical errors and should read: “wherein the first electrode layer is located on a side
Regarding claim 14: claim 14 contains grammatical errors and should read: “a cathode layer located on a side
Regarding claim 16: claim 16 contains grammatical errors and should read: “wherein the first electrode layer is located on a side
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-7 and 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication No. 20200212350 (filed Nov. 14, 2019) (hereinafter “Hsu”) in view of U.S. Patent Publication No. 20220020827 (effectively filed Mar. 23, 2020) (hereinafter “Liu”).
Regarding independent claim 1, Hsu discloses: A display panel (FIG. 3, display device 10, [0014]), comprising:
a first substrate (FIG. 1C, substrate 100, [0014]);
a first electrode layer (FIG. 1C, auxiliary electrode 110, [0015]) located on a side of the first substrate (FIG. 1C, depicting wherein the auxiliary electrode 110 is located on a side of the substrate 100) comprising
a first part that is located in a display area of the display panel (FIG. 1C, depicting wherein the auxiliary electrode 110 includes a first part that is located in an active region A of the display device 10, [0015]) and
a second part that is located in a border area of the display panel (FIG. 1C, depicting wherein the auxiliary electrode 110 includes a second part that is located in a peripheral region B of the display device 10, [0015]);
a cathode layer (FIG. 1C, second electrode E2, [0022]) located on a side that is of the first electrode layer and that is away from the first substrate (FIG. 1C, depicting wherein the second electrode E2 is located on a side of the auxiliary electrode 110 that is away from the substrate 100),
the cathode layer comprising a first part that covering the display area of the display panel (FIGS. 3/1C, depicting wherein the second electrode E2 includes a first part that covers the active region A of the display device 10) and a second part extending to the border area of the display panel (FIGS. 3/1C, depicting wherein the second electrode E2 includes a second part that extends to the peripheral region B of the display device 10);
an anode layer (FIG. 1C, first electrode E1, [0022]) located on a side of the cathode layer and that faces the first substrate (FIG. 1C, depicting wherein the first electrode E1 is located on a side of the second electrode E2 that is away from the substrate 100); and
a control circuit layer (FIG. 1C, depicting, e.g., a layer including an active element T2 and chip 210, [0014], [0022]) located on a side of the anode layer and that is away from the cathode layer (FIG. 1C, depicting wherein the layer including layer including an active element T2 and chip 210 is located on a side of the first electrode E1 that is away from the second electrode E2), wherein
in the display area,
one or more first vias directly connect the anode layer to the control circuit layer (FIGS. 1B/1C, depicting wherein the first electrode E1 is directly connected to the layer including an layer including an active element T2 and chip 210 by a via in an opening O2, [0022]), and
in the border area,
the second part of the first electrode layer is directly connected to the second part of the cathode layer (FIGS. 1B/1C, depicting wherein the second part of the auxiliary electrode 110 is directly connected to the second electrode E2 in the peripheral region B), and
the control circuit layer directly connects to the second part of the first electrode layer (FIGS. 1B/1C, depicting wherein the layer including an active element T2 and chip 210 is directly connected to the second electrode E2 in the peripheral region B).
Hsu does not specifically disclose wherein one or more second vias directly connect the first part of the cathode layer to the first part of the first electrode layer.
In the same field of endeavor, Liu discloses a display panel (FIGS. 14A/15/16, depicting a display substrate, [0297]) including a first electrode layer configuration wherein the first electrode layer (FIGS. 14A/15/16, auxiliary cathode layer 6, [0291]) includes a plurality of electrode lines (FIGS. 14A/15/16, depicting wherein the auxiliary cathode layer 6 is formed as a mesh structure formed from a plurality of auxiliary cathode layer 6 lines), and further wherein the first electrode layer is disposed between a control circuit layer and an anode layer (FIGS. 14A/15/16, depicting wherein the auxiliary cathode layer 6 formed as a mesh structure formed from a plurality of auxiliary cathode layer 6 lines is disposed between a driving circuit layer 85 and an anode pattern 4 layer). Liu states in [0146]: “On one hand, in order to ensure the transmittance of the cathode, the Mg/Ag metal is made very thin; on the other hand, the negative power signal line (VS S) electrically connected to the cathode in the related art is only a wiring line located at the edge of the display substrate. Therefore, the resistance of the cathode is relatively large (when the cathode is made of Mg/Ag alloy, the square resistance of the cathode is between 10 Ω/sq-15 Ω/sq). The IR Drop problem caused by the cathode leads to uneven display of the display substrate and the power consumption of the display substrate becomes larger.” Regarding the configuration of the first electrode 2, in [0164], Liu states: “In the display substrate provided by the foregoing embodiment, the space between the anode patterns 4 is used or the position of the anode pattern 4 is adjusted, so as to realize the rational layout of the first electrode 2 and interconnect with the upper cathode, which is equivalent to introducing a layer of an auxiliary electrode connected in parallel with the cathode to the display substrate, thereby effectively reducing the resistance of the cathode, and improving the IR Drop problem of the cathode.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed display device 10 of Hsu with by substituting the auxiliary cathode 6 layer configuration of Liu in order to reduce the resistance of the cathode and improve the IR drop problem of the cathode. See Liu [0164].
Moreover, substitution of the auxiliary cathode 6 layer configuration of Liu would result in a configuration wherein one or more second vias (Liu FIGS. 14A/15/16, depicting wherein the display substrate of Liu includes one or more vias Via3, [0389]) directly connect the first part of the cathode layer to the first part of the first electrode layer (Hsu FIGS. 3/1B/1C; Liu FIGS. 14A/15/16; depicting wherein the vias via3 would directly connect the first part of the second electrode E2 layer to the first part of the auxiliary electrode layer 110, as modified by Liu).
Regarding claim 2, Hsu in view of Liu further discloses a pixel definition layer (FIG. 1C, pixel defining layer 160, [0014]) and a light-emitting layer (FIG. 1C, light emitting layer EL, [0022]) that are located between the anode layer and the cathode layer (FIG. 1C, depicting wherein the pixel defining layer 160 and light emitting layer EL are located between the first electrode E1 and the second electrode E2), wherein the pixel definition layer comprises a plurality of pixel definition areas (FIGS. 1B/1C, depicting wherein the pixel defining layer 160 comprises a plurality of pixel definition areas), the light-emitting layer comprises a plurality of light-emitting units (FIGS. 1B/1C, depicting wherein the light emitting layer EL comprises a plurality of light-emitting units), and the light-emitting units are in a one-to-one correspondence with the pixel definition areas and are located in the pixel definition areas (FIGS. 1B/1C, depicting wherein the light emitting units of the light emitting layer EL are in a one-to-one correspondence with the pixel definition areas and are located in the pixel definition areas), and wherein a configuration of the first electrode layer differs based on a location of the first electrode layer at each of the plurality of light-emitting unit relative to a signal input end of the display panel, such that brightness of the display panel is more uniform (Hsu FIGS. 3/1B/1C; Liu FIGS. 14A/15/16, depicting wherein the configuration of the auxiliary electrode 110 layer, as modified by Liu, differs based on a location of the auxiliary electrode 110 at each of the light emitting units of the light emitting layer EL relative to an end of the display panel in which the semiconductor chip 210 is disposed, such that the brightness of the display device 10 is more uniform, as disclosed in [0146] and [0164] of Liu and [0038] of Hsu).
Regarding claim 3, Hsu in view of Liu further discloses wherein the first electrode layer (FIG. 1C, auxiliary electrode 110) is located on a side that is of the anode layer and that is away from the cathode layer (Hsu FIGS. 3/1B/1C; Liu FIGS. 14A/15/16; depicting wherein the auxiliary electrode 110 layer, as modified by Liu, is located on a side of the first electrode E1 and that is away from the second electrode E2).
Regarding claim 4, Hsu in view of Liu further discloses wherein the first electrode layer (FIG. 1C, auxiliary electrode 110) is located between the anode layer and the control circuit layer (Hsu FIGS. 3/1B/1C; Liu FIGS. 14A/15/16; depicting wherein the auxiliary electrode 110 layer, as modified by Liu, would be located between the first electrode E1 and the layer including an active element T2 and chip 210).
Regarding claim 5, Hsu in view of Liu further discloses wherein there is a first insulation layer between the control circuit layer and the first electrode layer (Hsu FIGS. 3/1B/1C; Liu FIGS. 14A/15/16, depicting wherein the auxiliary electrode 110 layer, as modified by Liu, would result in a configuration wherein an insulating layer 140 would be disposed between the layer including an active element T2 and chip 210 and the auxiliary electrode 110 layer, [0021]), and there is a second insulation layer between the first electrode layer and the anode layer (Hsu FIGS. 3/1B/1C; Liu FIGS. 14A/15/16, depicting wherein the auxiliary electrode 110 layer, as modified by Liu, would result in a configuration wherein an insulating layer 150 would be disposed between the auxiliary electrode 110 layer and the first electrode E2 layer, [0021]).
Regarding claim 6, Hsu in view of Liu further discloses wherein the one or more second vias respectively penetrate gap between adjacent light-emitting units (Hsu FIGS. 3/1B/1C; Liu FIGS. 14A/15/16, depicting wherein the auxiliary electrode 110 layer, as modified by Liu, would result in a configuration wherein the one or more vias Via3 would penetrate gaps between adjacent light emitting units of the light emitting layer EL as disclosed in Liu).
Regarding claim 7, Hsu in view of Liu further discloses wherein a projection of the first electrode layer on a plane on which the first substrate is located at least partially overlaps with a projection of the light-emitting layer on the plane on which the first substrate is located (Hsu FIGS. 3/1B/1C; Liu FIGS. 14A/15/16, depicting wherein the auxiliary electrode 110 layer, as modified by Liu, would result in a configuration wherein a projection of the auxiliary electrode 110 layer on a plane on which the substrate 100 is located at least partially overlaps with a projection of the light emitting layer EL on a plane on which the substrate 100 is located).
Regarding claim 11, Hsu in view of Liu further discloses wherein the first electrode layer comprises a plurality of first electrode lines (Hsu FIGS. 3/1B/1C; Liu FIGS. 14A/15/16, depicting wherein the auxiliary electrode 110 layer, as modified by Liu, would include a plurality of lines as disclosed in Liu), the plurality of light-emitting units comprise a plurality of rows of light-emitting units (Hsu FIGS. 3/1B/1C, depicting wherein the light emitting units of the light emitting layer EL include a plurality of rows of light emitting units of the light emitting layer EL), the first electrode lines extend in a row direction (Hsu FIGS. 3/1B/1C; Liu FIGS. 14A/15/16, depicting wherein the auxiliary electrode 110 layer, as modified by Liu, would include a plurality of lines extending in a row direction as disclosed in Liu), and a projection of the first electrode line on the plane on which the first substrate is located is within a projection range of a gap between adjacent rows of the light-emitting units on the plane on which the first substrate is located (Hsu FIGS. 3/1B/1C; Liu FIGS. 14A/15/16, depicting wherein the auxiliary electrode 110 layer, as modified by Liu, would result in a configuration wherein a projection of the lines on the plane on which the substrate 100 is located would be within a projection range of a gap between adjacent rows of light emitting units of the light emitting layer EL on the plane on which the substrate 100 is located, as disclosed in Liu).
Regarding claim 12, Hsu in view of Liu further discloses wherein the first electrode layer further comprises a plurality of second electrode lines, the second electrode lines extend in a column direction, the plurality of light-emitting units comprise a plurality of columns of light-emitting units, and a projection of the second electrode line on the plane on which the first substrate is located is within a projection range of a gap between adjacent columns of the light-emitting units on the plane on which the first substrate is located.
Regarding claim 13, Hsu in view of Liu further discloses a shape of an electrode line at the first electrode layer is a broken line shape (Hsu FIGS. 3/1B/1C; Liu FIGS. 14A/15/16, depicting wherein the auxiliary electrode 110 layer, as modified by Liu, would result in a configuration wherein the electrode lines would form a broken line shape).
Regarding independent claim 14, Hsu discloses: An electronic device, comprising: a display having a display panel (FIG. 3, display device 10, [0014]), the display panel comprising:
a first substrate (FIG. 1C, substrate 100, [0014]);
a first electrode layer (FIG. 1C, auxiliary electrode 110, [0015]) located on a side of the first substrate (FIG. 1C, depicting wherein the auxiliary electrode 110 is located on a side of the substrate 100) comprising
a first part that is located in a display area of the display panel (FIG. 1C, depicting wherein the auxiliary electrode 110 includes a first part that is located in an active region A of the display device 10, [0015]) and
a second part that is located in a border area of the display panel (FIG. 1C, depicting wherein the auxiliary electrode 110 includes a second part that is located in a peripheral region B of the display device 10, [0015]);
a cathode layer (FIG. 1C, second electrode E2, [0022]) located on a side that is of the first electrode layer and that is away from the first substrate (FIG. 1C, depicting wherein the second electrode E2 is located on a side of the auxiliary electrode 110 that is away from the substrate 100),
the cathode layer comprising a first part that covering the display area of the display panel (FIGS. 3/1C, depicting wherein the second electrode E2 includes a first part that covers the active region A of the display device 10) and a second part extending to the border area of the display panel (FIGS. 3/1C, depicting wherein the second electrode E2 includes a second part that extends to the peripheral region B of the display device 10); and
an anode layer (FIG. 1C, first electrode E1, [0022]) located on a side of the cathode layer and that faces the first substrate (FIG. 1C, depicting wherein the first electrode E1 is located on a side of the second electrode E2 that is away from the substrate 100); and
a control circuit layer (FIG. 1C, depicting, e.g., a layer including an active element T2 and chip 210, [0014], [0022]) located on a side of the anode layer and that is away from the cathode layer (FIG. 1C, depicting wherein the layer including layer including an active element T2 and chip 210 is located on a side of the first electrode E1 that is away from the second electrode E2), wherein
in the display area,
one or more first vias directly connect the anode layer to the control circuit layer (FIGS. 1B/1C, depicting wherein the first electrode E1 is directly connected to the layer including an layer including an active element T2 and chip 210 by a via in an opening O2, [0022]), and
in the border area,
the second part of the first electrode layer is directly connected to the second part of the cathode layer (FIGS. 1B/1C, depicting wherein the second part of the auxiliary electrode 110 is directly connected to the second electrode E2 in the peripheral region B), and
the control circuit layer directly connects to the second part of the first electrode layer (FIGS. 1B/1C, depicting wherein the layer including an active element T2 and chip 210 is directly connected to the second electrode E2 in the peripheral region B).
Hsu does not specifically disclose wherein one or more second vias directly connect the first part of the cathode layer to the first part of the first electrode layer.
In the same field of endeavor, Liu discloses a display panel (FIGS. 14A/15/16, depicting a display substrate, [0297]) including a first electrode layer configuration wherein the first electrode layer (FIGS. 14A/15/16, auxiliary cathode layer 6, [0291]) includes a plurality of electrode lines (FIGS. 14A/15/16, depicting wherein the auxiliary cathode layer 6 is formed as a mesh structure formed from a plurality of auxiliary cathode layer 6 lines), and further wherein the first electrode layer is disposed between a control circuit layer and an anode layer (FIGS. 14A/15/16, depicting wherein the auxiliary cathode layer 6 formed as a mesh structure formed from a plurality of auxiliary cathode layer 6 lines is disposed between a driving circuit layer 85 and an anode pattern 4 layer). Liu states in [0146]: “On one hand, in order to ensure the transmittance of the cathode, the Mg/Ag metal is made very thin; on the other hand, the negative power signal line (VS S) electrically connected to the cathode in the related art is only a wiring line located at the edge of the display substrate. Therefore, the resistance of the cathode is relatively large (when the cathode is made of Mg/Ag alloy, the square resistance of the cathode is between 10 Ω/sq-15 Ω/sq). The IR Drop problem caused by the cathode leads to uneven display of the display substrate and the power consumption of the display substrate becomes larger.” Regarding the configuration of the first electrode 2, in [0164], Liu states: “In the display substrate provided by the foregoing embodiment, the space between the anode patterns 4 is used or the position of the anode pattern 4 is adjusted, so as to realize the rational layout of the first electrode 2 and interconnect with the upper cathode, which is equivalent to introducing a layer of an auxiliary electrode connected in parallel with the cathode to the display substrate, thereby effectively reducing the resistance of the cathode, and improving the IR Drop problem of the cathode.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed display device 10 of Hsu with by substituting the auxiliary cathode 6 layer configuration of Liu in order to reduce the resistance of the cathode and improve the IR drop problem of the cathode. See Liu [0164].
Moreover, substitution of the auxiliary cathode 6 layer configuration of Liu would result in a configuration wherein one or more second vias (Liu FIGS. 14A/15/16, depicting wherein the display substrate of Liu includes one or more vias Via3, [0389]) directly connect the first part of the cathode layer to the first part of the first electrode layer (Hsu FIGS. 3/1B/1C; Liu FIGS. 14A/15/16; depicting wherein the vias via3 would directly connect the first part of the second electrode E2 layer to the first part of the auxiliary electrode layer 110, as modified by Liu).
Regarding claim 15, Hsu in view of Liu further discloses a pixel definition layer (FIG. 1C, pixel defining layer 160, [0014]) and a light-emitting layer (FIG. 1C, light emitting layer EL, [0022]) that are located between the anode layer and the cathode layer (FIG. 1C, depicting wherein the pixel defining layer 160 and light emitting layer EL are located between the first electrode E1 and the second electrode E2), wherein the pixel definition layer comprises a plurality of pixel definition areas (FIGS. 1B/1C, depicting wherein the pixel defining layer 160 comprises a plurality of pixel definition areas), the light-emitting layer comprises a plurality of light-emitting units (FIGS. 1B/1C, depicting wherein the light emitting layer EL comprises a plurality of light-emitting units), and the light-emitting units are in a one-to-one correspondence with the pixel definition areas and are located in the pixel definition areas (FIGS. 1B/1C, depicting wherein the light emitting units of the light emitting layer EL are in a one-to-one correspondence with the pixel definition areas and are located in the pixel definition areas), and wherein a configuration of the first electrode layer differs based on a location of the first electrode layer at each of the plurality of light-emitting unit relative to a signal input end of the display panel, such that brightness of the display panel is more uniform (Hsu FIGS. 3/1B/1C; Liu FIGS. 14A/15/16, depicting wherein the configuration of the auxiliary electrode 110 layer, as modified by Liu, differs based on a location of the auxiliary electrode 110 at each of the light emitting units of the light emitting layer EL relative to an end of the display panel in which the semiconductor chip 210 is disposed, such that the brightness of the display device 10 is more uniform, as disclosed in [0146] and [0164] of Liu and [0038] of Hsu).
Regarding claim 16, Hsu in view of Liu further discloses wherein the first electrode layer (FIG. 1C, auxiliary electrode 110) is located on a side that is of the anode layer and that is away from the cathode layer (Hsu FIGS. 3/1B/1C; Liu FIGS. 14A/15/16; depicting wherein the auxiliary electrode 110 layer, as modified by Liu, is located on a side of the first electrode E1 and that is away from the second electrode E2).
Regarding claim 17, Hsu in view of Liu further discloses wherein the first electrode layer (FIG. 1C, auxiliary electrode 110) is located between the anode layer and the control circuit layer (Hsu FIGS. 3/1B/1C; Liu FIGS. 14A/15/16; depicting wherein the auxiliary electrode 110 layer, as modified by Liu, would be located between the first electrode E1 and the layer including an active element T2 and chip 210).
Regarding claim 18, Hsu in view of Liu further discloses wherein there is a first insulation layer between the control circuit layer and the first electrode layer (Hsu FIGS. 3/1B/1C; Liu FIGS. 14A/15/16, depicting wherein the auxiliary electrode 110 layer, as modified by Liu, would result in a configuration wherein an insulating layer 140 would be disposed between the layer including an active element T2 and chip 210 and the auxiliary electrode 110 layer, [0021]), and there is a second insulation layer between the first electrode layer and the anode layer (Hsu FIGS. 3/1B/1C; Liu FIGS. 14A/15/16, depicting wherein the auxiliary electrode 110 layer, as modified by Liu, would result in a configuration wherein an insulating layer 150 would be disposed between the auxiliary electrode 110 layer and the first electrode E2 layer, [0021]).
Regarding claim 19, Hsu in view of Liu further discloses wherein the one or more second vias respectively penetrate gap between adjacent light-emitting units (Hsu FIGS. 3/1B/1C; Liu FIGS. 14A/15/16, depicting wherein the auxiliary electrode 110 layer, as modified by Liu, would result in a configuration wherein the one or more vias Via3 would penetrate gaps between adjacent light emitting units of the light emitting layer EL as disclosed in Liu).
Regarding claim 20, Hsu in view of Liu further discloses wherein a projection of the first electrode layer on a plane on which the first substrate is located at least partially overlaps with a projection of the light-emitting layer on the plane on which the first substrate is located (Hsu FIGS. 3/1B/1C; Liu FIGS. 14A/15/16, depicting wherein the auxiliary electrode 110 layer, as modified by Liu, would result in a configuration wherein a projection of the auxiliary electrode 110 layer on a plane on which the substrate 100 is located at least partially overlaps with a projection of the light emitting layer EL on a plane on which the substrate 100 is located).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Publication Nos.: 2022/0173352 (disclosing a via connection between anode and auxiliary line similar to that of the instant application); 2019/0067396 (disclosing a via connection between anode and auxiliary line similar to that of the instant application); 2022/0416198 (disclosing a via connection between anode and auxiliary line similar to that of the instant application); 2022/0344440 (disclosing a via connection between anode and auxiliary line similar to that of the instant application).
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/ADAM D WEILAND/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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