Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on September 24, 2025 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 6, and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Sudo et al. (US PGPUB 2017/0303771 – “Sudo”) in view of Jachetta et al. (US Patent 7,474,852 – “Jachetta”) and Lim (US PGPUB 2004/0255111 – “Lim”).
With regard to Claim 1, Sudo discloses:
An endoscope arrangement (Sudo FIG. 1, endoscope system 1), comprising:
a camera head (Sudo FIG. 1, image pickup device 11) with at least one distally arranged image sensor (Sudo FIG. 1, light receiving portion 12);
an image processing unit (Sudo FIG. 1, signal processor 30) connected to the camera head via a connecting line (Sudo FIG. 1, connection cable 20), the connecting line having: a) at least one optical line (Sudo FIG. 1, optical fibers 21a and 21b) for transmitting image information (Sudo paragraph [0051], “optical fibers 21a and 21b that transmit the optical signal”) over one or more optical image channels (Sudo FIG. 1, electrooptic converters 18a/18b, optical fibers 21a/21b, and optoelectric converters 33a/33b defining one or more optical image channels), and
b) at least one electrical line (Sudo FIG. 1, metal wire 22c) for serial transmission of signals (Sudo paragraph [0063] “drive signal generating portion 32 generates the drive signal for driving the CMOS image pickup device 11, based on the reference clock generated by the reference clock generating portion 31. The drive signal generated by the drive signal generating portion 32 is transmitted through the metal wire 22c to the TG (timing generator) 14”); and
a main processor (Sudo FIG. 1, image processing portion 35) of the image processing unit (Sudo FIG. 1, signal processor 30) which is connected to at least one functional unit (Sudo FIG. 1, transmission amount change 19) of the camera head (Sudo FIG. 1, image pickup device 11) via the at least one electrical line (Sudo FIG. 1, metal wire 22b);
wherein the at least one electrical line (16) (Sudo FIG. 1, metal wire 22c) is configured to transmit signals which are fed to the image sensor (4) in the camera head (2) (Sudo FIG. 1, showing control signal from drive signal generating portion 32 fed into image pickup device 11), and b) a second control signal that is fed to the at least one functional unit in the camera head, the at least one functional unit including at least one of a memory, a sensor, or an actuating element (10) (Sudo paragraph [0032], “timing generator (TG) 14 generates a timing signal based on a drive signal from a drive signal generating portion 32 to be described later of the signal processor 30, and supplies the timing signal to the respective circuits inside the CMOS image pickup device 11, for example, the control circuit 13, the noise elimination portions 15a and 15b, and the A/D converters 16a and 16b.”).
Sudo does not explicitly disclose:
a line configured to transmit the signals which include a) at least one clock signal and a first control signal;
a converter of the image processing unit configured to combine the signals to be serially transmitted over the at least one electrical line;
a camera head converter of the camera head configured to separate the signals transmitted serially over the at least one electrical line.
Jachetta teaches:
a line configured to serially transmit the signals, which include a) at least one clock signal and a first control signal (Jachetta col. 3 line 65 – col. 4 line 1, “In addition to the combined data and control signals that are destined for the individual remote heads, the uplink stream from the base also has embedded within it, a master clock signal derived from a master clock source in the base”; Jachetta col. 12, lines 56-61, “interface port 109 also accepts input data 110 to be input to a parallel to serial converter 137 similar to that in the multi-head embodiment, which also provides for embedding of a master clock signal 147”),
a converter (Jachetta FIG. 15, parallel to serial converter 137) of the image processing unit (Jachetta FIG. 2, single unit base 165) configured to combine the signals to be serially transmitted (Jachetta FIG. 15, camera control and data I/O module 109; Jachetta col. 12, lines 56-61, “interface port 109 also accepts input data 110 to be input to a parallel to serial converter 137 similar to that in the multi-head embodiment, which also provides for embedding of a master clock signal 147”) over the at least one electrical line (Jachetta FIG. 2, electrical cables 104);
a camera head converter (Jachetta FIG. 4, serial to parallel conversion and clock recovery circuit 138 within head video and data processing unit 127) of the camera head (Jachetta FIG. 3, head 103, also shown in Jachetta FIG. 2, and shown as including a head video and data processing unit 127 shown in Jachetta FIG. 4) configured to separate the signals transmitted serially over the at least one electrical line (Jachetta FIG. 4, showing serial to parallel conversion circuit 138 receiving serial data stream 111 from electric cable 101 shown in Jachetta FIGs. 2-3 via the transceiver module 125 shown in Jachetta FIG. 3).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine Jachetta’s clock/data combination and serializer/deserializer circuits with the endoscope disclosed by Sudo. A person having ordinary skill in the art would be motivated to combine these prior art elements according to known methods to yield the predictable result of an endoscopic arrangement that frequency locks clocks through the system, in order coordinate operations (e.g., control transmission, etc.) throughout the endoscopic arrangement (see col. 3, line 65 – col. 4, line 8 of Jachetta).
Sudo in view of Jachetta do not explicitly teach:
a main processor which is connected to a coprocessor,
wherein the main processor is configured to transmit at least one of an operating program, a boot program, or control commands from the main processor to the coprocessor.
Lim teaches:
a main processor (Lim FIG. 9, main processor 100) is connected to a coprocessor (Lim FIG. 9, coprocessor 200),
wherein the main processor is configured to transmit at least one of an operating program, a boot program (Lim FIG. 10, block 513 and Lim paragraph [0082], “The main processor 100 reads code files of the boot module…and moves the read code files to the internal RAM 205 of the coprocessor 200”), or control commands from the main processor to the coprocessor.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine Lim’s boot control system with the endoscope arrangement taught by Sudo in view of Jachetta. A person having ordinary skill in the art would be motivated to combine these prior art elements according to known methods to yield the predictable result of an endoscope arrangement in which coprocessors are controlled during boot by a main processor, in order to avoid collisions/crashes that can result if different components utilize different boot programs during start up.
With regard to Claim 4, Sudo in view of Jachetta and Lim teach the features of Claim 1, as described above.
Sudo further discloses wherein the at least one electrical line comprises a two-wire line (Sudo FIG. 1, metal wire 22b and metal wire 22c).
With regard to Claim 6, Sudo in view of Jachetta and Lim teach the features of Claim 1, as described above.
Jachetta further teaches wherein the main processor (Jachetta FIG. 15, circuit 109; Jachetta col. 11 lines 13-14, “circuits 109 are programmable”; Examiner notes that the main processor 17 described in paragraph [0037] of the present specification is described as a field programmable gate array (FPGA), and thus may be any type of programmable circuit) feeds the signals (Jachetta FIG. 15, data 110) separately to the converter (Jachetta FIG. 15, parallel to serial converter 137).
With regard to Claim 9, Sudo in view of Jachetta and Lim teach the features of Claim 1, as described above.
Sudo further discloses wherein the at least one optical line includes a separate one of the optical lines for each respective one of the optical image channels (Sudo FIG. 1, separate optical fibers 21a and 21b defining separate optical image channels).
With regard to Claim 10, Sudo in view of Jachetta and Lim teach the features of Claim 1, as described above.
Sudo further discloses wherein at least one of the at least one optical line is associated with at least one of a dedicated optical fiber in the connecting line or a mode of a fiber (Sudo FIG. 1, separate optical fibers 21a and 21b in connection cable 20).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Sudo et al. (US PGPUB 2017/0303771 – “Sudo”) in view of Jachetta et al. (US Patent 7,474,852 – “Jachetta”), Lim (US PGPUB 2004/0255111 – “Lim”), and Khamphilavong et al. (US PGPUB 2018/0330848 – “Khamphilavong”).
With regard to Claim 11, Sudo in view of Jachetta and Lim teach the features of Claim 4, as described above.
Sudo in view of Jachetta and Lim do not explicitly teach wherein the two-wire line is a twisted pair, shielded twisted pair or coaxial cable.
Khamphilavong teaches wherein the two-wire line is a twisted pair, shielded twisted pair (Khamphilavong FIG. 3, twisted pair conductor assemblies 102/104 with insulators 112 within electrical cable 100; see also Khamphilavong FIG. 1, endoscope device 200 with electrical cable 100) or coaxial cable.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to substitute Khamphilavong’s insulated twisted pair conductors for Sudo’s metal wires 22b/22c in the endoscope arrangement taught by Sudo in view of Jachetta and Lim. A person having ordinary skill in the art would be motivated to make this simple substitution of one known element for another to obtain the predictable result of an endoscopic system having signal conductors that resist external electrical interference and provide insultation to the conducting wires.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Sudo et al. (US PGPUB 2017/0303771 – “Sudo”) in view of Jachetta et al. (US Patent 7,474,852 – “Jachetta”), Lim (US PGPUB 2004/0255111 – “Lim”), and Sugie et al. (US PGPUB 2022/0046248 – “Sugie”).
With regard to Claim 12, Sudo in view of Jachetta and Lim teach the features of Claim 1, as described above.
As described above, Jachetta teaches a serializer converter (Jachetta FIG. 15, parallel to serial converter 137) which combines the signals for serial transmission and a deserializer converter (Jachetta FIG. 4, serial to parallel conversion and clock recovery circuit 138) which separates the serial signal. However, Sudo in view of Jachetta and Lim, and specifically Jachetta, do not explicitly teach that the signals being converted from parallel to serial signals or vice versa are gigabit multimedia serial link (GMSL) signals.
Sugie teaches an endoscope (Sugie FIG. 14, endoscope surgery system 5113) that utilizes GMSL signals (Sugie paragraph [0167], “gigabit multimedia serial link (GMSL))… functions as a data transmission path”).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to utilize Sugie’s GMSL data transmission path with the electrical lines disclosed by Sudo in the endoscope arrangement taught by Sudo in view of Jachetta and Lim. A person having ordinary skill in the art would be motivated to combine these prior art elements according to known methods to yield the predictable result of an endoscope system capable of transmitting high-speed control signals over a cable between a controller and a camera head.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Sudo et al. (US PGPUB 2017/0303771 – “Sudo”) in view of Jachetta et al. (US Patent 7,474,852 – “Jachetta”), Lim (US PGPUB 2004/0255111 – “Lim”), and Adler et al. (US PGPUB 2006/0055793 – “Adler”).
With regard to Claim 13, Sudo in view of Jachetta and Lim teach the features of Claim 1, as described above.
Sudo in view of Jachetta and Lim do not explicitly teach wherein the at least one functional unit (in the camera head) includes a memory.
Adler teaches wherein the at least one functional unit (in camera head 300 shown in Adler FIG. 3) includes a memory (Adler FIG. 3, EPROM 350).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine Adler’s EPROM with the endoscope taught by Sudo in view of Jachetta and Lim. A person having ordinary skill in the art would be motivated to combine these prior art elements according to known methods to yield the predictable result of an endoscope with a camera head that is capable of reading operational parameters for its sensor, illumination system, etc. locally, thus providing the ability to substitute different camera heads for use with a single system controller (see Adler paragraph [0033]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Sudo et al. (US PGPUB 2017/0303771 – “Sudo”) in view of Jachetta et al. (US Patent 7,474,852 – “Jachetta”), Lim (US PGPUB 2004/0255111 – “Lim”), and Annampedu et al. (US PGPUB 2014/0204987 – “Annampedu”).
With regard to Claim 14, Sudo in view of Jachetta and Lim teach the features of Claim 9, as described above.
Sudo in view of Jachetta and Lim do not explicitly teach a serializer and a deserializer, the serializer and deserializer being connected upstream and downstream, respectively, of the respective one of the optical lines for the respective optical image channel, and being configured to transmit the respective optical image channel over the respective optical line.
Annampedu teaches a serializer (Annampedu FIG. 1A, serializer 106) and a deserializer (Annampedu FIG. 1A, deserializer 110), the serializer and deserializer being connected upstream (Annampedu FIG. 1A, data source 102) and downstream (Annampedu FIG. 1A, data destination 104), respectively, of the respective one of the optical lines for the respective optical image channel, and being configured to transmit the respective optical image channel over the respective optical line (Annampedu FIG. 1A, communication channel 108; Annampedu paragraph [0018], “communication channel 108…includes one or more transmission lines (e.g.,…optical fiber)”).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine Annampedu’s optical serializer/deserializer (SERDES) system with the endoscope arrangement taught by Sudo in view of Jachetta and Lim. A person having ordinary skill in the art would be motivated to combine these prior art elements according to known methods to yield the predictable result of an endoscopic system having high-speed data transmission between a processing unit and a camera head that mitigates the impact of channel loss (see Annampedu paragraphs [0003] – [0005]).
Response to Arguments
Applicant's arguments filed on September 24, 2025 have been fully considered but they are not persuasive.
On pages 6-9 of the September 24, 2025 response, and regarding independent Claim 1, Applicant asserts that a combination of Sudo (US PGPUB 2017/ 0303771) and Jachetta (US Patent 7,474,852) fails to teach an image processing unit connected to the camera head via a connecting line, the connecting line having: a) at least one optical line for transmitting image information over one or more optical image channels, and b) at least one electrical line for serial transmission of signals. More specifically, Applicant asserts on pages 6-7 that Sudo in view of Jachetta fail to teach a converter of the image processing unit configured to combine the signals to be serially transmitted over the at least one electrical line, and a camera head converter of the camera head configured to separate the signals transmitted serially over the at least one electric line. Examiner respectfully disagrees.
As described herein, Jachetta teaches a converter (Jachetta FIG. 15, parallel to serial converter 137) of the image processing unit (Jachetta FIG. 2, single unit base 165) configured to combine the signals to be serially transmitted (Jachetta FIG. 15, camera control and data I/O module 109; Jachetta col. 12, lines 56-61, “interface port 109 also accepts input data 110 to be input to a parallel to serial converter 137 similar to that in the multi-head embodiment, which also provides for embedding of a master clock signal 147”). Jachetta further teaches in FIG. 2 that serial signals can be transmitted over the at least one electrical line (Jachetta FIG. 2, electrical cables 104). Jachetta further teaches that serial data an electrical data cable 204 (Jachetta FIG. 1C), serial audio signals can be sent over an electrical audio cable 205 ( Jachetta FIG. 1C), and serial video data can be sent over an electrical video cable 206 (Jachetta FIG. 1C). As such, since Jachetta teaches extensive use of electrical cables in an electronic system, it would be obvious to a PHOSITA to make use of an electrical cable in place of the fiber optic cable 101 shown in Jachetta FIG. 11. Examiner also notes that the Applicant-cited passage from Jachetta col. 8, lines 39-43 of an ADC that converts information “into a serial stream, which is required for transmission over a fiber optic link” does not limit the output of parallel to serial converter 137 to use by fiber optics.
Applicant further asserts that a combination of Sudo and Jachetta fails to teach the at least one electrical line is configured to serially transmit the signals, which include a) at least one clock signal and a first control signal, which are fed to the image sensor in the camera head, and b) a second control signal that is fed to the at least one functional unit in the camera head, the at least one functional unit including at least one of a memory, a sensor, or an actuating element. Sudo in view of Jachetta teach the at least one electrical line is configured to serially transmit the signals, which include a) at least one clock signal and a first control signal (Jachetta col. 3 line 65 — col. 4 line 1, “In addition to the combined data and control signals that are destined for the individual remote heads, the uplink stream from the base also has embedded within it, a master clock signal derived from a master clock source in the base”; Jachetta col. 12, lines 56- 61, “interface port 109 also accepts input data 110 to be input to a parallel to serial converter 137 similar to that in the multi-head embodiment, which also provides for embedding of a master clock signal 147”), which are fed to the image sensor in the camera head (Sudo FIG. 1, showing control signal from drive signal generating portion 32 fed into image pickup device 11), and b) a second control signal that is fed to the at least one functional unit in the camera head, the at least one functional unit including at least one of a memory, a sensor, or an actuating element (Sudo paragraph [0032], “timing generator (TG) 14 generates a timing signal based on a drive signal from a drive signal generating portion 32 to be described later of the signal processor 30, and supplies the timing signal to the respective circuits inside the CMOS image pickup device 11, for example, the control circuit 13, the noise elimination portions 15a and 15b, and the A/D converters 16a and 16b.”).
On pages 8-9, Applicant asserts that it would not be obvious for a PHOSITA to combine Sudo with Jachetta to teach these features due to disparate approaches taken to preserve high-bandwidth usage (Sudo) and distributing information over optical fibers (Jachetta). However , Examiner has already shown that it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine Jachetta with Sudo in order to combine’ s clock/data combination and serializer/deserializer circuits with the endoscope disclosed by Sudo. A person having ordinary skill in the art would be motivated to combine these prior art elements according to known methods to yield the predictable result of an endoscopic arrangement that frequency locks clocks through the system, in order coordinate operations (e.g., control transmission, etc.) throughout the endoscopic arrangement (see col. 3, line 65 — col. 4, line 8 of Jachetta). Thus a motivation to combine Jachetta with Sudo has already been shown, and nothing in the record indicates that such a combination would result in inoperability of one with the other.
On page 10-11, Applicant asserts that dependent Claims 4, 6, and 9-14 do not cure the alleged deficiencies in the rejection of base Claim 1 without providing a rationale for this conclusion. Examiner maintains that Claims 4, 6, and 9-14 are rejected for depending on Claim 1, and do not present any allowable features, for reasons described herein.
Thus, the rejections presented in the August 5, 2025 final office action and herein are maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure includes:
Takahashi et al. (US PGPUB 2007/0274649 – “Takahashi”), which teaches in Takahashi FIG. 1 a main processor 15, which communicates with a signal processing circuit 41 via a coprocessor 31, such that the main processor 15 controls the signal processing circuit 41, which is connected to the imaging sensor 11 in the scope 10.
Talbert et a. (US PGPUB 2012/0133750 – “Talbert”), which teaches in Talbert FIG. 26 an imaging device 2602 with in image sensor 2606, having a clock circuit 2608 that controls timing of video/control signal transmission to a control unit 2632.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIM BOICE whose telephone number is (571)272-6565. The examiner can normally be reached Monday-Friday 9:00am - 5:00pm Eastern.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Anhtuan Nguyen can be reached at (571)272-4963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JIM BOICE
Examiner
Art Unit 3795
/JAMES EDWARD BOICE/Examiner, Art Unit 3795
/ANH TUAN T NGUYEN/Supervisory Patent Examiner, Art Unit 3795 10/31/2025