DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/10/2026 has been entered. Claims 1-4, 6-18 and 20-22 are currently pending in the application. Claims 8-18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to nonelected species, there being no allowable generic or linking claim. Claims 1-4, 6, 7 and 20-22 read in the elected species I, as asserted by the Applicant, are considered in the application. An action follows below:
Response to Arguments
In response to the rejections of independent claims 1 and 20 under 35 U.S.C. 102(a)(1) in the first set of rejections and, in the alternative, under 35 U.S.C. 103 in the second/alternative set of rejections in the previous Office action dated 05/08/2026, Applicant has amended claims 1 and 20 to include new limitations and provided on pages 16-18 of the amendment arguments that the cited references, Kim and Yang fail to teach the limitations currently added to these claims. The arguments have been fully considered, but they are not persuasive. In order to best respond, the examiner respectfully directs the applicant to the below detailed rejections, specifically the limitations currently added to these claims.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-4, 6, 7 and 20-22 are rejected under 35 U.S.C. 112(a), as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Note that, in order to satisfy its burden under the written description requirement, a patent application must disclose the full scope of the claim. Univ. of Rochester v. G.D. Searle & Co., 358 F.3d 916, 920 (Fed. Cir. 2004) (The purpose of the written description requirement is to “ensure that the scope of the right to exclude, as set forth in the claims, does not overreach the scope of the inventor’s contribution to the field of art as described in the patent specification.”.)
As per claim 1, this claim recites limitations, “wherein the connection line segments comprise a first sub-connection line segment and a second sub-connection line segment; the first sub-connection line segment and the second sub-connection line segment are arranged adjacent to each other, being adjacent in both the row direction and the column direction, and are spaced apart from each other in the first direction” in last 4 lines, which were not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor(s), at the time the application was filed, had possession of the claimed invention.
First, the terms, “a first sub-connection line segment” and “a second sub-connection line segment” of the above underlined limitations, are not even found or does not explicitly discuss in detail, so as to reasonably convey to one skilled in the relevant art that the inventor(s), at the time the application was filed, had possession of the claimed invention. Further, see the above bolded note.
Further, note that the [[annotated]] FIG. 5 of the present application on page 17 of the amendment filed 08/10/2026 includes the reference characters “S1” and “S2”, which were not shown in the original FIG. 5 and were not disclosed or discussed in detail in the original disclosure. Furthermore, the [[annotated]] FIG. 5 does not explicitly disclose in detail the first sub-connection line segment “S1” being a connection line segment 4 or a portion of a connection line segment 4 and the second sub-connection line segment “S2” being another connection line segment 4 or a portion of another connection line segment 4.
Second, in order to further consider, since the term “sub-connection line segment” can be construed as a portion of the term “connection line segment”, it is assumed in light of the [[annotated]] FIG. 5 that each connection line segment 4 comprises a first/right sub-connection line segment S1, a second/middle sub-connection line segment S1, and a third/left sub-connection line segment. The above underlined limitations include at least features, (i) “wherein all of the connection line segments comprise a common first sub-connection line segment and a common second sub-connection line segment; the common first sub-connection line segment and the common second sub-connection line segment are arranged adjacent to each other, being adjacent in both the row direction and the column direction, and are spaced apart from each other in the first direction” and (ii) “wherein some of the connection line segments comprise a common first sub-connection line segment and others of the connection line segments comprise a common second sub-connection line segment; the common first sub-connection line segment and the common second sub-connection line segment are arranged adjacent to each other, being adjacent in both the row direction and the column direction, and are spaced apart from each other in the first direction”, which were not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor(s), at the time the application was filed, had possession of the claimed invention. Further, see the above bolded note.
Accordingly, the original disclosure does not contain such description and details regarding to the above underlined limitations of this claim, so as to reasonably convey to one skilled in the relevant art that the inventor(s), at the time the application was filed, had possession of the claimed invention.
As per claims 2-4, 6, 7, 21 and 22, these claims are therefore rejected for at least the reason set forth in claim 1 above.
In addition to claim 21, this claim further recites limitations, “wherein the first sub-connection line segment and the second sub-connection line segment are staggered in the first direction, wherein the staggering indicates that, upon translation of the orthographic projection of the first sub- connection line segment on the base substrate along the second direction, the orthographic projection of the first sub-connection line segment and the orthographic projection of the second sub-connection line segment only partially overlap each other,” which were not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor(s), at the time the application was filed, had possession of the claimed invention. See the discussion in the rejection of claim 1 regarding to the terms, “the first sub-connection line segment” and “the second sub-connection line segment.” Further, Fig. 3 does not show the connection line segments 4 partially overlapping each other in the X-Y plane or in a plan view. Further, see the above bolded note. Accordingly, the original disclosure does not contain such description and details regarding to the above underlined limitations of this claim, so as to reasonably convey to one skilled in the relevant art that the inventor(s), at the time the application was filed, had possession of the claimed invention.
In addition to claim 22, this claim further recites a limitation, “the first sub-connection line segment and the second sub-connection line segment are located in the same layer as the anode of the light-emitting unit,” which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor(s), at the time the application was filed, had possession of the claimed invention. See the discussion in the rejection of claim 1 regarding to the terms, “the first sub-connection line segment” and “the second sub-connection line segment.” Further, see the above bolded note. Accordingly, the original disclosure does not contain such description and details regarding to the above underlined limitation of this claim, so as to reasonably convey to one skilled in the relevant art that the inventor(s), at the time the application was filed, had possession of the claimed invention.
As per claim 20, see the rejection of claim 1 for similar limitations.
Notice to Applicant(s)
Examiner notes that the specification is not the measure of invention. Therefore, limitations contained therein can’t be read into the claims for the purpose of avoiding the prior art. See In re Sporck, 55 CCPA 743, 386 F.2d 924, 155 USPQ 687 (1968).
Further, the names/ terms of the features/elements used in the pending application or pending claims may be different from the names/terms of the matching features/ elements of the prior arts; however, the matching features/ elements of the prior arts contain all characteristics/ functions of the features/elements DEFINED by the pending claims.
Note that in order to avoid confusion, the below citations in the below rejection(s) are mere one or more places in the reference to disclose the "claimed" limitation(s) and/or are directed to one or more of embodiments disclosed by the cited reference(s). In other words, the “claimed” features/limitations may be read in other places in the reference or other embodiments of the reference. In order to better understand how the claimed limitations are taught by the reference(s), a review of the entire reference(s) is suggested by the examiner. Applicant is reminded a prior art reference must be considered in its entirety, i.e., as a whole, including portions that would lead away from the claimed invention as not all relevant paragraphs may have been cited in the rejection. W.L. Gore & Associates, Inc. v. Garlock, Inc., 721 F.2d 1540, 220 USPQ 303 (Fed. Cir. 1983), cert. denied, 469 U.S. 851 (1984).
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
FIRST SET OF REJECTIONS:
Claims 1, 2, 7 and 20-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2020/0203587 A1; hereinafter Kim.)
Note that, in order to easily recognize the features/elements of the Kim reference corresponding to the claimed limitations/elements, Figs. 2, 5A and 6A of the Kim reference are annotated below.
As per claims 1 and 20, Kim discloses a display device (see at least Figs. 2, 4-7; ¶ 54:1-3) comprising a display panel (see at least Figs. 2, 4-7,) wherein the display panel comprises:
a base substrate [SUB; Figs. 2 and any of Figs. 6A/B, 7];
a third conductive layer located on one side of the base substrate (see at least any of Figs. 6-7, disclosing a third conductive layer comprising at least elements [PL1, PL2] and located on a top side of the base substrate SUB,) wherein the third conductive layer comprises first signal lines [PL1], orthographic projections of the first signal lines on the base substrate [SUB] are spaced apart in a first direction [DR1] and extend along a second direction [DR2], and the first direction intersects with the second direction (see at least Figs. 5A, 6A/B, 7;) and
a fourth conductive layer located on one side of the third conductive layer away from the base substrate (see at least any of Figs. 6A/B, 7, disclosing a fourth conductive layer comprising at least element [NE1] and located on the top side of the third conductive layer away from the base substrate SUB,) wherein the fourth conductive layer comprises connection line segments (see at least annotated Fig. 5A, disclosing a portion of NE1 corresponding the claimed connection line segment,) orthographic projections of the connection line segments on the base substrate extend along the first direction (see at least Fig. 5A and any of Figs. 6A/B, 7,) and a same one of the connection line segments is connected to multiple ones [[two]] of the first signal lines [PL1] through via holes [CT1], respectively (see at least Figs. 5A, 6, 7; ¶ 104:4-8;)
a first conductive layer located between the base substrate and the third conductive layer (see at least Figs. 5A, first modified 6A; ¶ 99, disclosing a first conductive layer comprising first conductive parts [GE1], provided in the layer [ILD1], and located between the base substrate [SUB] and the above-discussed third conductive layer,) wherein the first conductive layer comprises first conductive parts [GE1] (see the above discussion;)
a second conductive layer located between the first conductive layer and the third conductive layer (see at least Fig. 5A, first modified Fig. 6A; ¶ 99, disclosing a second conductive layer comprising second conductive parts [GE2], provided in the layer [ILD2], located between the above-discussed first conductive layer and the above-discussed third conductive layer, and spaced apart the above-discussed third conductive layer with a portion of the layer [ILD2] [as the claimed dielectric layer] in order to be not electrically connected to the above-discussed third conductive layer;)
a dielectric layer, located between the second conductive layer and the third conductive layer (see the above discussion; or see Kim at least modified 6A; ¶¶ 99, 101, disclosing a portion of the layer [ILD2] located between the above-discussed second conductive layer and the above-discussed third conductive layer, as the claimed dielectric layer;) and
a planarization layer [ILD3] located between the third conductive layer and the fourth conductive layer, wherein a thickness of the planarization layer is greater than a thickness of the dielectric layer (see Kim at least first modified Fig. 6A; ¶¶ 99, 101,)
wherein the first direction is a row direction [DR1], the second direction is a column direction [DR2] (see at least annotated Fig. 2, 5A, 6A,) and the fourth conductive layer comprises the connection line segments [the above-discussed portions of NE1] arranged in the row direction and the column direction (see at least annotated Fig. 2 disclosing pixels arranged in the row direction DR1 [e.g., pixels [PXL1_1, PXL2_1, PXL3_1 … PXLm_1] arranged in the first row, pixels [PXL1_2, PXL2_2, PXL3_2 … PXLm_2] arranged in the second row, and etc.; pixels arranged in the column direction DR2 [e.g., pixels [PXL1_1, PXL1_2, PXL1_3 … PXL1_n] arranged in the first column, pixels [PXL2_1, PXL2_2, PXL2_3 … PXL2-n] arranged in the second column, and etc.; further see at least annotated Figs. 2, 5A, 6A, disclosing the fourth conductive layer comprising some of the connection line segments [portions of NE1] arranged in the row direction DR1 [e.g., each of a first row of the connection line segments [portion of NE1] arranged between a corresponding pixel of the above-discussed first row of pixels and a corresponding pixel of the above-discussed second row of pixels, each of a second row of the connection line segments [portions of NE1] arranged between a corresponding pixel of the above-discussed second row of pixels and a corresponding pixel of the above-discussed third row of pixels, and etc.] and some of the connection line segments [portions of NE1] arranged in the column direction DR2 [e.g., each connection line segment of a first column of the connection line segments [portions of NE1] arranged between two corresponding adjacent pixels of the above-discussed first column of pixels, each connection line segment of a second column of the connection line segments [portions of NE1] arranged between two corresponding adjacent pixels of the above-discussed second column of pixels, and etc.], wherein each connection line segment [each portion of NE1] associates with a corresponding pixel;)
the connection line segments located in a same row are spaced apart in the row direction, and adjacent connection line segments in the same row are connected to different ones of the first signal lines (see the above discussion regarding to the “construed” connection line segments; further see annotated Figs. 2A, 5A, disclosing that the [[e.g., two]] connection line segments [portions of NE1] located in a same row are spaced apart in the row direction DR1, and adjacent connection line segments in the same row are connected to different ones of the first signal lines [e.g., a connection line segment [a portion of NE1] in the first row of the connection line segments [NE1] and the first column of the connection line segments [NE1] and between the pixels [PXL1_1, PXL1_2] are connected to two corresponding [e.g., first and second] first signal lines [PL1] and a connection line segment [a portion of NE1] in the first row of the connection line segments [portions of NE1] and the second column of the connection line segments [portions of NE1] and between the pixels [PXL2_1, PXL2_2] are connected to two corresponding [e.g., third and fourth] first signal lines [PL1];)
the connection line segments located in a same column are spaced apart in the column direction, and the connection line segments in the same column are connected to a same group of the first signal lines (see the above discussion regarding to the “construed” connection line segments; further see annotated Figs. 2A, 5A, disclosing that the connection line segments located in a same column are spaced apart in the column direction DR2 [e.g., the connection line segment [portion of NE1] between the pixels [PXL1_1, PXL1_2] and the connection line segment [portion of NE1] between the pixels [PXL1_2, PXL1_3] located in a same/first column are spaced apart in the column direction DR2 with the pixel [PXL1_2] therebetween], and the connection line segments in the same/first column are connected to a same group of two first signal lines PL1;)
wherein the connection line segments comprise a first sub-connection line segment and a second sub-connection line segment; the first sub-connection line segment and the second sub-connection line segment are arranged adjacent to each other, being adjacent in both the row direction [DR1] and the column direction [DR2], and are spaced apart from each other in the first direction [DR1] (see at least annotated Figs. 2, 5A, disclosing that, e.g., the connection line segment [the portion of NE1] between pixels [PXL1_1, PXL1_2] comprises a first sub-connection line segment S1 and the [[another]] connection line segment [the another portion of NE1] between pixels [PXL2-2, PXL2-3] comprises a second sub-connection line segment S2; the first sub-connection line segment S1 and the second sub-connection line segment S2 are arranged adjacent to each other, being adjacent in both the row direction [DR1] and the column direction [DR2], and are spaced apart from each other in the first direction [DR1].)
PNG
media_image1.png
696
957
media_image1.png
Greyscale
PNG
media_image2.png
748
943
media_image2.png
Greyscale
PNG
media_image3.png
742
1276
media_image3.png
Greyscale
As per claim 2, Kim discloses the first signal line [PL1] being a power line (see at least ¶ 104:4-11.)
As per claim 7, Kim discloses: wherein the display panel comprises pixel driving circuits arranged in rows and columns (see at least Figs. 2, 4;) the first signal lines [PL1] are provided in a one-to-one correspondence with multiple columns of the pixel driving circuits (see at least Figs. 2, 4, 5A;) and the pixel driving circuits are connected to corresponding first signal lines [PL1]; and multiple rows of the connection line segments [portions of NE1] are provided in a one-to-one correspondence with multiple rows of the pixel driving circuits (see at least Figs. 2, 4, 5A.)
As per claim 21, Kim discloses: wherein the first sub-connection line segment and the second sub-connection line segment are staggered in the first direction [DR1] (see the rejection of claim 1 for the first sub-connection line segment S1 and the second sub-connection line segment S2,) wherein the staggering indicates that, upon translation of the orthographic projection of the first sub-connection line segment on the base substrate along the second direction (see the rejection of claim 1 for the first sub-connection line segment S1 and the second sub-connection line segment S2,) the orthographic projection of the first sub-connection line segment and the orthographic projection of the second sub-connection line segment only partially overlap each other (see at least annotated Figs. 2, 5A, disclosing the orthographic projection of the first sub-connection line segment and the orthographic projection of the second sub-connection line segment only partially overlapping each other in a direction forming a certain acute angle relative with the first direction DR1 and/or the second direction DR2.)
As per claim 22, Kim discloses: wherein the display panel further comprises a light-emitting unit [LD], the light-emitting unit is provided with an anode [REL1], and the first sub- connection line segment [S1 of the portion of NE1; see the rejection of claim 1] and the second sub-connection line segment [S2 of the portion of NE1; see the rejection of claim 1] are located in the same layer as the anode of the light-emitting unit (see at least Fig. 7; ¶¶ 103-104, disclosing the anode [REL1] directly on the element NE1 and both the portion of the anode [REL1] in the contact hole CT1 and the element NE1 in the layer PSV; in the alternative, the anode [REL1] and the element NE1 both in a same multi-layer comprising elements [PSV, BRL, INS3].)
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Yang et al. (US 2016/0118420 A1; hereinafter Yang.)
As per claim 3, Kim discloses the display panel further comprises pixel driving circuits arranged in the first direction and the second direction (see at least Figs. 2, 4, disclosing the display panel further comprising pixel driving circuits of the pixels PXL arranged in the first direction DR1 and the second direction DR2, each pixel driving circuit comprising elements [T1-T7, Cst],) the pixel driving circuit comprises a driving transistor [T1], a capacitor [Cst] and a fourth transistor [T2], a first electrode of the capacitor [Cst] is connected to a gate of the driving transistor [T1], a second electrode of the capacitor [Cst] is connected to a power line [VDD/ELVDD/PL1], a second electrode of the fourth transistor [T2] is connected to a first electrode of the driving transistor [T1], and a first electrode of the fourth transistor is connected to a data line [Dj] (see at least Fig. 4;)
wherein the first conductive layer comprises first conductive parts [GE1] (see the above discussion,) orthographic projections of the first conductive parts on the base substrate are spaced apart in the first direction (see at least Figs. 5A, 6A,) and the first conductive parts are used to form the gate of the driving transistor and the first electrode of the capacitor [Cst] (see at least ¶¶ 97, 99;)
wherein the second conductive layer comprises second conductive parts [GE2], orthographic projections of the second conductive parts on the base substrate [SUB] are spaced apart in the first direction (see at least Figs. 5A, 6A,) the second conductive parts [GE2] are provided in a one-to-one correspondence with the first conductive parts [GE1] (see at least Fig. 5A,) the orthographic projections of the second conductive parts [GE2] on the base substrate [SUN] at least partially overlap with orthographic projections of corresponding first conductive parts [GE1] on the base substrate [SUB] (see at least Figs. 5A, 6A,) and the second conductive parts [GE2] are used to form the second electrode of the capacitor [Cst] (see at least Fig. 5A; ¶ 99;)
Accordingly, Kim discloses all limitations of this claim, but is silent to the above strikethrough limitations.
However, in the same field of endeavor, Yang discloses a related display panel comprising pixel driving circuits [2] (see Figs. 1-2,) each similar to the pixel driving circuit of the Kim reference (see the pixel driving circuit 2 shown in Fig. 2 of Yang and the pixel driving circuit shown in Fig. 4 of Kim,) wherein the third conductive layer further comprises the data line [16] (see at least Figs. 3-4; ¶¶ 36, 64, disclosing a third conductive layer comprising the data line [16], a driving voltage line [26/ELVDD],) wherein an orthographic projection of the data line on the base substrate extends along the second/vertical direction (see at least Fig. 3,) and the orthographic projection of the data line [16] on the base substrate is located between orthographic projections of two second conductive parts [C2] adjacent in the first/horizontal direction on the base substrate (see at least Figs. 1, 3.) Thus, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of invention of the pending application to easily recognize the Yang reference remedying for the deficiency of Kim or to modify the display panel of Kim to include the above strikethrough limitations, in view of the teaching in the Yang reference, to obtain the same predictable result.
As per claim 4, the above modified Kim in view of Yang obviously renders: wherein the orthographic projection of the data line on the base substrate intersects with the orthographic projections of the connection line segments on the base substrate (see Kim at least Fig. 5A, disclosing the orthographic projection of the power lines [PL1] on the base substrate intersecting with the orthographic projections of the connection line segments [NE1] on the base substrate; further see Yang at least Fig. 3 disclosing the orthographic projection of the data line [16] on the base substrate intersecting with the orthographic projections of the connection line segments [26’] on the base substrate.)
Claims 6 and 22 (alternative) are rejected under 35 U.S.C. 103 as being unpatentable over Kim.
As per claim 6, Kim discloses each connection line segment [a portion of NE1] connected to adjacent first signal lines [PL1] (see at least Fig. 5A) and the staggered connection line segments commonly connected to two adjacent first signal lines (see the above discussion in the rejection of claim 1 for the connection line segments arranged in the row direction and the column direction; further see at least Figs. 2, 5A, disclosing the connection line segments [portions of NE1] of adjacent rows and adjacent columns are staggered in the first direction [DR1], and the staggered connection line segments are commonly connected to two adjacent first signal lines [PL1].) Accordingly, Kim discloses each connection line segment [NE1] connected to two adjacent first signal lines [PL1], instead of four adjacent first signal lines, as claimed. In other words, Kim is silent to a particular number of adjacent first signal lines connected to each connection line segment being four, as claimed.
However, a change in size or range was judicially recognized as being within the level of ordinary skill in the art, In re Larson, 340 F.2d 965,968 (CCPA 1965); In re Dulberg, 289 F.2d 522, 523 (CCPA 1961); In re Rose, 105 USPQ 237 (CCPA 1955); and In re Reven, 156 USPQ 679 (CCPA 1968). Therefore, while Kim may not exemplify the particular number of adjacent first signal lines connected to each connection line segment being four, as claimed, one of ordinary skill in the art would have found it obvious to make the Kim display panel having the particular number of adjacent first signal lines connected to each connection line segment being four, as desired as claimed, to obtain the same predictable result.
As per claim 22, in the alternative for the case “a same layer” being a single layer, Kim discloses: wherein the display panel further comprises a light-emitting unit [LD], the light-emitting unit is provided with an anode [REL1], and the first sub- connection line segment [S1 of the portion of NE1; see the rejection of claim 1] and the second sub-connection line segment [S2 of the portion of NE1; see the rejection of claim 1] are located in the same multi-layer as the anode of the light-emitting unit (see at least Fig. 7; ¶¶ 103-104, disclosing the anode [REL1] electrically-and-directly connected the element NE1 and both the portion of the anode [REL1] in the contact hole CT1 and the element NE1 in the layer PSV; in the alternative, the anode [REL1] and the element NE1 both in a same multi-layer comprising elements [PSV, BRL, INS3].) Accordingly, Kim discloses all limitations of this claim except that Kim discloses the anode [REL1] and the element NE1 both in a same multi-layer, instead of [[assumed]] same single layer. However, one of ordinary skill in the art would have found it obvious to modify the Kim display panel having the anode [REL1] and the element NE1 both in a same single layer, as desired as claimed, to obtain the same predictable result of providing the same signal to both the anode [REL1] and the element NE1, either the anode [REL1] and the element NE1 both in a same multi-layer or a same single layer, as taught by the Kim reference.
SECOND/ ALTERNATIVE SET OF REJECTIONS:
Claims 1-4, 6, 7 and 20-22 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Yang.
As per claims 1 and 20, Kim discloses a display device (see at least Figs. 2, 4-7; ¶ 54:1-3) comprising a display panel (see at least Figs. 2, 4-7,) wherein the display panel comprises:
a base substrate [SUB; Figs. 2 and any of Figs. 6A/B, 7];
a third conductive layer located on one side of the base substrate (see at least any of Figs. 6-7, disclosing a third conductive layer comprising at least elements [PL1, PL2] and located on a top side of the base substrate SUB,) wherein the third conductive layer comprises first signal lines [PL1], orthographic projections of the first signal lines on the base substrate [SUB] are spaced apart in a first direction [DR1] and extend along a second direction [DR2], and the first direction intersects with the second direction (see at least Figs. 5A, 6A/B, 7;) and
a fourth conductive layer located on one side of the third conductive layer away from the base substrate (see at least any of Figs. 6A/B, 7, disclosing a fourth conductive layer comprising at least element [NE1] and located on the top side of the third conductive layer away from the base substrate SUB,) wherein the fourth conductive layer comprises connection line segments (see at least annotated Fig. 5A, disclosing a portion of NE1 corresponding the claimed connection line segment,) orthographic projections of the connection line segments on the base substrate extend along the first direction (see at least Fig. 5A and any of Figs. 6A/B, 7,) and a same one of the connection line segments is connected to multiple ones [[two]] of the first signal lines [PL1] through via holes [CT1], respectively (see at least Figs. 5A, 6, 7; ¶ 104:4-8;)
a first conductive layer located between the base substrate and the third conductive layer (see at least Figs. 5A, second modified 6A; ¶ 99, disclosing a first conductive layer comprising first conductive parts [GE1], provided in the layer [ILD1], and located between the base substrate [SUB] and the above-discussed third conductive layer,) wherein the first conductive layer comprises first conductive parts [GE1] (see the above discussion;)
a second conductive layer located between the first conductive layer and the third conductive layer (see at least Fig. 5A, second modified Fig. 6A; ¶ 99, disclosing a second conductive layer comprising second conductive parts [GE2], provided in the layer [ILD2], located between the above-discussed first conductive layer and the above-discussed third conductive layer, and spaced apart the above-discussed third conductive layer with a portion of the layer [ILD2] therebetween, in order to be not electrically connected to the above-discussed third conductive layer;)
a dielectric layer, located between the second conductive layer and the third conductive layer (see Kim at least second modified 6A; ¶¶ 99, 101, disclosing the layer [ILD2], as the dielectric layer, located between the above-discussed second conductive layer and the above-discussed third conductive layer; note that the claimed dielectric layer of this second/alternative set, in the alternative, is mapped to the layer [ILD2], which is different from the mapping in the first set of rejections;) and
a planarization layer [ILD3] located between the third conductive layer and the fourth conductive layer (see Kim at least second modified Fig. 6A; ¶¶ 99, 101,)
wherein the first direction is a row direction [DR1], the second direction is a column direction [DR2] (see at least annotated Fig. 2, 5A, 6A,) and the fourth conductive layer comprises the connection line segments [the above-discussed portions of NE1] arranged in the row direction and the column direction (see at least annotated Fig. 2 disclosing pixels arranged in the row direction DR1 [e.g., pixels [PXL1_1, PXL2_1, PXL3_1 … PXLm_1] arranged in the first row, pixels [PXL1_2, PXL2_2, PXL3_2 … PXLm_2] arranged in the second row, and etc.; pixels arranged in the column direction DR2 [e.g., pixels [PXL1_1, PXL1_2, PXL1_3 … PXL1_n] arranged in the first column, pixels [PXL2_1, PXL2_2, PXL2_3 … PXL2-n] arranged in the second column, and etc.; further see at least annotated Figs. 2, 5A, 6A, disclosing the fourth conductive layer comprising some of the connection line segments [portions of NE1] arranged in the row direction DR1 [e.g., each of a first row of the connection line segments [portion of NE1] arranged between a corresponding pixel of the above-discussed first row of pixels and a corresponding pixel of the above-discussed second row of pixels, each of a second row of the connection line segments [portions of NE1] arranged between a corresponding pixel of the above-discussed second row of pixels and a corresponding pixel of the above-discussed third row of pixels, and etc.] and some of the connection line segments [portions of NE1] arranged in the column direction DR2 [e.g., each connection line segment of a first column of the connection line segments [portions of NE1] arranged between two corresponding adjacent pixels of the above-discussed first column of pixels, each connection line segment of a second column of the connection line segments [portions of NE1] arranged between two corresponding adjacent pixels of the above-discussed second column of pixels, and etc.], wherein each connection line segment [each portion of NE1] associates with a corresponding pixel;)
the connection line segments located in a same row are spaced apart in the row direction, and adjacent connection line segments in the same row are connected to different ones of the first signal lines (see the above discussion regarding to the “construed” connection line segments; further see annotated Figs. 2A, 5A, disclosing that the [[e.g., two]] connection line segments [portions of NE1] located in a same row are spaced apart in the row direction DR1, and adjacent connection line segments in the same row are connected to different ones of the first signal lines [e.g., a connection line segment [a portion of NE1] in the first row of the connection line segments [NE1] and the first column of the connection line segments [NE1] and between the pixels [PXL1_1, PXL1_2] are connected to two corresponding [e.g., first and second] first signal lines [PL1] and a connection line segment [a portion of NE1] in the first row of the connection line segments [portions of NE1] and the second column of the connection line segments [portions of NE1] and between the pixels [PXL2_1, PXL2_2] are connected to two corresponding [e.g., third and fourth] first signal lines [PL1];)
the connection line segments located in a same column are spaced apart in the column direction, and the connection line segments in the same column are connected to a same group of the first signal lines (see the above discussion regarding to the “construed” connection line segments; further see annotated Figs. 2A, 5A, disclosing that the connection line segments located in a same column are spaced apart in the column direction DR2 [e.g., the connection line segment [portion of NE1] between the pixels [PXL1_1, PXL1_2] and the connection line segment [portion of NE1] between the pixels [PXL1_2, PXL1_3] located in a same/first column are spaced apart in the column direction DR2 with the pixel [PXL1_2] therebetween], and the connection line segments in the same/first column are connected to a same group of two first signal lines PL1;)
wherein the connection line segments comprise a first sub-connection line segment and a second sub-connection line segment; the first sub-connection line segment and the second sub-connection line segment are arranged adjacent to each other, being adjacent in both the row direction [DR1] and the column direction [DR2], and are spaced apart from each other in the first direction [DR1] (see at least annotated Figs. 2, 5A, disclosing that, e.g., the connection line segment [the portion of NE1] between pixels [PXL1_1, PXL1_2] comprises a first sub-connection line segment S1 and the [[another]] connection line segment [the another portion of NE1] between pixels [PXL2-2, PXL2-3] comprises a second sub-connection line segment S2; the first sub-connection line segment S1 and the second sub-connection line segment S2 are arranged adjacent to each other, being adjacent in both the row direction [DR1] and the column direction [DR2], and are spaced apart from each other in the first direction [DR1].)
Accordingly, Kim discloses all limitations of these claims, but is silent to “wherein a thickness of the planarization layer is greater than a thickness of the dielectric layer,” as claimed.
PNG
media_image4.png
742
1274
media_image4.png
Greyscale
However, in the same field of endeavor, Yang discloses a related display panel (see at least Figs. 1, 4/5) comprising a dielectric layer [the layer ILD1] located between the second conductive layer [the layer including elements [G1, G6]] and the third conductive layer [the layer including elements [16, 26]; see at least Figs. 3-4; ¶ 36, ¶ 64] (see at least Fig. 4/5;) and a planarization layer [PL] located between the above-discussed third conductive layer and the fourth conductive layer [the layer including elements 121] (see at least Fig. 4/5,) wherein a thickness of the planarization layer is greater than a thickness of the dielectric layer (see at least Fig. 4/5.)
Thus, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of invention of the pending application to easily recognize the Yang reference remedying for the deficiency, “a thickness of the planarization layer is greater than a thickness of the dielectric layer,” of Kim, or to modify the display panel of Kim to include the above underlined limitation, in view of the teaching in the Yang reference, to obtain the same predictable result.
As per claim 2, Kim discloses the first signal line [PL1] being a power line (see at least ¶ 104:4-11.)
As per claim 3, Kim further discloses the display panel further comprises pixel driving circuits arranged in the first direction and the second direction (see Kim at least Figs. 2, 4, disclosing the display panel further comprising pixel driving circuits of the pixels PXL arranged in the first direction DR1 and the second direction DR2, each pixel driving circuit comprising elements [T1-T7, Cst],) the pixel driving circuit comprises a driving transistor [T1], a capacitor [Cst] and a fourth transistor [T2], a first electrode of the capacitor [Cst] is connected to a gate of the driving transistor [T1], a second electrode of the capacitor [Cst] is connected to a power line [VDD/ELVDD/PL1], a second electrode of the fourth transistor [T2] is connected to a first electrode of the driving transistor [T1], and a first electrode of the fourth transistor is connected to a data line [Dj] (see Kim at least Fig. 4;)
wherein the first conductive layer comprises first conductive parts [GE1] (see the above discussion,) orthographic projections of the first conductive parts on the base substrate are spaced apart in the first direction (see Kim at least Figs. 5A, 6A,) and the first conductive parts are used to form the gate of the driving transistor and the first electrode of the capacitor [Cst] (see Kim at least ¶¶ 97, 99;)
wherein the second conductive layer comprises second conductive parts [GE2], orthographic projections of the second conductive parts on the base substrate [SUB] are spaced apart in the first direction (see Kim at least Figs. 5A, 6A,) the second conductive parts [GE2] are provided in a one-to-one correspondence with the first conductive parts [GE1] (see at least Fig. 5A,) the orthographic projections of the second conductive parts [GE2] on the base substrate [SUN] at least partially overlap with orthographic projections of corresponding first conductive parts [GE1] on the base substrate [SUB] (see Kim at least Figs. 5A, 6A,) and the second conductive parts [GE2] are used to form the second electrode of the capacitor [Cst] (see Kim at least Fig. 5A; ¶ 99;)
Accordingly, the above modified Kim discloses all limitations of this claim, but is silent to the above strikethrough limitations.
However, Yang further discloses the display panel comprising pixel driving circuits [2] (see Figs. 1-2,) each similar to the pixel driving circuit of the Kim reference (see the pixel driving circuit 2 shown in Fig. 2 of Yang and the pixel driving circuit shown in Fig. 4 of Kim,) wherein the third conductive layer further comprises the data line [16] (see at least Figs. 3-4; ¶¶ 36, 64, disclosing a third conductive layer comprising the data line [16], a driving voltage line [26/ELVDD],) wherein an orthographic projection of the data line on the base substrate extends along the second/vertical direction (see at least Fig. 3,) and the orthographic projection of the data line [16] on the base substrate is located between orthographic projections of two second conductive parts [C2] adjacent in the first/horizontal direction on the base substrate (see at least Figs. 1, 3.) Thus, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of invention of the pending application to easily recognize the Yang reference remedying for the deficiency of Kim or to modify the display panel of Kim to include the above strikethrough limitations, in view of the teaching in the Yang reference, to obtain the same predictable result.
As per claim 4, the above modified Kim in view of Yang obviously renders: wherein the orthographic projection of the data line on the base substrate intersects with the orthographic projections of the connection line segments on the base substrate (see Kim at least Fig. 5A, disclosing the orthographic projection of the power lines [PL1] on the base substrate intersecting with the orthographic projections of the connection line segments [NE1] on the base substrate; further see Yang at least Fig. 3 disclosing the orthographic projection of the data line [16] on the base substrate intersecting with the orthographic projections of the connection line segments [26’] on the base substrate.)
As per claim 6, Kim further discloses each connection line segment [NE1] connected to adjacent first signal lines [PL1] (see at least Fig. 5A) and the staggered connection line segments commonly connected to two adjacent first signal lines (see the above discussion in the rejection of claim 5 for the connection line segments arranged in the row direction and the column direction; further see at least Figs. 2, 5A, disclosing the connection line segments [NE1] of adjacent rows and adjacent columns are staggered in the first direction [DR1], and the staggered connection line segments are commonly connected to two adjacent first signal lines [PL1].) Accordingly, Kim discloses each connection line segment [NE1] connected to two adjacent first signal lines [PL1], instead of four adjacent first signal lines, as claimed. In other words, Kim in view of Yang is silent to a particular number of adjacent first signal lines connected to each connection line segment being four, as claimed.
However, a change in size or range was judicially recognized as being within the level of ordinary skill in the art, In re Larson, 340 F.2d 965,968 (CCPA 1965); In re Dulberg, 289 F.2d 522, 523 (CCPA 1961); In re Rose, 105 USPQ 237 (CCPA 1955); and In re Reven, 156 USPQ 679 (CCPA 1968). Therefore, while Kim may not exemplify the particular number of adjacent first signal lines connected to each connection line segment being four, as claimed, one of ordinary skill in the art would have found it obvious to make the Kim display panel having the particular number of adjacent first signal lines connected to each connection line segment being four, as desired as claimed, to obtain the same predictable result.
As per claim 7, Kim further discloses: wherein the display panel comprises pixel driving circuits arranged in rows and columns (see Kim at least Figs. 2, 4;) the first signal lines [PL1] are provided in a one-to-one correspondence with multiple columns of the pixel driving circuits (see Kim at least Figs. 2, 4, 5;), and the pixel driving circuits are connected to corresponding first signal lines [PL1]; and multiple rows of the connection line segments [NE1] are provided in a one-to-one correspondence with multiple rows of the pixel driving circuits (see Kim at least Figs. 2, 4, 5.)
As per claim 21, Kim discloses: wherein the first sub-connection line segment and the second sub-connection line segment are staggered in the first direction [DR1] (see the rejection of claim 1 for the first sub-connection line segment S1 and the second sub-connection line segment S2,) wherein the staggering indicates that, upon translation of the orthographic projection of the first sub-connection line segment on the base substrate along the second direction (see the rejection of claim 1 for the first sub-connection line segment S1 and the second sub-connection line segment S2,) the orthographic projection of the first sub-connection line segment and the orthographic projection of the second sub-connection line segment only partially overlap each other (see at least annotated Figs. 2, 5A, disclosing the orthographic projection of the first sub-connection line segment and the orthographic projection of the second sub-connection line segment only partially overlapping each other in a direction forming a certain acute angle relative with the first direction DR1 and/or the second direction DR2.)
As per claim 22, Kim discloses: wherein the display panel further comprises a light-emitting unit [LD], the light-emitting unit is provided with an anode [REL1], and the first sub- connection line segment [S1 of the portion of NE1; see the rejection of claim 1] and the second sub-connection line segment [S2 of the portion of NE1; see the rejection of claim 1] are located in the same layer as the anode of the light-emitting unit (see at least Fig. 7; ¶¶ 103-104, disclosing the anode [REL1] directly on the element NE1 and both the portion of the anode [REL1] in the contact hole CT1 and the element NE1 in the layer PSV; in the alternative, the anode [REL1] and the element NE1 both in a same multi-layer comprising elements [PSV, BRL, INS3].)
In the alternative of claim 22 for the case “a same layer” being a single layer, Kim discloses: wherein the display panel further comprises a light-emitting unit [LD], the light-emitting unit is provided with an anode [REL1], and the first sub- connection line segment [S1 of the portion of NE1; see the rejection of claim 1] and the second sub-connection line segment [S2 of the portion of NE1; see the rejection of claim 1] are located in the same multi-layer as the anode of the light-emitting unit (see at least Fig. 7; ¶¶ 103-104, disclosing the anode [REL1] electrically-and-directly connected the element NE1 and both the portion of the anode [REL1] in the contact hole CT1 and the element NE1 in the layer PSV; in the alternative, the anode [REL1] and the element NE1 both in a same multi-layer comprising elements [PSV, BRL, INS3].) Accordingly, Kim discloses all limitations of this claim except that Kim discloses the anode [REL1] and the element NE1 both in a same multi-layer, instead of [[assumed]] same single layer. However, one of ordinary skill in the art would have found it obvious to modify the Kim display panel having the anode [REL1] and the element NE1 both in a same single layer, as desired as claimed, to obtain the same predictable result of providing the same signal to both the anode [REL1] and the element NE1, either the anode [REL1] and the element NE1 both in a same multi-layer or a same single layer, as taught by the Kim reference.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jimmy H Nguyen whose telephone number is (571) 272-7675. The examiner can normally be reached on Monday-Friday 8:30AM-6PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Temesghen Ghebretinsae, can be reached at (571) 272-3017. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Jimmy H Nguyen/
Primary Examiner, Art Unit 2626
Prosecution Insights