DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 6 is objected to because of the following informalities:
Examiner notes that claim 6 recites “…a first circuit region comprises a stages of first gate drive units, and a second circuit region comprises (m-a) stages of second gate drive units, where a is a natural number greater than 1 and less than m, and m is a total number of stages of the first gate drive units and the second gate drive units;…” (emphasis added) which should be changed to read --…a first circuit region comprises (a) stages of first gate drive units, and a second circuit region comprises (m-a) stages of second gate drive units, where (a) is a natural number greater than 1 and less than (m) , and m is a total number of stages of the first gate drive units and the second gate drive units;…-- in order to place the claim in better form.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites the limitation "one of the first circuit regions" in lines 1-2 of the claim and "one of the second circuit regions" in line 2 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Examiner notes that Claim 7, which depends from claim 5, recites two first signal regions and two first signal regions and two second signal regions. Claim 8, however, is dependent upon claim 5 (and not 7) which does not provide for more than one first signal region or more than one second signal region.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (Wang – US Doc. No. 20210375173).
Regarding claim 1, Wang discloses a display substrate (Figure 1, element 100), comprising:
a base substrate (11) comprising a display area (A) and a bonding area located at a side of the display area (B), wherein the display area comprises first circuit signal lines (Figure 1, elements 12_A; see also Figure 2, element G) and a second circuit signal lines (Figure 1, elements 12_C; see also Figure 2, element G – note that both 12_A and 12_C are gate driver circuits and thus gate lines G extend from both 12_A and 12_C), and the bonding area comprises bonding signal pins (Figure 1, element B; see also Figure 6A - region B, elements Y1, J1, J2, X4, X51-X53, etc.);
a circuit structure layer located in the display area (see Figure 1, A; see also Figure 2 – note that there are circuit structures in the display area); the circuit structure layer comprises at least one first circuit region (Figure 1, element 12/12_A) and at least one second circuit region (12/12_C); the at least one first circuit region comprises at least one first gate drive circuit (12_A); the at least one second circuit region comprises at least one second gate drive circuit (12_C);
the at least one first gate drive circuit comprises a plurality of cascaded first gate drive units (Figure 2, element SR1-SR3, etc.; see also paragraph 0045), and the at least one second gate drive circuit comprises a plurality of cascaded second gate drive units (see Figure 5, elements SR1-SR2, etc.; see also paragraph 0046); the plurality of first gate drive units are sequentially arranged along a second direction, and the plurality of second gate drive units are sequentially arranged along the second direction (as shown in Figures 2 and 5; see also paragraphs 0045-0047); and
the first circuit signal lines are coupled with the plurality of first gate drive units and the bonding signal pins, and the second circuit signal lines are coupled with the plurality of second gate drive units and the bonding signal pins (see Figure 6A – note that X51-X53 are in the bonding area ‘B’ and are coupled to the data lines D; see also Figures 2 and 5 – note that the gate lines and the data lines are coupled to the gate lines G).
Regarding claim 2, Wang discloses all of the limitations of claim 1 as discussed in the claim 1 rejection above and further that the at least one first circuit region and the at least one second circuit region are misaligned in a first direction, and the first direction intersects with the second direction (as shown in Figure 5 – note that 12_A and 12_C are misaligned).
Regarding claim 3, Wang discloses all of the limitations of claim 2 as discussed in the claim 2 rejection above and further that an arrangement position of the at least one first circuit region in the second direction and an arrangement position of the at least one second circuit region in the second direction are at least partially discontinuous, and an arrangement position of the at least one first circuit region in the first direction and an arrangement position of the at least one second circuit region in the first direction are at least partially different (as shown in Figure 5 – note that 12_A and 12_C are separated in the first direction [read: horizontally] and are also not aligned in the second direction [read: vertically]).
Regarding claim 4, Wang discloses all of the limitations of claim 1 as discussed in the claim 1 rejection above and further that the base substrate further comprises a signal trace area located between the display area and the bonding area, the signal trace area comprises a plurality of signal buses (see annotated Figure 7A below – note that the area included in the dotted line is considered a ‘trace area’); the signal buses are respectively connected with the first circuit signal lines, the second circuit signal lines and the bonding signal pins (note that the pins in the bonding area B are connected to lines 15 and 16; see also paragraphs 0069-0070);
the first circuit signal lines are coupled with the plurality of first gate drive units and the bonding signal pins, the second circuit signal lines are coupled with the plurality of second gate drive units and the bonding signal pins, which comprises that the first circuit signal lines are connected with the plurality of first gate drive units, the signal buses and the bonding signal pins, and the second circuit signal lines are connected with the plurality of second gate drive units, the signal buses and the bonding signal pins (as show in Figures 2, 3, and 5; see also paragraphs 0055-0058).
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Regarding claim 5, Wang discloses all of the limitations of claim 1 as discussed in the claim 1 rejection above and further that the display area further comprises a first cascade signal line through which the at least one first gate drive circuit and the at least one second gate drive circuit are cascaded (as shown in annotated Figures 2 and 5 below).
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Regarding claim 18, Wang discloses all of the limitations of claim 1 as discussed in the claim 1 rejection above and further that the display area is substantially symmetrical about a center line in a first direction, and the first direction intersects with the second direction (as shown in Figure 7A – note that the display area is symmetrical about center line Z).
Regarding claim 19, Wang discloses all of the limitations of claim 1 as discussed in the claim 1 rejection above and further that the display area is rectangle, heart-shaped or elliptical (as shown in Figure 1 – note that display area A is circular, which is also an ellipse; see also paragraph 0041).
Regarding claim 20, Wang discloses a display apparatus, comprising the display substrate (Figure 1 element 100) according to claim 1 (see rejection of claim 1 above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (Wang – US Doc. No. 20210375173).
Regarding claim 16, Wang discloses all of the limitations of claim 1 as discussed in the claim 1 rejection above. Wang does not specifically recite that at least one of the first circuit signal lines and at least one of the second circuit signal lines are connected with a same bonding signal pin. Wang does, however, recite that the pins in the bonding area B are used for multiple data lines by multiplexing the data signal lines (see paragraph 0096).
It would have been obvious to use one pin in the bonding area to control multiple signal lines through multiplexing in order to reduce the bonding region size and reduce bezel size of the display, the combination yielding predictable results and no more than one of ordinary skill in the art would expect from such an arrangement.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (Wang – US Doc. No. 20210375173) in view of Park et al. (hereinafter Park – US Doc. No. 20210398488).
Regarding claim 17, Wang discloses all of the limitations of claim 1 as discussed in the claim 1 rejection above. Wang does not specifically recite that the bonding signal pins comprises power supply signal pins and clock signal pins, and the clock signal pins at least comprise a first clock signal pin and a second clock signal pin.
Park, in the same field of endeavor, discloses a display (Figure 1, element 100) including a bonding region (Figure 2, element PU) which includes power supply signal pins and clock signal pins (see paragraph 0082), and the clock signal pins at least comprise a first clock signal pin and a second clock signal pin (see Figure 2, elements CLP1 and CLP2; see also paragraph 0082).
It would have been obvious to combine the display as disclosed by Wang with signal pins as disclosed by Park, the combination yielding predictable results and no more than one of ordinary skill in the art would expect from such an arrangement. It would also allow the display substrate to encompass fewer necessary modules and thus lessen the footprint of the display substrate by allowing components to be located on a different substrate yet still communicate with the display substrate.
Allowable Subject Matter
Claims 6-7 and 10-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 6 is allowable since the claim recites the first cascade signal line comprises a first sub-cascade signal line and a second sub-cascade signal line, a first circuit region comprises a stages of first gate drive units, and a second circuit region comprises (m-a) stages of second gate drive units, where a is a natural number greater than 1 and less than m, and m is a total number of stages of the first gate drive units and the second gate drive units; an output signal end of a second gate drive unit in a first stage is connected with a reset signal input end of a first gate drive unit in a-th stage through the first sub-cascade signal line; and
an output signal end of the first gate drive unit in a-th stage is connected with a signal input end of the second gate drive unit in the first stage through the second sub-cascade signal line.
Claim 7 is allowable since the claim recites two first circuit regions are provided, and the two first circuit regions are arranged along a first direction; two second circuit regions are provided, and the two second circuit regions are arranged along the first direction; two groups of first cascade signal lines are provided;
one of the first circuit regions and one of the second circuit regions are cascaded by a group of the first cascade signal lines, and the other of the first circuit regions and the other of the second circuit regions are cascaded by the other group of the first cascade signal lines.
Claims 10 and 11-15 are allowed as being dependent upon aforementioned dependent claim 7.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM R GIESY whose telephone number is (571)272-7555. The examiner can normally be reached Mon-Fri 8-6.
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/ADAM R. GIESY/ Primary Examiner, Art Unit 2622