DETAILED ACTION
1. Claims 1-20 are pending in the application.
Claim Rejections - 35 USC § 112
2. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
3. Claims 1 and 12 are rejected under 35 U.S.C. 112(b) as being directed to unclear subject matter.
Claim 1 recites “m” in the claim, however there is no definition for “m” until claim 2. Claim recites m is an integer greater than or equal to 0. It is suggested that this be brought into the independent claim 1.
Claim 12 is rejected for similar reasons as claim 1.
Notice of Pre-AIA or AIA Status
4. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
5. 35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-11 are rejected under 35 U.S.C. 101 as being directed to non-statutory subject matter.
6. Claim 1 rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. As analyzed under the current 2019 Revised Patent Subject Matter Eligibility Guidance; first, the claim is directed to a proper statutory category. Second, under step 2A prong 1, the claim is directed to abstract ideas; specifically mathematical concepts such as mathematical calculations and/or mental processes possibly performed by pen and paper, i.e. generating a random sequence with logic operations. They are highlighted below (underlined, italicized):
1. A method for generating a pseudo-random sequence, comprising:
performing an AND operation and an XOR operation on M bit values of a first sequence to obtain an (A+m)th bit value of the first sequence, where M is an integer greater than or equal to 1, and A is an integer greater than or equal to 0; and
determining, according to the (A+m)th bit value of the first sequence, an mth bit value of the pseudo-random sequence.
As currently recited, under the broadest reasonable interpretation, these highlighted limitations can be interpreted as mathematical concepts and/or mental processes performed by pen and paper.
Next, under step 2A prong 2, are there additional elements or combination of elements that apply or integrate the judicial exception into a practical application? There are no additional limitations or combination of elements that apply or integrate the judicial exception into a practical application.
Lastly, under step 2B are there limitations indicative of an inventive concept (i.e. significantly more)? No, there are no additional limitations indicative of an inventive concept (i.e. significantly more). The claim is not patent eligible.
7. Dependent claims 2-11 are rejected under 35 U.S.C. 101 as non- statutory for at least the reason stated above, as they do not add any feature or subject matter that would solve the non-statutory deficiencies of the independent claims from which they depend. The claims depend from claim 1, but fail to include any additional elements sufficient to amount to significantly more than the judicial exception. The claims recite further limitations that abstract mathematical concepts and/or mental steps without reciting any additional limitations that make the claim any less abstract or that impose meaningful limits on practicing the abstract idea. Accordingly, the claims are not patent-eligible under 35 U.S.C. 101.
Claim Rejections - 35 USC § 102
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
9. Claim(s) 1, 6-8, and 10-12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Schooler et al (hereafter Schooler)(US Pub. 20030122697).
Schooler was cited in the IDS filed 08/09/2004
10. As to claim 1, Schooler discloses a method for generating a pseudo-random sequence ([0001]), comprising:
performing an AND operation (fig. 4 and [0071] and an XOR operation (fig. 4 and [0071]) on M bit values of a first sequence to obtain an (A+m)th bit value of the first sequence ([0072] Equation (9) shows that M code bits may be generated in parallel, requiring only that state inputs [N+M-1:0] and mask input [N-1:0] be known), where M is an integer greater than or equal to 1, and A is an integer greater than or equal to 0 (fig. 4 the bit positions M-1 to 0 are determined by dout, wherein M refers to the number of chips. M is at least 2); and
determining, according to the (A+m)th bit value of the first sequence, an mth bit value of the pseudo-random sequence ([0083] XOR reduction array 930 may be in the form to generate many PN sequence bits in parallel, as shown in Fig. 4. The new PN sequence bits may be store in bit accumulator 940).
11. As to claim 2, Schooler discloses wherein performing the AND operation and the XOR operation on M bit values of the first sequence to obtain the (A+m)th bit value of the first sequence comprises: performing an AND operation on an ith bit value in the M bit values and k^(mi) to obtain a corresponding ith intermediate bit value, where i is an integer greater than or equal to 1 and less than or equal to M, and k^(mi) is a proportionality coefficient corresponding to the ith bit value and m; where m is an integer greater than or equal to 0; and performing an XOR operation on M intermediate bit values to obtain the (A+m)th bit value of the first sequence ([0071] the AND gates generate intermediate values by combining state bits with corresponding mask bits wherein the output of the AND gates are fed to the XOR gates resulting in the pseudo random output to be stored).
12. As to claim 3, Schooler discloses determining k^(mi) according to a first correspondence relationship among i, m and k^(mi) ([0066] and [0071]-[0072]).
13. As to claims 4 and 13-14, Schooler discloses wherein the AND operation and the XOR operation corresponding to m of a same segment are performed in parallel, and determination of bit values belonging to a same segment in the pseudo-random sequence is performed in parallel, wherein each segment comprises N bit values of the pseudo-random sequence, where N is an integer greater than or equal to 2; and the segment is obtained by dividing the pseudo-random sequence ([0066], [0071], and [0072]).
14. As to claim 5, Schooler discloses wherein N is less than or equal to a maximum parallel number supported by a processor ([0072], generated in parallel).
15. As to claim 6, Schooler discloses wherein M is less than or equal to a bit width of a processor ([0072]-[0075).
16. As to claim 7, Schooler discloses wherein the M bit values comprise:
a jth bit value to a (j+M-1)th bit value, where j is an integer greater than or equal to 0 ([0072]-[0075]).
17. As to claims 8 and 15-16, Schooler discloses calculating, according to an initial value of the first sequence, M bit values of the first sequence ([0072]-[0075]).
18. As to claims 9 and 17-20, Schooler discloses acquiring, according to a preset second correspondence relationship between i and an ith bit value of a second sequence, an (A+m)th bit value of the second sequence, where i is an integer greater than or equal to 1 and less than or equal to M; accordingly, determining, according to the (A+m)th bit value of the first sequence, the mth bit value of the pseudo-random sequence comprises: determining, according to the (A+m)th bit value of the first sequence and the (A+m)th bit value of the second sequence, the mth bit value of the pseudo-random sequence ([0066] and [0071]-[0075]).
19. As to claims 10, 11, and 12, the claims are rejected for similar reasons as claim 1 above.
Conclusion
20. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Pat. 6526427 – related to calculating the mask for an arbitrary delay of a pseudo-noise sequence uses only XOR operations on previously calculated masks. A method for calculating the mask for an arbitrary delay of a pseudo-noise sequence whose shift register polynomial is of order R uses no more than N.sub.OP operations where N.sub.OP is independent of the delay and N.sub.OP is on the order of R.
US Pub. 20100070549 – related to a random number generator system, comprises a pre-processing unit, and a random number generation unit, wherein the pre-processing unit is adapted to calculate an internal seed out of an external seed and/or system variables and/or dynamic variables related to stack, and wherein the random number generation unit is adapted to generate a random number by using a determined function, wherein the determined function is a function of the internal seed and of at least one dynamic runtime variable related to the stack.
US Pub. 20150268933 – related to a bit sequence generator for generating a bit sequence defined by a generating function and an initial state of the generating function comprising a plurality of state machines and a multiplexer. Each state machine of the plurality of state machines generates a time-interleaved bit sequence, wherein a state machine generates a bit of the time-interleaved bit sequence for a current time step based on at least one bit generated by the state machine for a preceding time step, the generating function of the bit sequence to be generated, and the initial state of the generating function and independent from a time-interleaved bit sequence generated by another state machine of the plurality of state machines. Further, a multiplexer selects successively one bit from each generated time-interleaved bit sequence in a repetitive manner to obtain the bit sequence defined by the generating function and the initial state of the generating function.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL D YAARY whose telephone number is (571)270-1249. The examiner can normally be reached Mon-Fri 9-5:30.
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/MICHAEL D. YAARY/ Primary Examiner, Art Unit 2151
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