DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5-8, and 15-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yi et al. (US PG-Pub No.: 2022/0310743 A1, hereinafter, “Yi”).
Regarding claim 1, Yi discloses a display panel (see Yi, FIGs. 1A-1D) having a display region (100, FIG. 1A), the display region (100) including a first display region (100b, FIG. 1C) and a second display region (100a, FIG. 1C);
the display panel comprising:
a base substrate (108, FIG. 1C);
a driving circuit layer (lays comprising 102, FIG. 1C) disposed on a side of the base substrate (108); the driving circuit layer including a plurality of first-type pixel driving circuits (102, one is shown in FIG. 1C, but there are a plurality of 102 in FIG 1A) located in the first display region (100b);
a connection layer (201+202+104, FIG. 1C) including a plurality of connection lines (201/202/104); the plurality of connection lines including a plurality of first lines (202 for each pixel); and
an anode layer (106, ¶ [0090]) including a plurality of first-type anodes (106) located in the second display region (100a); wherein the plurality of first-type anodes (106) include a plurality of first anodes (106), and at least two first anodes (106 for two 1011, ¶ [0090]) are electrically connected to a first-type pixel driving circuit (102) via a first line (202, FIG. 1C).
Regarding claim 2, Yi discloses the display panel according to claim 1, wherein the plurality of connection lines (201/202/104) further include a plurality of third lines (104 for each pixel), a third line (104) is connected to the at least two first anodes (106), the first line (202) is connected to the third line (104) and the first-type pixel driving circuit (102), so that the at least two first anodes (106) are electrically connected to the first- type pixel driving circuit (102, FIG. 1C).
Regarding claim 3, Yi discloses the display panel according to claim 1, wherein the plurality of first-type anodes (106) further include a plurality of second anodes (anodes for some pixels in 100c and 100a) and a plurality of third anodes (anodes for some pixels in 100c and 100a); the plurality of connection lines (201/202/104) further include a plurality of second lines (another group of 202); a second anode (another 106) is electrically connected to another first-type pixel driving circuit (another 102) via a second line (202), and a third anode (a third 106) is electrically connected to yet another first-type pixel driving circuit (a third 102) via another second line (a third 202).
Regarding claim 5, Yi discloses the display panel according to claim 2, wherein the connection layer (201+202+104) is disposed on a side of the driving circuit layer (lays comprising 102) away from the base substrate (108); and the anode layer (106) is disposed on a side of the connection layer (201+202+104) away from the base substrate (108, FIG. 1C).
Regarding claim 6, Yi discloses the display panel according to claim 5, wherein the connection layer (to meet the limitation, 201+202+104+103+105) includes at least one conductive layer (202+104) and at least one insulating layer (105+103), and each conductive layer (202/104) is provided with an insulating layer (103/105) of the at least one insulating layer on a side away from the base substrate (108, FIG. 1C).
Regarding claim 7, Yi discloses the display panel according to claim 6, wherein the connection layer (201+202+104+103+105) includes: a first conductive layer (104) disposed on the side of the driving circuit layer (layers comprising 102) away from the base substrate (108); a first insulating layer (105) disposed on a side of the first conductive layer (104) away from the base substrate (108); a second conductive layer (202) disposed on a side of the first insulating layer (105) away from the base substrate (108); and a second insulating layer (103) disposed on a side of the second conductive layer (202) away from the base substrate (108); wherein the plurality of connection lines (201+202+104+103+105) further include a plurality of second lines, the first conductive layer (104) includes at least a part of the plurality of second lines, and the second conductive layer (202) includes at least a part of the plurality of first lines; the third line and the first line that are connected to each other are located in a same conductive layer; the first insulating layer (105) has first via holes therein, the second insulating layer (103) has second via holes therein, the first conductive layer (104) is electrically connected to the second conductive layer (202) through the first via holes, and the second conductive layer (202) is electrically connected to the anode layer (106) through the second via holes (FIG. 1C).
Regarding claim 8, Yi discloses the display panel according to claim 1, wherein the plurality of first-type anodes (106) are arranged in a plurality of first-type anode rows (many 106 for different pixels), and at least one first-type anode row includes at least two first anodes (two 106 in FIG. 1C), at least one second anode (106 for another pixel) and at least one third anode (106 for a third pixel) that are arranged in a row; at least two first anodes (two 106 in FIG. 1C) in a first-type anode row are electrically connected to a first line (201, FIG. 1C).
Regarding claim 15, Yi discloses a display apparatus, comprising: the display panel according to claim 1; and at least one sensor (¶ [0099]); the sensor being disposed on a non-display side of the display panel, and an orthographic projection of the sensor on the display panel is located in the second display region (100a, ¶ [0099]).
Regarding claim 16, Yi discloses a method of manufacturing a display panel (see Yi, FIGs. 1A-1D), wherein the display panel has a display region (100, FIG. 1A), and the display region (100) includes a first display region (100b, FIG. 1C) and a second display region (100a, FIG. 1C);
the method of manufacturing the display panel comprises:
providing a base substrate (108, FIG. 1C);
forming a driving circuit layer (lays comprising 102, FIG. 1C) on the base substrate (108); wherein the driving circuit layer includes a plurality of first-type pixel driving circuits (102, one is shown in FIG. 1C, but there are a plurality of 102 in FIG 1A), and the plurality of first-type pixel driving circuits are disposed in the first display region (100b);
forming a connection layer (201+202+104, FIG. 1C); wherein the connection layer includes a plurality of connection lines (201/202/104), and the plurality of connection lines include first lines (202) and second lines (104); and
forming an anode layer (106, ¶ [0090]); wherein the anode layer (106) includes a plurality of first-type anodes (106) located in the second display region (100a); the plurality of first-type anodes (106) include a plurality of first anodes, a plurality of second anodes and a plurality of third anodes, at least two first anodes are electrically connected to a first-type pixel driving circuit (102) via a first line, a second anode (106 for another pixel) is electrically connected to another first-type pixel driving circuit (another 102) via a second line, and a third anode (106 for a third pixel) is electrically connected to yet another first-type pixel driving circuit (a third 102) via another second line (FIG. 1C shows one pixel).
Regarding claim 17, Yi discloses the method of manufacturing the display panel according to claim 16, wherein the connection layer (to meet the limitation, 201/202/104/103/105) includes a first conductive layer (104), a first insulating layer (105), a second conductive layer (202) and a second insulating layer (103) that are sequentially arranged on a side of the driving circuit layer (102) away from the base substrate (108); forming the connection layer on the side of the driving circuit layer away from the base substrate includes: forming a first conductive material layer on the side of the driving circuit layer away from the base substrate; patterning the first conductive material layer by using a first mask, so as to form the first conductive layer having patterns; forming a first insulating material layer on a side of the first conductive layer away from the base substrate; patterning the first insulating material layer by using a second mask, so as to form the first insulating layer having patterns; forming a second conductive material layer on a side of the first insulating layer away from the base substrate; patterning the second conductive material layer by using a third mask, so as to form the second conductive layer having patterns; and forming a second insulating material layer on a side of the second conductive layer away from the base substrate and patterning the second insulating material layer by using a fourth mask, so as to form the second insulating layer having patterns; wherein patterns of the first conductive layer include at least a part of the second lines; patterns of the second conductive layer include at least a part of the first lines; patterns of the first insulating layer include first via holes; patterns of the second insulating layer include second via holes (FIG. 1C and see claim 7 for references).
Regarding claim 18, Yi discloses the display panel according to claim 7, wherein in a case where the second conductive layer (202) includes all of the plurality of first lines, the first conductive layer (104) includes a part or all of the plurality of second lines (FIG. 1C).
Regarding claim 19, Yi discloses the display panel according to claim 7, wherein in a case where the first conductive layer (104) includes a part of the plurality of second lines, and the second conductive layer includes a part of the plurality of first lines, the rest of the plurality of second lines are located in the second conductive layer, and the rest of the plurality of first lines are located in the first conductive layer (FIG. 1C).
Allowable Subject Matter
Claims 4, 9-14, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record neither anticipates nor renders obvious all the claimed subject of base claim 4, in particular, the at least two first anodes constitute a first anode group, and the first anode group, the second anode and the third anode are adjacent to one another; in the first anode group, the second anode and the third anode, a length of a first line electrically connected to the first anode group is less than a length of a second line electrically connected to the second anode, and is less than a length of a second line electrically connected to the third anode.
The prior art of record neither anticipates nor renders obvious all the claimed subject of base claim 9, in particular, first-type anodes in each of the at least one first-type anode row are cyclically arranged according to an order of a second anode, a first anode, a third anode and a first anode; the plurality of connection lines are arranged to constitute a plurality of line groups, and a line group includes at least one first line and at least two second lines; the plurality of connection lines each extend in a first direction, and the first direction is a row direction in which the plurality of first-type anodes are arranged; wherein in the line group, a first line is connected to the at least two first anodes in the first- type anode row, and a second line is connected to a second anode or a third anode in the first-type anode row; or in the line group, a first line is connected to the at least two first anodes in the first- type anode row, the at least two second lines in the line group include at least one first sub-line and at least one second sub-line, a first sub-line is connected to the second anode or the third anode in the first-type anode row, and a second sub-line is connected to a second anode or a third anode in another first-type anode row adjacent to the first- type anode row. Claims 11-14 depend upon claim 9.
The prior art of record neither anticipates nor renders obvious all the claimed subject of base claim 20, in particular, the plurality of first-type anodes are arranged in a plurality of first-type anode columns, and at least one first-type anode column includes at least two first anodes, at least one second anode and at least one third anode that are arranged in a column; at least two first anodes in a first-type anode column are electrically connected to a first line. Claim 10 depends upon claim 20.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIA L. CROSS whose telephone number is (571)270-3273. The examiner can normally be reached 9 am-5:30 pm.
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/XIA L CROSS/Primary Examiner, Art Unit 2892