Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
1. This Office Action responds to the Election of Restriction Requirement filed on 7/20/2026 and IDS filed on 2/9/2023, 8/14/2024, and 7/14/2025. Claims 1-7, 9-19, 21, and 22 are pending.
Election/Restrictions
Applicant’s election without traverse of Group I (Claims 1-7, 9-11, and 22) in the reply filed on 7/20/2026 is acknowledged.
Claims 12-19 and 21 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/20/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7, 9-11, and 22 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recited “applying an optimal bias configuration between the first
processing element and the second processing element to shuttle the qubit from the first processing element to the second processing element in a manner that minimizes the time spent by the qubit in one or more state transition points between the first processing element and the second processing element”, however it is not apparent how one would determine an optimal bias configuration in a manner that would minimizes the time spent by the qubit in one or more state transition points between the first processing element and the second processing element.
Claim 22 recited “each of the processing elements has a dwelling bias point at which coherence times of the qubit is highest…applying an optimal bias configuration between the first processing element and the second processing element such that the qubit dwells in each of the one or more transport elements at the dwelling bias point”, however it is not apparent how one would determine an optimal bias configuration that would allow the qubit to dwells in each of the one or more transport elements at the dwelling bias point. It is not apparent of the basis for determining that a dwelling bias point would result in coherence times of the qubit is highest. There is also lack of antecedent basis for the one or more transport elements. It is also not apparent of the relationship between transport elements and the processing element.
As per claims 2-7 and 9-11 are rejected to for incorporating the above limitations into the claims by dependency.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 6, 7, and 9-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bounacorsi (“Simulated coherent electron shuttling in silicon quantum dots”, by Brandon Buonacorsi, Benjamin Shaw, and Jonathan Baugh, Xiv:2003.08018v1 [quant-ph] 18 Mar 2020).
As per claim 1, Bounacorsi discloses:
A method for shuttling a qubit from a first processing element to a second processing element in a quantum processing device, the quantum processing device comprising a plurality of processing elements (See Abstract, i.e. Shuttling of single electrons in gate-defined silicon quantum dots), the method comprising:
applying an optimal bias configuration between the first processing element and the second processing element to shuttle the qubit from the first processing element to the second processing element (See Section I. Introduction, i.e. optimize both the device geometry and the voltage sequences for shuttling… shuttling of a single charge across a linear array of nine dots in 50 ns, See Section II, i.e. choose voltage configurations…pass through during the shuttling… configurations for shuttling through n dots, See Pages 8&9, i.e. device geometry optimization) in a manner that minimizes the time spent by the qubit in one or more state transition points between the first processing element and the second processing element (See Section I. Introduction, i.e. optimize both the device geometry and the voltage sequences for shuttling… shuttling of a single charge across a linear array of nine dots in 50 ns, See Section II, i.e. choose voltage configurations…pass through during the shuttling… configurations for shuttling through n dots, See Section III, i.e. tunnel coupling tc between two neighboring QDs determines the pulse length…a threshold time of 325 ps for dot-to-dot shuttling with a final orbital state fidelity > 99% - a factor of 5 improvement in speed over linear pulses, See Pages 8&9, i.e. device geometry optimization –[prior art optimize shuttling speed across dots (processing elements) , because the shuttle speed is increase overall, the time spent in the transition points would also be reduce therefore considered as the minimize as cited above]).
As per claim 6, Bounacorsi discloses all of the features of claim 1 as discloses above wherein Bounacorsi also discloses where the quantum processing device is a silicon based system (See Page 1-2, i.e. Shuttling of single electrons in gate-defined silicon quantum dots).
As per claim 7, Bounacorsi discloses all of the features of claim 6 as discloses above wherein Bounacorsi also discloses wherein the quantum processing device is a silicon MOS system and the plurality of processing elements are quantum dots with electron or hole encoding the qubit (See Page 1-2, i.e. Shuttling of single electrons in gate-defined silicon quantum dots, See Page 2&3, i.e. MOS geometry…MOS qubit).
As per claim 9, Bounacorsi discloses all of the features of claim 1 as discloses above wherein Bounacorsi also discloses correcting a phase error or rotation in the qubit by performing dynamical decoupling while the qubit is shuttled to the second processing element and/or once the qubit is shuttled to the second processing element (See Page 14, i.e. dominant error is a phase rotation, See Page 16, i.e. corrective phase rotations).
As per claim 10, Bounacorsi discloses all of the features of claim 1 as discloses above wherein Bounacorsi also discloses wherein the plurality of processing elements form a N X M matrix, where N and M are integer values (See Page 3, i.e. Consider a linear chain of n QDs –[chain of quantum dots would result in 1xn matrix]).
As per claim 11, Bounacorsi discloses all of the features of claim 1 as discloses above wherein Bounacorsi also discloses wherein the quantum processing device further comprising one or more exchange coupling gates arranged between pairs of processing or transport elements, the exchange coupling gate configurable to control the time taken by the qubit to transition from one element to another (See Section I. Introduction, i.e. optimize both the device geometry and the voltage sequences for shuttling… shuttling of a single charge across a linear array of nine dots in 50 ns, See Section II, i.e. choose voltage configurations…pass through during the shuttling… configurations for shuttling through n dots, See Pages 8&9, i.e. device geometry optimization).
Allowable Subject Matter
Claim 22 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Claims 2-5 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to independent claim 22, the prior art does not teach the method for shuttling a qubit from a first processing element to a second processing element in a quantum processing device having combination of features as recited in independent claim 22.
With respect to claims 2-5, the prior art does not teach the limitation of claim 2 and/or 4 – wherein claims 3 and 5 depend from claim 2.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NHA T NGUYEN whose telephone number is (571)270-1405. The examiner can normally be reached M-F 8:00AM-5:00PM.
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/NHA T NGUYEN/ Primary Examiner, Art Unit 2851
