DETAILED ACTION
Claims 1-11 and 26 are cancelled. Claims 12 and 24 are amended. Claims 12-25 are pending in the application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Examiner’s Notes
The Examiner cites particular sections in the references as applied to the claims below for the convenience of the applicant(s). Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant(s) fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Information Disclosure Statement
The listing of references in the specification is not a proper information disclosure statement (see the non-patent literature documents listed on pages 3-4). 37 CFR 1.98(b) requires a list of all patents, publications, or other information submitted for consideration by the Office, and MPEP § 609.04(a) states, "the list may not be incorporated into the specification but must be submitted in a separate paper." Therefore, unless the references have been cited by the examiner on form PTO-892, they have not been considered.
Claim Objections
Claims 24 and 25 are objected to because of the following informalities:
Claim 24: “unit;[” (line 3) should have been –unit;–.
Claim 25 inherits the features of claim 24 and is objected to accordingly.
Appropriate corrections are required. Applicant is advised to review the entire claims for further needed corrections.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12-25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 recites the limitation "the application program" in line 19. There is insufficient antecedent basis for this limitation in the claim. Specifically, it is not clear if this limitation is referring to the “first application program” or to the “second application program” as previously recited in the claim.
For the following analysis, the Examiner will consider the limitation “the application program” as referring to –the second application program—.
Claims 13-23 inherit the features of claim 12 and are rejected accordingly.
Claim 24 recites the limitation "the application program" in lines 25-26. There is insufficient antecedent basis for this limitation in the claim. Specifically, it is not clear if this limitation is referring to the “first application program” or to the “second application program” as previously recited in the claim.
For the following analysis, the Examiner will consider the limitation “the application program” as referring to –the second application program—.
Claim 25 inherits the features of claim 24 and is rejected accordingly.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 12-22, 24, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Nightingale (US 2013/0346985 A1) in view of Jodh (US 2006/0136890 A1).
With respect to claim 12, Nightingale teaches: A computer-implemented method for dynamically executing at least one application program by a platform (see e.g. Nightingale, Fig. 1: “100”) including a processor (see e.g. Nightingale, Fig. 1: “106”; and paragraph 18: “configuration of a processing unit, co-processor and memory is illustrated in FIG. 1 by dashed line 106”) comprising a program memory (see e.g. Nightingale, Fig. 1: “104”; and paragraph 15: “computing device 100 includes… memory 104”) and a programmable logic unit (see e.g. Nightingale, Fig. 1: “120”; and paragraph 16: “computing device also includes one or more field programmable gate arrays (FPGA), denoted as FPGA unit 120”), during the programming mode, a first application program (see e.g. Nightingale, Fig. 3: “Application 300”) comprising at least one first module being loaded into at least one of the program memory (see e.g. Nightingale, paragraph 24: “If an application relies on a hardware library 304, then the operating system 306 uses the hardware library to program the FPGA resources 310 to allow the application 300 to use the library”) and the programmable logic unit (see e.g. Nightingale, paragraph 24: “each FPGA can be considered a functional unit”) so as to be executable as at least one first program code from an application database (see e.g. Nightingale, Fig. 3: “Hardware Libraries 304”) and being programmed (see e.g. Nightingale, paragraph 24: “each functional unit is a resource that can be assigned to one or more processes, programmed by the operating system using a hardware library that implements an operation, and then used by the processes assigned to it to perform the operation… uses the hardware library to program the FPGA resources 310 to allow the application 300 to use the library”) and, during the execution mode, the at least one first program code is executed (see e.g. paragraph 24: “When the application makes calls to functions performed by the FPGA, the operating system… executes the function using the FPGA”), the method comprising:
checking during the execution mode (see e.g. Nightingale, paragraph 29: “The association between a functional unit and a process running an application can be made at… runtime”), one of the processor or the programmable logic unit on which the at least one first program code is executed, based on at least one predefined runtime criterion (see e.g. Nightingale, paragraph 30: “associating a functional unit with a process at runtime… determined 608 if the functional unit is being shared”) comprising a resource usage level of the processor or the programmable logic unit (see e.g. Nightingale, paragraph 24: “resources within the FPGA unit is one or more groups of programmable gates, herein called functional units… each functional unit is a resource that can be assigned to one or more processes”; and paragraph 30: “functional unit is associated 606 with the process executing the application. It is then determined 608 if the functional unit is being shared with other processes”), whether a second application program (see e.g. Nightingale, paragraph 30: “other processes”) comprising at least one second module should be loaded from the application database (see e.g. Nightingale, paragraph 30: “It is then determined 608 if the functional unit is being shared with other processes… If there is conflict with other processes sharing this functional unit, then the FPGA library can be queued 614 for loading into the FPGA”);
performing a change to the programming mode (see e.g. Nightingale, paragraph 32: “When programming the FPGA”), and loading at least the at least one second module into at least one of the program memory and the programmable logic unit so as to be executable as at least one second program code (see e.g. Nightingale, paragraph 30: “It is then determined 608 if the functional unit is being shared with other processes…If there is conflict with other processes sharing this functional unit, then the FPGA library can be queued 614 for loading into the FPGA”; paragraph 32: “When programming the FPGA, a scheduler can consider whether other processes are using the FPGA, and whether programming the FPGA involves pausing those other processes (after their use of the FPGA has completed). As an example, the scheduler can wait until a process has become dormant, or has not been using the FPGA, to initiate programming the FPGA”; and Fig. 6, steps 614, 616), if the second application program comprising at least one second module should be loaded from the application database (see e.g. Nightingale, paragraph 30: “If there is conflict with other processes sharing this functional unit, then the FPGA library can be queued 614 for loading into the FPGA”),
implementing a change to the execution mode, in which the at least one second program code is executed (see e.g. Nightingale, paragraph 30: If there is conflict with other processes sharing this functional unit, then the FPGA library can be queued 614 for loading into the FPGA. A scheduler within the operating system is then invoked 616 to determine when the FPGA library can be loaded to program the functional unit, and subsequently when the application can be executed 612”; and Fig. 6, step 612) instead of the at least one first program code (see e.g. Nightingale, paragraph 30: “A scheduler within the operating system is then invoked 616 to determine when the FPGA library can be loaded to program the functional unit”; and paragraph 33: “the scheduler can detect that two processes are using a same functional unit but with different hardware libraries. In such a case, the scheduler can signal an exception, in response to which one of the processes uses a software library instead of a hardware library”), if the second application program comprising at least one second module should be loaded from the application database (see e.g. Nightingale, paragraph 30: “If there is conflict with other processes sharing this functional unit, then the FPGA library can be queued 614 for loading into the FPGA”);
wherein the programming mode comprises at least one of loading (i) executable program code into the program memory for execution by the processor (see e.g. Nightingale, paragraph 23: “An operating system executed on a computing device”, paragraph 15: “computing device 100 includes at least one processing unit 102, such as a typical central processing unit (CPU) of a general purpose computer”, paragraph 27: “System calls or standard library calls, normally executed in a general purpose CPU”, and Fig. 3) and (ii) executable logic configuration data into the programmable logic unit for execution by the programmable logic unit (see e.g. Nightingale, paragraph 4: “An FPGA can be programmed to perform functions… programming the FPGA in accordance with the functions to be performed by the processes using the FPGA” and paragraph 24: “one of the resources within the FPGA unit is one or more groups of programmable gates, herein called functional units… each functional unit is a resource that can be assigned to one or more processes, programmed by the operating system using a hardware library that implements an operation… The FPGA can be programmed”); and
wherein the execution mode comprises executing at least one of the loaded executable program code (see e.g. Nightingale, paragraph 24: “The operating system 306 also executes software commands from the application 300 and software libraries 302 on the CPU 308… When the application makes calls to functions performed by a software library, the operating system executes the function from the software library on the CPU 308”) and the loaded executable logic configuration data (see e.g. Nightingale, paragraph 24: “an application 300 can use conventional software libraries 302, and FPGA hardware libraries 304, to perform various operations… When the application makes calls to functions performed by the FPGA, the operating system ensures that the FPGA is programmed using the hardware library and executes the function using the FPGA”).
Nightingale discloses programming an FPGA and corresponding functional units 202-206 (i.e. programming mode) and executing processes utilizing the FPGA functional units (i.e. execution mode). Nightingale further discloses determining FPGA functional units, which are resources assigned to processes, that are to be shared between the processes (i.e. a criteria to determine functional unit usage levels by the processes) and programming the FPGA functional units by loading corresponding libraries in order to enable the processes to share the functional units during execution.
Nightingale but Jodh teaches:
the at least one second program code being a different implementation of the application program than the at least one first program code (see e.g. Jodh, paragraph 6: “one application may load one version of a DLL file, while another instance of the same application loads a different version of the same DLL file”); and
Nightingale and Jodh are analogous art because they are in the same field of endeavor: loading libraries required by processes for execution. Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Nightingale with the teachings of Jodh. The motivation/suggestion would be to provide combability with different versions of processes that might require different versions of the libraries; thus increasing the overall flexibility of the system.
With respect to claim 13, Nightingale as modified teaches: The method as claimed in claim 12, wherein a usage level of one of (i) the processor (see e.g. Nightingale, paragraph 32: “ When programming the FPGA, a scheduler can consider… whether programming the FPGA involves pausing those other processes… a process has become dormant”), (ii) the working memory and the program memory of the processor and (ii) the programmable logic unit are determined (see e.g. Nightingale, paragraph 32: “When programming the FPGA, a scheduler can consider whether other processes are using the FPGA”; and paragraph 33: “scheduler also can consider how long it takes to program the FPGA, and whether programming the FPGA will result in a functional unit being programmed differently for different processes over time”) and accordingly taken into consideration during the execution of the first application program during the check to determine whether the second application program should be loaded (see e.g. Nightingale, paragraph 30: “This functional unit is associated 606 with the process executing the application. It is then determined 608 if the functional unit is being shared with other processes… If there is conflict with other processes sharing this functional unit, then the FPGA library can be queued 614 for loading into the FPGA”; and paragraph 32: “When programming the FPGA, a scheduler can consider whether other processes are using the FPGA”).
With respect to claim 14, Nightingale as modified teaches: The method as claimed in claim 12, wherein a usage level of one of (i) the processor (see e.g. Nightingale, paragraph 32: “ When programming the FPGA, a scheduler can consider… whether programming the FPGA involves pausing those other processes… a process has become dormant”), (ii) the working memory and program memory of the processor and (iii) the programmable logic unit is calculated, estimated and accordingly taken into consideration (see e.g. Nightingale, paragraph 32: “When programming the FPGA, a scheduler can consider whether other processes are using the FPGA”; and paragraph 33: “scheduler also can consider how long it takes to program the FPGA, and whether programming the FPGA will result in a functional unit being programmed differently for different processes over time”) during the execution of the second application program during the check to determine whether the second application program should be loaded (see e.g. Nightingale, paragraph 30: If there is conflict with other processes sharing this functional unit, then the FPGA library can be queued 614 for loading into the FPGA. A scheduler within the operating system is then invoked 616 to determine when the FPGA library can be loaded to program the functional unit, and subsequently when the application can be executed 612”; paragraphs 32-33).
With respect to claim 15, Nightingale as modified teaches: The method as claimed in claim 13, wherein at least one of the processor and the programmable logic unit is utilized to define whether at least one of the first and second module should be stored in one of the program memory and the programmable logic unit during the execution mode (see e.g. Nightingale, paragraph 30: “A scheduler within the operating system is then invoked 616 to determine when the FPGA library can be loaded to program the functional unit, and subsequently when the application can be executed 612”; paragraph 32: “a scheduler can consider whether other processes are using the FPGA, and whether programming the FPGA involves pausing those other processes (after their use of the FPGA has completed). As an example, the scheduler can wait until a process has become dormant, or has not been using the FPGA, to initiate programming the FPGA”; and paragraph 27).
With respect to claim 16, Nightingale as modified teaches: The method as claimed in claim 14, wherein at least one of the processor and the programmable logic unit is utilized to define whether at least one of the first and second module should be stored in one of the program memory and the programmable logic unit during the execution mode (see e.g. Nightingale, paragraph 30: “A scheduler within the operating system is then invoked 616 to determine when the FPGA library can be loaded to program the functional unit, and subsequently when the application can be executed 612”; paragraph 32: “a scheduler can consider whether other processes are using the FPGA, and whether programming the FPGA involves pausing those other processes (after their use of the FPGA has completed). As an example, the scheduler can wait until a process has become dormant, or has not been using the FPGA, to initiate programming the FPGA”; and paragraph 27).
With respect to claim 17, Nightingale as modified teaches: The method as claimed in claim 12, wherein an application management module (see e.g. Nightingale, paragraph 26: “a scheduler”), which is executed by a management system (see e.g. Nightingale, paragraph 26: “operating system has a scheduler that determines which process has access to the FPGA resources at each scheduling quantum, i.e., time period, and when an FPGA functional unit will be programmed with a hardware library so that the functional unit is available to be used by that process”) contained in the platform and which is incorporated into a connection between the application database and the processor and the programmable logic unit, defines whether at least one of (i) the first and (ii) the at least one second module is stored in one of the program memory and the programmable logic unit during the execution mode (see e.g. Nightingale, paragraph 30: “A scheduler within the operating system is then invoked 616 to determine when the FPGA library can be loaded to program the functional unit, and subsequently when the application can be executed 612”; paragraph 32: “a scheduler can consider whether other processes are using the FPGA, and whether programming the FPGA involves pausing those other processes (after their use of the FPGA has completed). As an example, the scheduler can wait until a process has become dormant, or has not been using the FPGA, to initiate programming the FPGA”).
With respect to claim 18, Nightingale as modified teaches: The method as claimed in claim 12, wherein the at least one second module loaded so as to be executable comprises a corresponding second processor program code for execution by the processor in the program memory (see e.g. Nightingale, paragraph 23: “running an application on the computer system causes one or more processes to be created, with each process being allocated to different resources over time”; paragraph 25: “another process can start using functional unit”), and a corresponding second logic program code for execution by the programmable logic unit in the programmable logic unit (see e.g. Nightingale, paragraph 24: “each functional unit is a resource that can be assigned to one or more processes, programmed by the operating system using a hardware library that implements an operation, and then used by the processes assigned to it to perform the operation”; and paragraph 30: “If there is conflict with other processes sharing this functional unit, then the FPGA library can be queued 614 for loading into the FPGA. A scheduler within the operating system is then invoked 616 to determine when the FPGA library can be loaded to program the functional unit, and subsequently when the application can be executed 612”).
With respect to claim 19, Nightingale as modified teaches: The method as claimed in claim 12, wherein the predefined criterion comprises one of an exceedance of an operative limit value of the platform, reaching a predefined state for the first application program (see e.g. Nightingale, paragraph 26: “ factor to consider is whether processes can share a hardware library by sharing a functional unit”; and paragraph 30: “It is then determined 608 if the functional unit is being shared with other processes. If not, the FPGA library can be scheduled for loading 610 into this functional unit, after which the application can execute 612. If there is conflict with other processes sharing this functional unit, then the FPGA library can be queued 614 for loading into the FPGA”), triggering an alarm or a fault notification on the platform and reaching a predefined time.
With respect to claim 20, Nightingale as modified teaches: The method as claimed in claim 12, wherein at least two application programs are executed dynamically (see e.g. Nightingale, paragraph 30: “The association between a functional unit and a process running an application can be made at… runtime. The association can be… dynamic”; and paragraph 30: “process executing the application. It is then determined 608 if the functional unit is being shared with other processes… If there is conflict with other processes sharing this functional unit”).
With respect to claim 21, Nightingale as modified teaches: The method as claimed in claim 20, wherein at least three application programs are executed dynamically (see e.g. Nightingale, paragraph 30: “The association between a functional unit and a process running an application can be made at… runtime. The association can be… dynamic”; and paragraph 30: “process executing the application. It is then determined 608 if the functional unit is being shared with other processes… If there is conflict with other processes sharing this functional unit”).
Nightingale discloses executing “other processes” dynamically which encompasses any number of additional processes for executing dynamically. As such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to realize at least three processes to execute dynamically. The motivation/suggestion would be to accommodate different number of processes for execution; thus improving the overall processing efficiency.
With respect to claim 22, Nightingale as modified teaches: The method as claimed in claim 21, wherein at least five or at least ten application programs are executed dynamically (see e.g. Nightingale, paragraph 30: “The association between a functional unit and a process running an application can be made at… runtime. The association can be… dynamic”; and paragraph 30: “process executing the application. It is then determined 608 if the functional unit is being shared with other processes… If there is conflict with other processes sharing this functional unit”).
Nightingale discloses executing “other processes” dynamically which encompasses any number of additional processes for executing dynamically. As such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to realize at least five and/or at least ten processes to execute dynamically. The motivation/suggestion would be to accommodate different number of processes for execution; thus improving the overall processing efficiency.
With respect to claims 24-25: Claims 24 and 25 are directed to a system configured to implement active functions corresponding to the method disclosed in claims 12 and 17, respectively; please see the rejections directed to claims 12 and 17 above which also cover the limitations recited in claims 24 and 25. Note that, Nightingale also discloses a system (see e.g. Nightingale, Fig. 1) configured to implement the method disclosed in claims 12 and 17.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Nightingale in view of Jodh as applied to claim 12 above, and further in view of Espinosa et al. (US 2011/0107158 A1; hereinafter “Espinosa”).
With respect to claim 23, Nightingale as modified teaches: The method as claimed in claim 12, … wherein the at least one first and at least one second program code are different (see e.g. Nightingale, paragraph 25: “use of multiple functional units at the same time by different processes… multiple functional units being used by different processes at the same time”).
Nightingale does not but Espinosa teaches:
wherein the first and the second application program are identical (see e.g. Espinosa, paragraph 36: “the same code, instructions or application is run on two identical components (i.e., the two Xilinx®, FPGAs)”); and
Nightingale and Espinosa are analogous art because they are in the same field of endeavor: managing and distributing FPGA resources. Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Nightingale with the teachings of Espinosa. The motivation/suggestion would be to improve data analysis and possible error corrections associated with application program execution (see e.g. Espinosa, paragraph 36).
Response to Arguments
Applicant’s arguments with respect to the limitation “the at least one second program code being a different implementation of the application program than the at least one first program code” recited in claim 12, and the similar limitations recited in claim 24, have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
CONCLUSION
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Kajigaya (US 2016/0132343 A1) discloses determining when a library version used by an application server which provides an execution environment for an application is different from a library version used by the application and loading a corresponding library for the application server in response to a load request (see paragraph 4).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Umut Onat whose telephone number is (571)270-1735. The examiner can normally be reached M-Th 9:00-7:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kevin L Young can be reached at (571) 270-3180. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/UMUT ONAT/Primary Examiner, Art Unit 2194
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